Andreas Färber 0c591eb0a9 cputlb: Change tlb_set_page() argument to CPUState 12 年之前
..
Makefile.objs 5b50e790f9 cpu: Introduce CPUClass::gdb_{read,write}_register() 12 年之前
README 45664345fa lm32: todo and documentation 14 年之前
TODO 3dd3a2b965 target-lm32: add breakpoint/watchpoint support 11 年之前
cpu-qom.h 34f4aa83f9 target-lm32: move model features to LM32CPU 11 年之前
cpu.c 00c8cb0a36 cputlb: Change tlb_flush() argument to CPUState 11 年之前
cpu.h f0c3c505a8 cpu: Move breakpoints field from CPU_COMMON to CPUState 11 年之前
gdbstub.c 5b50e790f9 cpu: Introduce CPUClass::gdb_{read,write}_register() 12 年之前
helper.c 0c591eb0a9 cputlb: Change tlb_set_page() argument to CPUState 11 年之前
helper.h 667ff9612b target-lm32: stop VM on illegal or unknown instruction 11 年之前
machine.c 0ad6773f11 target-lm32: Update VMStateDescription to LM32CPU 12 年之前
op_helper.c 3f38f309b2 translate-all: Change cpu_restore_state() argument to CPUState 11 年之前
translate.c f0c3c505a8 cpu: Move breakpoints field from CPU_COMMON to CPUState 11 年之前

README

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
-serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Programmatically terminate the emulator
----------------------------------------
Originally neither the LatticeMico32 nor its peripherals support a
mechanism to shut down the machine. Emulation aware programs can write to a
to a special register within the system control block to shut down the
virtual machine. For more details see hw/lm32_sys.c. The lm32-evr is the
first BSP which instantiate this model. A (32 bit) write to 0xfff0000
causes a vm shutdown.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
cpu_lm32_set_phys_msb_ignore(env, 1);