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helper.c 6.2 KB

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  1. /*
  2. * LatticeMico32 helper routines.
  3. *
  4. * Copyright (c) 2010 Michael Walle <michael@walle.cc>
  5. *
  6. * This library is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU Lesser General Public
  8. * License as published by the Free Software Foundation; either
  9. * version 2 of the License, or (at your option) any later version.
  10. *
  11. * This library is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * Lesser General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU Lesser General Public
  17. * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "cpu.h"
  20. #include "qemu/host-utils.h"
  21. int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
  22. int mmu_idx)
  23. {
  24. int prot;
  25. address &= TARGET_PAGE_MASK;
  26. prot = PAGE_BITS;
  27. if (env->flags & LM32_FLAG_IGNORE_MSB) {
  28. tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
  29. TARGET_PAGE_SIZE);
  30. } else {
  31. tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
  32. }
  33. return 0;
  34. }
  35. hwaddr cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
  36. {
  37. return addr & TARGET_PAGE_MASK;
  38. }
  39. void do_interrupt(CPULM32State *env)
  40. {
  41. qemu_log_mask(CPU_LOG_INT,
  42. "exception at pc=%x type=%x\n", env->pc, env->exception_index);
  43. switch (env->exception_index) {
  44. case EXCP_INSN_BUS_ERROR:
  45. case EXCP_DATA_BUS_ERROR:
  46. case EXCP_DIVIDE_BY_ZERO:
  47. case EXCP_IRQ:
  48. case EXCP_SYSTEMCALL:
  49. /* non-debug exceptions */
  50. env->regs[R_EA] = env->pc;
  51. env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
  52. env->ie &= ~IE_IE;
  53. if (env->dc & DC_RE) {
  54. env->pc = env->deba + (env->exception_index * 32);
  55. } else {
  56. env->pc = env->eba + (env->exception_index * 32);
  57. }
  58. log_cpu_state_mask(CPU_LOG_INT, env, 0);
  59. break;
  60. case EXCP_BREAKPOINT:
  61. case EXCP_WATCHPOINT:
  62. /* debug exceptions */
  63. env->regs[R_BA] = env->pc;
  64. env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
  65. env->ie &= ~IE_IE;
  66. env->pc = env->deba + (env->exception_index * 32);
  67. log_cpu_state_mask(CPU_LOG_INT, env, 0);
  68. break;
  69. default:
  70. cpu_abort(env, "unhandled exception type=%d\n",
  71. env->exception_index);
  72. break;
  73. }
  74. }
  75. typedef struct {
  76. const char *name;
  77. uint32_t revision;
  78. uint8_t num_interrupts;
  79. uint8_t num_breakpoints;
  80. uint8_t num_watchpoints;
  81. uint32_t features;
  82. } LM32Def;
  83. static const LM32Def lm32_defs[] = {
  84. {
  85. .name = "lm32-basic",
  86. .revision = 3,
  87. .num_interrupts = 32,
  88. .num_breakpoints = 4,
  89. .num_watchpoints = 4,
  90. .features = (LM32_FEATURE_SHIFT
  91. | LM32_FEATURE_SIGN_EXTEND
  92. | LM32_FEATURE_CYCLE_COUNT),
  93. },
  94. {
  95. .name = "lm32-standard",
  96. .revision = 3,
  97. .num_interrupts = 32,
  98. .num_breakpoints = 4,
  99. .num_watchpoints = 4,
  100. .features = (LM32_FEATURE_MULTIPLY
  101. | LM32_FEATURE_DIVIDE
  102. | LM32_FEATURE_SHIFT
  103. | LM32_FEATURE_SIGN_EXTEND
  104. | LM32_FEATURE_I_CACHE
  105. | LM32_FEATURE_CYCLE_COUNT),
  106. },
  107. {
  108. .name = "lm32-full",
  109. .revision = 3,
  110. .num_interrupts = 32,
  111. .num_breakpoints = 4,
  112. .num_watchpoints = 4,
  113. .features = (LM32_FEATURE_MULTIPLY
  114. | LM32_FEATURE_DIVIDE
  115. | LM32_FEATURE_SHIFT
  116. | LM32_FEATURE_SIGN_EXTEND
  117. | LM32_FEATURE_I_CACHE
  118. | LM32_FEATURE_D_CACHE
  119. | LM32_FEATURE_CYCLE_COUNT),
  120. }
  121. };
  122. void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
  123. {
  124. int i;
  125. cpu_fprintf(f, "Available CPUs:\n");
  126. for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
  127. cpu_fprintf(f, " %s\n", lm32_defs[i].name);
  128. }
  129. }
  130. static const LM32Def *cpu_lm32_find_by_name(const char *name)
  131. {
  132. int i;
  133. for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
  134. if (strcasecmp(name, lm32_defs[i].name) == 0) {
  135. return &lm32_defs[i];
  136. }
  137. }
  138. return NULL;
  139. }
  140. static uint32_t cfg_by_def(const LM32Def *def)
  141. {
  142. uint32_t cfg = 0;
  143. if (def->features & LM32_FEATURE_MULTIPLY) {
  144. cfg |= CFG_M;
  145. }
  146. if (def->features & LM32_FEATURE_DIVIDE) {
  147. cfg |= CFG_D;
  148. }
  149. if (def->features & LM32_FEATURE_SHIFT) {
  150. cfg |= CFG_S;
  151. }
  152. if (def->features & LM32_FEATURE_SIGN_EXTEND) {
  153. cfg |= CFG_X;
  154. }
  155. if (def->features & LM32_FEATURE_I_CACHE) {
  156. cfg |= CFG_IC;
  157. }
  158. if (def->features & LM32_FEATURE_D_CACHE) {
  159. cfg |= CFG_DC;
  160. }
  161. if (def->features & LM32_FEATURE_CYCLE_COUNT) {
  162. cfg |= CFG_CC;
  163. }
  164. cfg |= (def->num_interrupts << CFG_INT_SHIFT);
  165. cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
  166. cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
  167. cfg |= (def->revision << CFG_REV_SHIFT);
  168. return cfg;
  169. }
  170. LM32CPU *cpu_lm32_init(const char *cpu_model)
  171. {
  172. LM32CPU *cpu;
  173. CPULM32State *env;
  174. const LM32Def *def;
  175. static int tcg_initialized;
  176. def = cpu_lm32_find_by_name(cpu_model);
  177. if (!def) {
  178. return NULL;
  179. }
  180. cpu = LM32_CPU(object_new(TYPE_LM32_CPU));
  181. env = &cpu->env;
  182. env->features = def->features;
  183. env->num_bps = def->num_breakpoints;
  184. env->num_wps = def->num_watchpoints;
  185. env->cfg = cfg_by_def(def);
  186. qemu_init_vcpu(env);
  187. if (tcg_enabled() && !tcg_initialized) {
  188. tcg_initialized = 1;
  189. lm32_translate_init();
  190. }
  191. return cpu;
  192. }
  193. /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
  194. * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
  195. * 0x80000000-0xffffffff is not cached and used to access IO devices. */
  196. void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
  197. {
  198. if (value) {
  199. env->flags |= LM32_FLAG_IGNORE_MSB;
  200. } else {
  201. env->flags &= ~LM32_FLAG_IGNORE_MSB;
  202. }
  203. }