r70270 isn't ready yet. Back this out. Sorry for the noise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/AsmPrinter.h

@@ -65,8 +65,8 @@ namespace llvm {
     // Necessary for external weak linkage support
     std::set<const GlobalValue*> ExtWeakSymbols;
 
-    /// OptLevel - Generating code at a specific optimization level.
-    unsigned OptLevel;
+    /// Fast - Generating code via fast instruction selection.
+    bool Fast;
   public:
     /// Output stream on which we're printing assembly code.
     ///
@@ -110,8 +110,8 @@ namespace llvm {
     bool VerboseAsm;
 
   protected:
-    explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
-                        const TargetAsmInfo *T, unsigned OL, bool V);
+    AsmPrinter(raw_ostream &o, TargetMachine &TM,
+               const TargetAsmInfo *T, bool F, bool V);
     
   public:
     virtual ~AsmPrinter();

include/llvm/CodeGen/DwarfWriter.h

@@ -81,7 +81,7 @@ public:
   void EndFunction(MachineFunction *MF);
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, unsigned OptLevel);
+  bool ValidDebugInfo(Value *V, bool FastISel);
 
   /// RecordSourceLine - Register a source line with debug info. Returns a
   /// unique label ID used to generate a label and provide correspondence to

include/llvm/CodeGen/LinkAllCodegenComponents.h

@@ -42,11 +42,11 @@ namespace {
       llvm::linkOcamlGC();
       llvm::linkShadowStackGC();
       
-      (void) llvm::createBURRListDAGScheduler(NULL, 3);
-      (void) llvm::createTDRRListDAGScheduler(NULL, 3);
-      (void) llvm::createTDListDAGScheduler(NULL, 3);
-      (void) llvm::createFastDAGScheduler(NULL, 3);
-      (void) llvm::createDefaultScheduler(NULL, 3);
+      (void) llvm::createBURRListDAGScheduler(NULL, false);
+      (void) llvm::createTDRRListDAGScheduler(NULL, false);
+      (void) llvm::createTDListDAGScheduler(NULL, false);
+      (void) llvm::createFastDAGScheduler(NULL, false);
+      (void) llvm::createDefaultScheduler(NULL, false);
 
     }
   } ForceCodegenLinking; // Force link by creating a global definition.

include/llvm/CodeGen/SchedulerRegistry.h

@@ -32,7 +32,7 @@ class MachineBasicBlock;
 
 class RegisterScheduler : public MachinePassRegistryNode {
 public:
-  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
+  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool);
 
   static MachinePassRegistry Registry;
 
@@ -64,27 +64,27 @@ public:
 /// createBURRListDAGScheduler - This creates a bottom up register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
-                                               unsigned OptLevel);
+                                               bool Fast);
 
 /// createTDRRListDAGScheduler - This creates a top down register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
-                                               unsigned OptLevel);
+                                               bool Fast);
 
 /// createTDListDAGScheduler - This creates a top-down list scheduler with
 /// a hazard recognizer.
 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
-                                             unsigned OptLevel);
+                                             bool Fast);
 
 /// createFastDAGScheduler - This creates a "fast" scheduler.
 ///
 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
-                                           unsigned OptLevel);
+                                           bool Fast);
 
 /// createDefaultScheduler - This creates an instruction scheduler appropriate
 /// for the target.
 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
-                                           unsigned OptLevel);
+                                           bool Fast);
 
 } // end namespace llvm
 

include/llvm/CodeGen/SelectionDAG.h

@@ -202,7 +202,7 @@ public:
   /// certain types of nodes together, or eliminating superfluous nodes.  The
   /// Level argument controls whether Combine is allowed to produce nodes and
   /// types that are illegal on the target.
-  void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
+  void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
 
   /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
   /// only uses types natively supported by the target.  Returns "true" if it
@@ -218,7 +218,7 @@ public:
   ///
   /// Note that this is an involved process that may invalidate pointers into
   /// the graph.
-  void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
+  void Legalize(bool TypesNeedLegalizing, bool Fast);
 
   /// RemoveDeadNodes - This method deletes all unreachable nodes in the
   /// SelectionDAG.

include/llvm/CodeGen/SelectionDAGISel.h

@@ -51,10 +51,10 @@ public:
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   GCFunctionInfo *GFI;
-  unsigned OptLevel;
+  bool Fast;
   static char ID;
 
-  explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
+  explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
   virtual ~SelectionDAGISel();
   
   TargetLowering &getTargetLowering() { return TLI; }

include/llvm/Target/TargetMachine.h

@@ -213,7 +213,7 @@ public:
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
                                                raw_ostream &,
                                                CodeGenFileType,
-                                               unsigned /* OptLevel */) {
+                                               bool /*Fast*/) {
     return FileModel::None;
   }
 
@@ -222,8 +222,7 @@ public:
   /// used to finish up adding passes to emit the file, if necessary.
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &,
-                                         MachineCodeEmitter *,
-                                         unsigned /* OptLevel */) {
+                                         MachineCodeEmitter *, bool /*Fast*/) {
     return true;
   }
  
@@ -235,7 +234,7 @@ public:
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
                                           MachineCodeEmitter &,
-                                          unsigned /* OptLevel */) {
+                                          bool /*Fast*/) {
     return true;
   }
 
@@ -244,8 +243,7 @@ public:
   /// use this.
   virtual bool WantsWholeFile() const { return false; }
   virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
-                                        CodeGenFileType,
-                                        unsigned /* OptLevel */) {
+                                        CodeGenFileType, bool /*Fast*/) {
     return true;
   }
 };
@@ -260,16 +258,16 @@ protected: // Can only create subclasses.
   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
   /// both emitting to assembly files or machine code output.
   ///
-  bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
+  bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
 
 public:
   
   /// addPassesToEmitFile - Add passes to the specified pass manager to get the
   /// specified file emitted.  Typically this will involve several steps of code
-  /// generation.  If OptLevel is 0, the code generator should emit code as fast
-  /// as possible, though the generated code may be less efficient.  This method
-  /// should return FileModel::Error if emission of this file type is not
-  /// supported.
+  /// generation.  If Fast is set to true, the code generator should emit code
+  /// as fast as possible, though the generated code may be less efficient.
+  /// This method should return FileModel::Error if emission of this file type
+  /// is not supported.
   ///
   /// The default implementation of this method adds components from the
   /// LLVM retargetable code generator, invoking the methods below to get
@@ -278,15 +276,14 @@ public:
   virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
                                                raw_ostream &Out,
                                                CodeGenFileType FileType,
-                                               unsigned OptLevel);
+                                               bool Fast);
   
   /// addPassesToEmitFileFinish - If the passes to emit the specified file had
   /// to be split up (e.g., to add an object writer pass), this method can be
   /// used to finish up adding passes to emit the file, if necessary.
   ///
   virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
-                                         MachineCodeEmitter *MCE,
-                                         unsigned OptLevel);
+                                         MachineCodeEmitter *MCE, bool Fast);
  
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
   /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
@@ -295,22 +292,21 @@ public:
   /// not supported.
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
-                                          MachineCodeEmitter &MCE,
-                                          unsigned OptLevel);
+                                          MachineCodeEmitter &MCE, bool Fast);
   
   /// Target-Independent Code Generator Pass Configuration Options.
   
   /// addInstSelector - This method should add any "last minute" LLVM->LLVM
   /// passes, then install an instruction selector pass, which converts from
   /// LLVM code to machine instructions.
-  virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
     return true;
   }
 
   /// addPreRegAllocPasses - This method may be implemented by targets that want
   /// to run passes immediately before register allocation. This should return
   /// true if -print-machineinstrs should print after these passes.
-  virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
     return false;
   }
 
@@ -318,14 +314,14 @@ public:
   /// want to run passes after register allocation but before prolog-epilog
   /// insertion.  This should return true if -print-machineinstrs should print
   /// after these passes.
-  virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
     return false;
   }
   
   /// addPreEmitPass - This pass may be implemented by targets that want to run
   /// passes immediately before machine code is emitted.  This should return
   /// true if -print-machineinstrs should print out the code after the passes.
-  virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
+  virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
     return false;
   }
   
@@ -333,7 +329,7 @@ public:
   /// addAssemblyEmitter - This pass should be overridden by the target to add
   /// the asmprinter, if asm emission is supported.  If this is not supported,
   /// 'true' should be returned.
-  virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
+  virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
                                   bool /* VerboseAsmDefault */, raw_ostream &) {
     return true;
   }
@@ -341,7 +337,7 @@ public:
   /// addCodeEmitter - This pass should be overridden by the target to add a
   /// code emitter, if supported.  If this is not supported, 'true' should be
   /// returned. If DumpAsm is true, the generated assembly is printed to cerr.
-  virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+  virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
                               bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }
@@ -350,7 +346,7 @@ public:
   /// a code emitter (without setting flags), if supported.  If this is not
   /// supported, 'true' should be returned.  If DumpAsm is true, the generated
   /// assembly is printed to cerr.
-  virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /*Fast*/,
                                     bool /*DumpAsm*/, MachineCodeEmitter &) {
     return true;
   }

include/llvm/Target/TargetOptions.h

@@ -108,7 +108,7 @@ namespace llvm {
   /// generated.
   extern bool DisableJumpTables;
 
-  /// EnableFastISel - This flag enables fast-path instruction selection
+  /// FastISel - This flag enables fast-path instruction selection
   /// which trades away generated code quality in favor of reducing
   /// compile time.
   extern bool EnableFastISel;

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

@@ -42,8 +42,8 @@ AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
 
 char AsmPrinter::ID = 0;
 AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
-                       const TargetAsmInfo *T, unsigned OL, bool VDef)
-  : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
+                       const TargetAsmInfo *T, bool F, bool VDef)
+  : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
     TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
     IsInTextSection(false)
 {

lib/CodeGen/AsmPrinter/DwarfWriter.cpp

@@ -3351,7 +3351,7 @@ public:
   }
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
+  bool ValidDebugInfo(Value *V, bool FastISel) {
     if (!V)
       return false;
 
@@ -3393,7 +3393,7 @@ public:
     case DW_TAG_lexical_block:
       /// FIXME. This interfers with the qualitfy of generated code when 
       /// during optimization.
-      if (OptLevel != 0)
+      if (FastISel == false)
         return false;
     default:
       break;
@@ -3574,6 +3574,7 @@ public:
       return 0;
 
     SmallVector<DbgScope *, 2> &Scopes = I->second;
+    if (Scopes.empty()) return 0;
     DbgScope *Scope = Scopes.back(); Scopes.pop_back();
     unsigned ID = MMI->NextLabelID();
     MMI->RecordUsedDbgLabel(ID);
@@ -4730,8 +4731,8 @@ void DwarfWriter::EndFunction(MachineFunction *MF) {
 }
 
 /// ValidDebugInfo - Return true if V represents valid debug info value.
-bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
-  return DD && DD->ValidDebugInfo(V, OptLevel);
+bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
+  return DD && DD->ValidDebugInfo(V, FastISel);
 }
 
 /// RecordSourceLine - Records location information and associates it with a 

lib/CodeGen/LLVMTargetMachine.cpp

@@ -55,9 +55,9 @@ FileModel::Model
 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                        raw_ostream &Out,
                                        CodeGenFileType FileType,
-                                       unsigned OptLevel) {
+                                       bool Fast) {
   // Add common CodeGen passes.
-  if (addCommonCodeGenPasses(PM, OptLevel))
+  if (addCommonCodeGenPasses(PM, Fast))
     return FileModel::Error;
 
   // Fold redundant debug labels.
@@ -66,17 +66,17 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
+  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (OptLevel != 0)
+  if (!Fast)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
   default:
     break;
   case TargetMachine::AssemblyFile:
-    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
+    if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
       return FileModel::Error;
     return FileModel::AsmFile;
   case TargetMachine::ObjectFile:
@@ -94,9 +94,9 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
 /// finish up adding passes to emit the file, if necessary.
 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
                                                   MachineCodeEmitter *MCE,
-                                                  unsigned OptLevel) {
+                                                  bool Fast) {
   if (MCE)
-    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
+    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 
   PM.add(createGCInfoDeleter());
 
@@ -114,15 +114,15 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 ///
 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
                                                    MachineCodeEmitter &MCE,
-                                                   unsigned OptLevel) {
+                                                   bool Fast) {
   // Add common CodeGen passes.
-  if (addCommonCodeGenPasses(PM, OptLevel))
+  if (addCommonCodeGenPasses(PM, Fast))
     return true;
 
-  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
+  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
+  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 
   PM.add(createGCInfoDeleter());
 
@@ -135,12 +135,11 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
 /// both emitting to assembly files or machine code output.
 ///
-bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
-                                               unsigned OptLevel) {
+bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
   // Standard LLVM-Level Passes.
 
   // Run loop strength reduction before anything else.
-  if (OptLevel != 0) {
+  if (!Fast) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
@@ -154,7 +153,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  if (OptLevel != 0)
+  if (!Fast)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   PM.add(createStackProtectorPass(getTargetLowering()));
@@ -168,38 +167,38 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
 
   // Enable FastISel with -fast, but allow that to be overridden.
   if (EnableFastISelOption == cl::BOU_TRUE ||
-      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
+      (Fast && EnableFastISelOption != cl::BOU_FALSE))
     EnableFastISel = true;
 
   // Ask the target for an isel.
-  if (addInstSelector(PM, OptLevel))
+  if (addInstSelector(PM, Fast))
     return true;
 
   // Print the instruction selected machine code...
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (OptLevel != 0) {
+  if (!Fast) {
     PM.add(createMachineLICMPass());
     PM.add(createMachineSinkingPass());
   }
 
   // Run pre-ra passes.
-  if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
+  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Perform register allocation.
   PM.add(createRegisterAllocator());
 
   // Perform stack slot coloring.
-  if (OptLevel != 0)
+  if (!Fast)
     PM.add(createStackSlotColoringPass());
 
   if (PrintMachineCode)  // Print the register-allocated code
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Run post-ra passes.
-  if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
+  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   if (PrintMachineCode)
@@ -217,7 +216,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Second pass scheduler.
-  if (OptLevel != 0 && !DisablePostRAScheduler) {
+  if (!Fast && !DisablePostRAScheduler) {
     PM.add(createPostRAScheduler());
 
     if (PrintMachineCode)
@@ -225,7 +224,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
   }
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
-  if (OptLevel != 0)
+  if (!Fast)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 
   if (PrintMachineCode)

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -57,9 +57,9 @@ namespace {
     SelectionDAG &DAG;
     const TargetLowering &TLI;
     CombineLevel Level;
-    unsigned OptLevel;
     bool LegalOperations;
     bool LegalTypes;
+    bool Fast;
 
     // Worklist of all of the nodes that need to be simplified.
     std::vector<SDNode*> WorkList;
@@ -254,13 +254,13 @@ namespace {
     }
 
 public:
-    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
+    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
       : DAG(D),
         TLI(D.getTargetLoweringInfo()),
         Level(Unrestricted),
-        OptLevel(OL),
         LegalOperations(false),
         LegalTypes(false),
+        Fast(fast),
         AA(A) {}
 
     /// Run - runs the dag combiner on all nodes in the work list
@@ -4784,7 +4784,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
   SDValue Ptr   = LD->getBasePtr();
 
   // Try to infer better alignment information than the load already has.
-  if (OptLevel != 0 && LD->isUnindexed()) {
+  if (!Fast && LD->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > LD->getAlignment())
         return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
@@ -4904,7 +4904,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
   SDValue Ptr   = ST->getBasePtr();
 
   // Try to infer better alignment information than the store already has.
-  if (OptLevel != 0 && ST->isUnindexed()) {
+  if (!Fast && ST->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > ST->getAlignment())
         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
@@ -6084,9 +6084,8 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
 
 // SelectionDAG::Combine - This is the entry point for the file.
 //
-void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
-                           unsigned OptLevel) {
+void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) {
   /// run - This is the main entry point to this class.
   ///
-  DAGCombiner(*this, AA, OptLevel).Run(Level);
+  DAGCombiner(*this, AA, Fast).Run(Level);
 }

lib/CodeGen/SelectionDAG/FastISel.cpp

@@ -327,7 +327,7 @@ bool FastISel::SelectCall(User *I) {
   default: break;
   case Intrinsic::dbg_stoppoint: {
     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
       std::string Dir, FN;
       unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
@@ -344,7 +344,7 @@ bool FastISel::SelectCall(User *I) {
   }
   case Intrinsic::dbg_region_start: {
     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
-    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
       unsigned ID = 
         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
@@ -354,7 +354,7 @@ bool FastISel::SelectCall(User *I) {
   }
   case Intrinsic::dbg_region_end: {
     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
-    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
      unsigned ID = 0;
      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
      if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
@@ -380,7 +380,7 @@ bool FastISel::SelectCall(User *I) {
     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI->getSubprogram();
 
-    if (DW->ValidDebugInfo(SP, 0)) {
+    if (DW->ValidDebugInfo(SP, true)) {
       // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
       // (most?) gdb expects.
       DebugLoc PrevLoc = DL;
@@ -425,7 +425,7 @@ bool FastISel::SelectCall(User *I) {
   case Intrinsic::dbg_declare: {
     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
     Value *Variable = DI->getVariable();
-    if (DW && DW->ValidDebugInfo(Variable, 0)) {
+    if (DW && DW->ValidDebugInfo(Variable, true)) {
       // Determine the address of the declared object.
       Value *Address = DI->getAddress();
       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

@@ -55,8 +55,8 @@ namespace {
 class VISIBILITY_HIDDEN SelectionDAGLegalize {
   TargetLowering &TLI;
   SelectionDAG &DAG;
-  unsigned OptLevel;
   bool TypesNeedLegalizing;
+  bool Fast;
 
   // Libcall insertion helpers.
 
@@ -139,7 +139,7 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize {
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
-                                unsigned ol);
+                                bool fast);
 
   /// getTypeAction - Return how we should legalize values of this type, either
   /// it is already legal or we need to expand it into multiple registers of
@@ -345,9 +345,9 @@ SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT, DebugLoc dl,
 }
 
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
-                                           bool types, unsigned ol)
-  : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
-    TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
+                                           bool types, bool fast)
+  : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
+    Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
   assert(MVT::LAST_VALUETYPE <= 32 &&
          "Too many value types for ValueTypeActions to hold!");
 }
@@ -1271,7 +1271,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         unsigned Line = DSP->getLine();
         unsigned Col = DSP->getColumn();
 
-        if (OptLevel == 0) {
+        if (Fast) {
           // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
           // won't hurt anything.
           if (useDEBUG_LOC) {
@@ -8566,9 +8566,9 @@ SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
 
 // SelectionDAG::Legalize - This is the entry point for the file.
 //
-void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
+void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
   /// run - This is the main entry point to this class.
   ///
-  SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();
+  SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();
 }
 

lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

@@ -630,6 +630,6 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
   return new ScheduleDAGFast(*IS->MF);
 }

lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

@@ -261,7 +261,7 @@ void ScheduleDAGList::ListScheduleTopDown() {
 /// new hazard recognizer. This scheduler takes ownership of the hazard
 /// recognizer and deletes it when done.
 ScheduleDAGSDNodes *
-llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
   return new ScheduleDAGList(*IS->MF,
                              new LatencyPriorityQueue(),
                              IS->CreateTargetHazardRecognizer());

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

@@ -1505,7 +1505,7 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
@@ -1519,7 +1519,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
 }
 
 llvm::ScheduleDAGSDNodes *
-llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();

lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

@@ -3910,9 +3910,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
   case Intrinsic::dbg_stoppoint: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
+    if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
       MachineFunction &MF = DAG.getMachineFunction();
-      if (OptLevel == 0)
+      if (Fast)
         DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
                                         SPI.getLine(),
                                         SPI.getColumn(),
@@ -3930,8 +3930,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
   case Intrinsic::dbg_region_start: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
-
-    if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
+    if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
       unsigned LabelID =
         DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
       DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
@@ -3943,8 +3942,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
   case Intrinsic::dbg_region_end: {
     DwarfWriter *DW = DAG.getDwarfWriter();
     DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
+    if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
 
-    if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
       MachineFunction &MF = DAG.getMachineFunction();
       DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
       std::string SPName;
@@ -3953,7 +3952,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
           && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
           // This is end of inlined function. Debugging information for
           // inlined function is not handled yet (only supported by FastISel).
-        if (OptLevel == 0) {
+        if (Fast) {
           unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
           if (ID != 0)
             // Returned ID is 0 if this is unbalanced "end of inlined
@@ -3979,9 +3978,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     if (!DW) return 0;
     DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI.getSubprogram();
-    if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
-      MachineFunction &MF = DAG.getMachineFunction();
-      if (OptLevel == 0) {
+    if (SP && DW->ValidDebugInfo(SP, Fast)) {
+        MachineFunction &MF = DAG.getMachineFunction();
+      if (Fast) {
         // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
         // (most?) gdb expects.
         DebugLoc PrevLoc = CurDebugLoc;
@@ -4052,11 +4051,11 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     return 0;
   }
   case Intrinsic::dbg_declare: {
-    if (OptLevel == 0) {
+    if (Fast) {
       DwarfWriter *DW = DAG.getDwarfWriter();
       DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
       Value *Variable = DI.getVariable();
-      if (DW && DW->ValidDebugInfo(Variable, OptLevel))
+      if (DW && DW->ValidDebugInfo(Variable, Fast))
         DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
                                 getValue(DI.getAddress()), getValue(Variable)));
     } else {

lib/CodeGen/SelectionDAG/SelectionDAGBuild.h

@@ -355,17 +355,17 @@ public:
   ///
   FunctionLoweringInfo &FuncInfo;
 
-  /// OptLevel - What optimization level we're generating code for.
+  /// Fast - We are in -fast mode.
   /// 
-  unsigned OptLevel;
+  bool Fast;
   
   /// GFI - Garbage collection metadata for the function.
   GCFunctionInfo *GFI;
 
   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
-                       FunctionLoweringInfo &funcinfo, unsigned ol)
+                       FunctionLoweringInfo &funcinfo, bool fast)
     : CurDebugLoc(DebugLoc::getUnknownLoc()), 
-      TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
+      TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
   }
 
   void init(GCFunctionInfo *gfi, AliasAnalysis &aa);

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -136,16 +136,16 @@ namespace llvm {
   /// createDefaultScheduler - This creates an instruction scheduler appropriate
   /// for the target.
   ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
-                                             unsigned OptLevel) {
+                                             bool Fast) {
     const TargetLowering &TLI = IS->getTargetLowering();
 
-    if (OptLevel == 0)
-      return createFastDAGScheduler(IS, OptLevel);
+    if (Fast)
+      return createFastDAGScheduler(IS, Fast);
     if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
-      return createTDListDAGScheduler(IS, OptLevel);
+      return createTDListDAGScheduler(IS, Fast);
     assert(TLI.getSchedulingPreference() ==
          TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
-    return createBURRListDAGScheduler(IS, OptLevel);
+    return createBURRListDAGScheduler(IS, Fast);
   }
 }
 
@@ -262,13 +262,13 @@ static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
+SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
   FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
   FuncInfo(new FunctionLoweringInfo(TLI)),
   CurDAG(new SelectionDAG(TLI, *FuncInfo)),
-  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
+  SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
   GFI(),
-  OptLevel(OL),
+  Fast(fast),
   DAGSize(0)
 {}
 
@@ -576,9 +576,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
   // Run the DAG combiner in pre-legalize mode.
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Combining 1", GroupName);
-    CurDAG->Combine(Unrestricted, *AA, OptLevel);
+    CurDAG->Combine(Unrestricted, *AA, Fast);
   } else {
-    CurDAG->Combine(Unrestricted, *AA, OptLevel);
+    CurDAG->Combine(Unrestricted, *AA, Fast);
   }
   
   DOUT << "Optimized lowered selection DAG:\n";
@@ -608,9 +608,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
       // Run the DAG combiner in post-type-legalize mode.
       if (TimePassesIsEnabled) {
         NamedRegionTimer T("DAG Combining after legalize types", GroupName);
-        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
+        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
       } else {
-        CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
+        CurDAG->Combine(NoIllegalTypes, *AA, Fast);
       }
 
       DOUT << "Optimized type-legalized selection DAG:\n";
@@ -622,9 +622,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
 
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Legalization", GroupName);
-    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
+    CurDAG->Legalize(DisableLegalizeTypes, Fast);
   } else {
-    CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
+    CurDAG->Legalize(DisableLegalizeTypes, Fast);
   }
   
   DOUT << "Legalized selection DAG:\n";
@@ -635,9 +635,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
   // Run the DAG combiner in post-legalize mode.
   if (TimePassesIsEnabled) {
     NamedRegionTimer T("DAG Combining 2", GroupName);
-    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
+    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
   } else {
-    CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
+    CurDAG->Combine(NoIllegalOperations, *AA, Fast);
   }
   
   DOUT << "Optimized legalized selection DAG:\n";
@@ -645,7 +645,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
 
   if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
   
-  if (OptLevel != 0)
+  if (!Fast)
     ComputeLiveOutVRegInfo();
 
   // Third, instruction select all of the operations to machine code, adding the
@@ -1082,7 +1082,7 @@ ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
     RegisterScheduler::setDefault(Ctor);
   }
   
-  return Ctor(this, OptLevel);
+  return Ctor(this, Fast);
 }
 
 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {

lib/Target/ARM/ARM.h

@@ -91,7 +91,7 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
 FunctionPass *createARMISelDag(ARMTargetMachine &TM);
 FunctionPass *createARMCodePrinterPass(raw_ostream &O,
                                        ARMTargetMachine &TM,
-                                       unsigned OptLevel, bool Verbose);
+                                       bool Fast, bool Verbose);
 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 FunctionPass *createARMLoadStoreOptimizationPass();

lib/Target/ARM/ARMTargetMachine.cpp

@@ -138,37 +138,35 @@ const TargetAsmInfo *ARMTargetMachine::createTargetAsmInfo() const {
 
 
 // Pass Pipeline Configuration
-bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createARMISelDag(*this));
   return false;
 }
 
-bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
-  if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
+  if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
     PM.add(createARMLoadStoreOptimizationPass());
 
-  if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
+  if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
     PM.add(createIfConverterPass());
 
   PM.add(createARMConstantIslandPass());
   return true;
 }
 
-bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
-                                          bool Verbose,
-                                          raw_ostream &Out) {
+bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
+                                          bool Verbose, raw_ostream &Out) {
   // Output assembly language.
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
 
   return false;
 }
 
 
-bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   if (DefRelocModel == Reloc::Default)
@@ -179,22 +177,20 @@ bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;
 }
 
-bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
-                                            bool DumpAsm,
-                                            MachineCodeEmitter &MCE) {
+bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+                                        bool DumpAsm, MachineCodeEmitter &MCE) {
   // Machine code emitter pass for ARM.
   PM.add(createARMCodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;

lib/Target/ARM/ARMTargetMachine.h

@@ -41,7 +41,7 @@ protected:
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             ARMTargetMachine &tm,
-                                            unsigned OptLevel, bool verbose);
+                                            bool fast, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -69,13 +69,13 @@ public:
   virtual const TargetAsmInfo *createTargetAsmInfo() const;
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 };
 

lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp

@@ -80,9 +80,9 @@ namespace {
     /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
     bool InCPMode;
   public:
-    explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                           const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
+    ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                  const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
         InCPMode(false) {
       Subtarget = &TM.getSubtarget<ARMSubtarget>();
     }
@@ -1061,8 +1061,8 @@ bool ARMAsmPrinter::doFinalization(Module &M) {
 ///
 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
                                              ARMTargetMachine &tm,
-                                             unsigned OptLevel, bool verbose) {
-  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                             bool fast, bool verbose) {
+  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 namespace {

lib/Target/Alpha/Alpha.h

@@ -26,7 +26,7 @@ namespace llvm {
   FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
   FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
                                            TargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           bool Fast, bool Verbose);
   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
   FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
                                            MachineCodeEmitter &MCE);

lib/Target/Alpha/AlphaTargetMachine.cpp

@@ -76,34 +76,31 @@ AlphaTargetMachine::AlphaTargetMachine(const Module &M, const std::string &FS)
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createAlphaISelDag(*this));
   return false;
 }
-bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                        unsigned OptLevel) {
+bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   // Must run branch selection immediately preceding the asm printer
   PM.add(createAlphaBranchSelectionPass());
   return false;
 }
-bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
+bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
                                             bool Verbose,
                                             raw_ostream &Out) {
   PM.add(createAlphaLLRPPass(*this));
-  PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }
-bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
                                         bool DumpAsm, MachineCodeEmitter &MCE) {
   PM.add(createAlphaCodeEmitterPass(*this, MCE));
   if (DumpAsm)
-    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel, true));
+    PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
   return false;
 }
 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                              unsigned OptLevel, bool DumpAsm,
+                                              bool Fast, bool DumpAsm,
                                               MachineCodeEmitter &MCE) {
-  return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
+  return addCodeEmitter(PM, Fast, DumpAsm, MCE);
 }

lib/Target/Alpha/AlphaTargetMachine.h

@@ -58,13 +58,13 @@ public:
   static unsigned getModuleMatchQuality(const Module &M);
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 };
 

lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp

@@ -36,9 +36,9 @@ namespace {
     /// Unique incrementer for label values for referencing Global values.
     ///
 
-    explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
-                             const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(o, tm, T, OL, V) {}
+    AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
+                    const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(o, tm, T, F, V) {}
 
     virtual const char *getPassName() const {
       return "Alpha Assembly Printer";
@@ -68,9 +68,8 @@ namespace {
 ///
 FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               unsigned OptLevel,
-                                               bool verbose) {
-  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                               bool fast, bool verbose) {
+  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 #include "AlphaGenAsmWriter.inc"

lib/Target/CBackend/CBackend.cpp

@@ -3587,7 +3587,7 @@ void CWriter::visitExtractValueInst(ExtractValueInst &EVI) {
 bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                               raw_ostream &o,
                                               CodeGenFileType FileType,
-                                              unsigned OptLevel) {
+                                              bool Fast) {
   if (FileType != TargetMachine::AssemblyFile) return true;
 
   PM.add(createGCLoweringPass());

lib/Target/CBackend/CTargetMachine.h

@@ -27,8 +27,7 @@ struct CTargetMachine : public TargetMachine {
 
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                        CodeGenFileType FileType,
-                                        unsigned OptLevel);
+                                        CodeGenFileType FileType, bool Fast);
 
   // This class always works, but must be requested explicitly on 
   // llc command line.

lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp

@@ -48,9 +48,9 @@ namespace {
   class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
     std::set<std::string> FnStubs, GVStubs;
   public:
-    explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                           const TargetAsmInfo *T, unsigned OL, bool V) :
-      AsmPrinter(O, TM, T, OL, V) {}
+    SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                  const TargetAsmInfo *T, bool F, bool V) :
+      AsmPrinter(O, TM, T, F, V) {}
 
     virtual const char *getPassName() const {
       return "STI CBEA SPU Assembly Printer";
@@ -615,6 +615,6 @@ bool LinuxAsmPrinter::doFinalization(Module &M) {
 ///
 FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
                                             SPUTargetMachine &tm,
-                                            unsigned OptLevel, bool verbose) {
-  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                            bool fast, bool verbose) {
+  return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }

lib/Target/CellSPU/SPU.h

@@ -25,7 +25,7 @@ namespace llvm {
   FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
   FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
                                         SPUTargetMachine &tm,
-                                        unsigned OptLevel, bool verbose);
+                                        bool fast, bool verbose);
 
   /*--== Utility functions/predicates/etc used all over the place: --==*/
   //! Predicate test for a signed 10-bit value

lib/Target/CellSPU/SPUTargetMachine.cpp

@@ -81,17 +81,15 @@ SPUTargetMachine::SPUTargetMachine(const Module &M, const std::string &FS)
 //===----------------------------------------------------------------------===//
 
 bool
-SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
+SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
 {
   // Install an instruction selector.
   PM.add(createSPUISelDag(*this));
   return false;
 }
 
-bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
-                                          bool Verbose,
-                                          raw_ostream &Out) {
-  PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
+bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                          bool Verbose, raw_ostream &Out) {
+  PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
   return false;
 }

lib/Target/CellSPU/SPUTargetMachine.h

@@ -83,9 +83,9 @@ public:
   }
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
-                                  bool Verbose, raw_ostream &Out);
+  virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /*Fast*/, 
+                                  bool /*Verbose*/, raw_ostream &Out);
 };
 
 } // end namespace llvm

lib/Target/CppBackend/CPPBackend.cpp

@@ -1995,7 +1995,7 @@ char CppWriter::ID = 0;
 bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
                                                 raw_ostream &o,
                                                 CodeGenFileType FileType,
-                                                unsigned OptLevel) {
+                                                bool Fast) {
   if (FileType != TargetMachine::AssemblyFile) return true;
   PM.add(new CppWriter(o));
   return false;

lib/Target/CppBackend/CPPTargetMachine.h

@@ -29,8 +29,7 @@ struct CPPTargetMachine : public TargetMachine {
 
   virtual bool WantsWholeFile() const { return true; }
   virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                        CodeGenFileType FileType,
-                                        unsigned OptLevel);
+                                        CodeGenFileType FileType, bool Fast);
 
   // This class always works, but shouldn't be the default in most cases.
   static unsigned getModuleMatchQuality(const Module &M) { return 1; }

lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp

@@ -37,9 +37,9 @@ namespace {
   class IA64AsmPrinter : public AsmPrinter {
     std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
   public:
-    explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
-                            const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V) {}
+    IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
+                   const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V) {}
 
     virtual const char *getPassName() const {
       return "IA64 Assembly Printer";
@@ -370,7 +370,6 @@ bool IA64AsmPrinter::doFinalization(Module &M) {
 ///
 FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
                                               IA64TargetMachine &tm,
-                                              unsigned OptLevel,
-                                              bool verbose) {
-  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                              bool fast, bool verbose) {
+  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }

lib/Target/IA64/IA64.h

@@ -37,7 +37,7 @@ FunctionPass *createIA64BundlingPass(IA64TargetMachine &TM);
 ///
 FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
                                         IA64TargetMachine &tm,
-                                        unsigned OptLevel, bool verbose);
+                                        bool fast, bool verbose);
 
 } // End llvm namespace
 

lib/Target/IA64/IA64TargetMachine.cpp

@@ -72,21 +72,19 @@ IA64TargetMachine::IA64TargetMachine(const Module &M, const std::string &FS)
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
+bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createIA64DAGToDAGInstructionSelector(*this));
   return false;
 }
 
-bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   // Make sure everything is bundled happily
   PM.add(createIA64BundlingPass(*this));
   return true;
 }
-bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                           unsigned OptLevel,
-                                           bool Verbose,
-                                           raw_ostream &Out) {
-  PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
+bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                           bool Verbose, raw_ostream &Out) {
+  PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }
 

lib/Target/IA64/IA64TargetMachine.h

@@ -51,9 +51,9 @@ public:
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
 };
 } // End llvm namespace

lib/Target/MSIL/MSILWriter.cpp

@@ -35,8 +35,7 @@ namespace {
 
     virtual bool WantsWholeFile() const { return true; }
     virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
-                                          CodeGenFileType FileType,
-                                          unsigned OptLevel);
+                                         CodeGenFileType FileType, bool Fast);
 
     // This class always works, but shouldn't be the default in most cases.
     static unsigned getModuleMatchQuality(const Module &M) { return 1; }
@@ -1663,8 +1662,7 @@ void MSILWriter::printExternals() {
 //===----------------------------------------------------------------------===//
 
 bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
-                                          CodeGenFileType FileType,
-                                          unsigned OptLevel)
+                                          CodeGenFileType FileType, bool Fast)
 {
   if (FileType != TargetMachine::AssemblyFile) return true;
   MSILWriter* Writer = new MSILWriter(o);

lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp

@@ -49,9 +49,9 @@ namespace {
   class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
     const MipsSubtarget *Subtarget;
   public:
-    explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, 
-                            const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V) {
+    MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM, 
+                   const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V) {
       Subtarget = &TM.getSubtarget<MipsSubtarget>();
     }
 
@@ -91,8 +91,8 @@ namespace {
 /// regardless of whether the function is in SSA form.
 FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
                                               MipsTargetMachine &tm,
-                                              unsigned OptLevel, bool verbose) {
-  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                              bool fast, bool verbose) {
+  return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 //===----------------------------------------------------------------------===//

lib/Target/Mips/Mips.h

@@ -25,7 +25,7 @@ namespace llvm {
   FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
   FunctionPass *createMipsCodePrinterPass(raw_ostream &OS, 
                                           MipsTargetMachine &TM,
-                                          unsigned OptLevel, bool Verbose);
+                                          bool Fast, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for Mips registers.  This defines a mapping from

lib/Target/Mips/MipsTargetMachine.cpp

@@ -105,7 +105,7 @@ getModuleMatchQuality(const Module &M)
 // Install an instruction selector pass using 
 // the ISelDag to gen Mips code.
 bool MipsTargetMachine::
-addInstSelector(PassManagerBase &PM, unsigned OptLevel) 
+addInstSelector(PassManagerBase &PM, bool Fast) 
 {
   PM.add(createMipsISelDag(*this));
   return false;
@@ -115,7 +115,7 @@ addInstSelector(PassManagerBase &PM, unsigned OptLevel)
 // machine code is emitted. return true if -print-machineinstrs should 
 // print out the code after the passes.
 bool MipsTargetMachine::
-addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) 
+addPreEmitPass(PassManagerBase &PM, bool Fast) 
 {
   PM.add(createMipsDelaySlotFillerPass(*this));
   return true;
@@ -124,10 +124,10 @@ addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
 // Implements the AssemblyEmitter for the target. Must return
 // true if AssemblyEmitter is supported
 bool MipsTargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                    bool Verbose, raw_ostream &Out) 
 {
   // Output assembly language.
-  PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }

lib/Target/Mips/MipsTargetMachine.h

@@ -57,9 +57,9 @@ namespace llvm {
     static unsigned getModuleMatchQuality(const Module &M);
 
     // Pass Pipeline Configuration
-    virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-    virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-    virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+    virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+    virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+    virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                     bool Verbose, raw_ostream &Out);
   };
 

lib/Target/PIC16/PIC16.h

@@ -75,7 +75,7 @@ namespace PIC16CC {
   FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
   FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS, 
                                            PIC16TargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           bool Fast, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for PIC16 registers.  This defines a mapping from

lib/Target/PIC16/PIC16AsmPrinter.cpp

@@ -161,9 +161,8 @@ bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 ///
 FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
                                                PIC16TargetMachine &tm,
-                                               unsigned OptLevel,
-                                               bool verbose) {
-  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                               bool fast, bool verbose) {
+  return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {

lib/Target/PIC16/PIC16AsmPrinter.h

@@ -24,9 +24,9 @@
 
 namespace llvm {
   struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
-    explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
-                             const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V) {
+  PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
+                    const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V) {
       CurBank = "";
       FunctionLabelBegin = '@';
       IsRomData = false;

lib/Target/PIC16/PIC16TargetMachine.cpp

@@ -55,18 +55,17 @@ const TargetAsmInfo *PIC16TargetMachine::createTargetAsmInfo() const {
   return new PIC16TargetAsmInfo(*this);
 }
 
-bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   // Install an instruction selector.
   PM.add(createPIC16ISelDag(*this));
   return false;
 }
 
 bool PIC16TargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
+addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
                    raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }
 

lib/Target/PIC16/PIC16TargetMachine.h

@@ -57,8 +57,8 @@ public:
     return const_cast<PIC16TargetLowering*>(&TLInfo); 
   }
 
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
                                   bool Verbose, raw_ostream &Out);
 }; // PIC16TargetMachine.
 

lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp

@@ -54,9 +54,9 @@ namespace {
     StringSet<> FnStubs, GVStubs, HiddenGVStubs;
     const PPCSubtarget &Subtarget;
   public:
-    explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                           const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V),
+    PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                  const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V),
         Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
 
     virtual const char *getPassName() const {
@@ -297,9 +297,9 @@ namespace {
     DwarfWriter *DW;
     MachineModuleInfo *MMI;
   public:
-    explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                                const TargetAsmInfo *T, unsigned OL, bool V)
-      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
+    PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
+                       const TargetAsmInfo *T, bool F, bool V)
+      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
 
     virtual const char *getPassName() const {
       return "Linux PPC Assembly Printer";
@@ -326,9 +326,9 @@ namespace {
     MachineModuleInfo *MMI;
     raw_ostream &OS;
   public:
-    explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
-                                 const TargetAsmInfo *T, unsigned OL, bool V)
-      : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
+    PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
+                        const TargetAsmInfo *T, bool F, bool V)
+      : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
 
     virtual const char *getPassName() const {
       return "Darwin PPC Assembly Printer";
@@ -1176,15 +1176,13 @@ bool PPCDarwinAsmPrinter::doFinalization(Module &M) {
 ///
 FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
                                             PPCTargetMachine &tm,
-                                            unsigned OptLevel, bool verbose) {
+                                            bool fast, bool verbose) {
   const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
 
   if (Subtarget->isDarwin()) {
-    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
-                                   OptLevel, verbose);
+    return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
   } else {
-    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
-                                  OptLevel, verbose);
+    return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
   }
 }
 

lib/Target/PowerPC/PPC.h

@@ -28,7 +28,7 @@ FunctionPass *createPPCBranchSelectionPass();
 FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
 FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
                                       PPCTargetMachine &TM,
-                                      unsigned OptLevel, bool Verbose);
+                                      bool Fast, bool Verbose);
 FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 } // end namespace llvm;

lib/Target/PowerPC/PPCTargetMachine.cpp

@@ -129,31 +129,29 @@ PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS)
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   // Install an instruction selector.
   PM.add(createPPCISelDag(*this));
   return false;
 }
 
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   
   // Must run branch selection immediately preceding the asm printer.
   PM.add(createPPCBranchSelectionPass());
   return false;
 }
 
-bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
-                                          bool Verbose,
-                                          raw_ostream &Out) {
+bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                          bool Verbose, raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
 
   return false;
 }
 
-bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
   // FIXME: This should be moved to TargetJITInfo!!
@@ -178,20 +176,20 @@ bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;
 }
 
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                             bool DumpAsm, MachineCodeEmitter &MCE) {
   // Machine code emitter pass for PowerPC.
   PM.add(createPPCCodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;

lib/Target/PowerPC/PPCTargetMachine.h

@@ -46,7 +46,7 @@ protected:
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             PPCTargetMachine &tm, 
-                                            unsigned OptLevel, bool verbose);
+                                            bool fast, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -76,13 +76,13 @@ public:
   }
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
   virtual bool getEnableTailMergeDefault() const;
 };

lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp

@@ -48,9 +48,9 @@ namespace {
     typedef std::map<const Value *, unsigned> ValueMapTy;
     ValueMapTy NumberForBB;
   public:
-    explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
-                             const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V) {}
+    SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
+                    const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V) {}
 
     virtual const char *getPassName() const {
       return "Sparc Assembly Printer";
@@ -82,9 +82,8 @@ namespace {
 ///
 FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
                                                TargetMachine &tm,
-                                               unsigned OptLevel,
-                                               bool verbose) {
-  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                               bool fast, bool verbose) {
+  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 /// runOnMachineFunction - This uses the printInstruction()

lib/Target/Sparc/Sparc.h

@@ -25,7 +25,7 @@ namespace llvm {
 
   FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
   FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           bool Fast, bool Verbose);
   FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
   FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
 } // end namespace llvm;

lib/Target/Sparc/SparcTargetMachine.cpp

@@ -68,8 +68,7 @@ unsigned SparcTargetMachine::getModuleMatchQuality(const Module &M) {
 #endif
 }
 
-bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createSparcISelDag(*this));
   return false;
 }
@@ -77,17 +76,15 @@ bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
 /// addPreEmitPass - This pass may be implemented by targets that want to run
 /// passes immediately before machine code is emitted.  This should return
 /// true if -print-machineinstrs should print out the code after the passes.
-bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
+bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
   PM.add(createSparcFPMoverPass(*this));
   PM.add(createSparcDelaySlotFillerPass(*this));
   return true;
 }
 
-bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
-                                            bool Verbose,
-                                            raw_ostream &Out) {
+bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                            bool Verbose, raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createSparcCodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createSparcCodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }

lib/Target/Sparc/SparcTargetMachine.h

@@ -51,9 +51,9 @@ public:
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
 };
 

lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h

@@ -33,9 +33,9 @@ class VISIBILITY_HIDDEN X86ATTAsmPrinter : public AsmPrinter {
   MachineModuleInfo *MMI;
   const X86Subtarget *Subtarget;
  public:
-  explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                            const TargetAsmInfo *T, unsigned OL, bool V)
-    : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
+  X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
+                   const TargetAsmInfo *T, bool F, bool V)
+    : AsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
   }
 

lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp

@@ -25,15 +25,13 @@ using namespace llvm;
 ///
 FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
                                              X86TargetMachine &tm,
-                                             unsigned OptLevel, bool verbose) {
+                                             bool fast, bool verbose) {
   const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
 
   if (Subtarget->isFlavorIntel()) {
-    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),
-                                  OptLevel, verbose);
+    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
   } else {
-    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(),
-                                OptLevel, verbose);
+    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
   }
 }
 

lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h

@@ -25,9 +25,9 @@
 namespace llvm {
 
 struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
-  explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
-                              const TargetAsmInfo *T, unsigned OL, bool V)
-    : AsmPrinter(O, TM, T, OL, V) {}
+  X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
+                     const TargetAsmInfo *T, bool F, bool V)
+    : AsmPrinter(O, TM, T, F, V) {}
 
   virtual const char *getPassName() const {
     return "X86 Intel-Style Assembly Printer";

lib/Target/X86/X86.h

@@ -25,7 +25,7 @@ class raw_ostream;
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
 
 /// createX86FloatingPointStackifierPass - This function returns a pass which
 /// converts floating point register references and pseudo instructions into
@@ -44,7 +44,7 @@ FunctionPass *createX87FPRegKillInserterPass();
 ///
 FunctionPass *createX86CodePrinterPass(raw_ostream &o,
                                        X86TargetMachine &tm,
-                                       unsigned OptLevel, bool Verbose);
+                                       bool fast, bool Verbose);
 
 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
 /// to the specified MCE object.

lib/Target/X86/X86ISelDAGToDAG.cpp

@@ -134,8 +134,8 @@ namespace {
     bool OptForSize;
 
   public:
-    explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
-      : SelectionDAGISel(tm, OptLevel),
+    X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
+      : SelectionDAGISel(tm, fast),
         TM(tm), X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()),
         OptForSize(false) {}
@@ -306,7 +306,7 @@ static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
 
 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
                                                  SDNode *Root) const {
-  if (OptLevel == 0) return false;
+  if (Fast) return false;
 
   if (U == Root)
     switch (U->getOpcode()) {
@@ -512,7 +512,7 @@ static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
 
 
 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
-/// This is only run if not in -O0 mode.
+/// This is only run if not in -fast mode (aka -O0).
 /// This allows the instruction selector to pick more read-modify-write
 /// instructions. This is a common case:
 ///
@@ -714,10 +714,10 @@ void X86DAGToDAGISel::InstructionSelect() {
   OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
 
   DEBUG(BB->dump());
-  if (OptLevel != 0)
+  if (!Fast)
     PreprocessForRMW();
 
-  // FIXME: This should only happen when not compiled with -O0.
+  // FIXME: This should only happen when not -fast.
   PreprocessForFPConvert();
 
   // Codegen the basic block.
@@ -1744,6 +1744,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
-  return new X86DAGToDAGISel(TM, OptLevel);
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
+  return new X86DAGToDAGISel(TM, Fast);
 }

lib/Target/X86/X86TargetMachine.cpp

@@ -180,9 +180,9 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   // Install an instruction selector.
-  PM.add(createX86ISelDag(*this, OptLevel));
+  PM.add(createX86ISelDag(*this, Fast));
 
   // If we're using Fast-ISel, clean up the mess.
   if (EnableFastISel)
@@ -194,29 +194,27 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
   return false;
 }
 
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool Fast) {
   // Calculate and set max stack object alignment early, so we can decide
   // whether we will need stack realignment (and thus FP).
   PM.add(createX86MaxStackAlignmentCalculatorPass());
   return false;  // -print-machineinstr shouldn't print after this.
 }
 
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool Fast) {
   PM.add(createX86FloatingPointStackifierPass());
   return true;  // -print-machineinstr should print after this.
 }
 
-bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                          unsigned OptLevel,
-                                          bool Verbose,
-                                          raw_ostream &Out) {
+bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                          bool Verbose, raw_ostream &Out) {
   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
   if (AsmPrinterCtor)
-    PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
+    PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
   return false;
 }
 
-bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
                                       bool DumpAsm, MachineCodeEmitter &MCE) {
   // FIXME: Move this to TargetJITInfo!
   // On Darwin, do not override 64-bit setting made in X86TargetMachine().
@@ -238,20 +236,19 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;
 }
 
-bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel, bool DumpAsm,
-                                            MachineCodeEmitter &MCE) {
+bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
+                                        bool DumpAsm, MachineCodeEmitter &MCE) {
   PM.add(createX86CodeEmitterPass(*this, MCE));
   if (DumpAsm) {
     assert(AsmPrinterCtor && "AsmPrinter was not linked in");
     if (AsmPrinterCtor)
-      PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
+      PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
   }
 
   return false;

lib/Target/X86/X86TargetMachine.h

@@ -45,7 +45,7 @@ protected:
   // set this functions to ctor pointer at startup time if they are linked in.
   typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
                                             X86TargetMachine &tm,
-                                            unsigned OptLevel, bool verbose);
+                                            bool fast, bool verbose);
   static AsmPrinterCtorFn AsmPrinterCtor;
 
 public:
@@ -74,14 +74,14 @@ public:
   }
 
   // Set up the pass pipeline.
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast);
+  virtual bool addPostRegAlloc(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
-  virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
                               bool DumpAsm, MachineCodeEmitter &MCE);
-  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+  virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
                                     bool DumpAsm, MachineCodeEmitter &MCE);
 
   /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are

lib/Target/XCore/XCore.h

@@ -24,7 +24,7 @@ namespace llvm {
   FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
   FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
                                            XCoreTargetMachine &TM,
-                                           unsigned OptLevel, bool Verbose);
+                                           bool Fast, bool Verbose);
 } // end namespace llvm;
 
 // Defines symbolic names for XCore registers.  This defines a mapping from

lib/Target/XCore/XCoreAsmPrinter.cpp

@@ -58,8 +58,8 @@ namespace {
     const XCoreSubtarget &Subtarget;
   public:
     XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
-                    const TargetAsmInfo *T, unsigned OL, bool V)
-      : AsmPrinter(O, TM, T, OL, V), DW(0),
+                    const TargetAsmInfo *T, bool F, bool V)
+      : AsmPrinter(O, TM, T, F, V), DW(0),
         Subtarget(*TM.getSubtargetImpl()) {}
 
     virtual const char *getPassName() const {
@@ -105,9 +105,8 @@ namespace {
 ///
 FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
                                                XCoreTargetMachine &tm,
-                                               unsigned OptLevel,
-                                               bool verbose) {
-  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
+                                               bool fast, bool verbose) {
+  return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
 }
 
 // PrintEscapedString - Print each character of the specified string, escaping

lib/Target/XCore/XCoreTargetMachine.cpp

@@ -55,17 +55,14 @@ unsigned XCoreTargetMachine::getModuleMatchQuality(const Module &M) {
   return 0;
 }
 
-bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         unsigned OptLevel) {
+bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
   PM.add(createXCoreISelDag(*this));
   return false;
 }
 
-bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
-                                            unsigned OptLevel,
-                                            bool Verbose,
-                                            raw_ostream &Out) {
+bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
+                                            bool Verbose, raw_ostream &Out) {
   // Output assembly language.
-  PM.add(createXCoreCodePrinterPass(Out, *this, OptLevel, Verbose));
+  PM.add(createXCoreCodePrinterPass(Out, *this, Fast, Verbose));
   return false;
 }

lib/Target/XCore/XCoreTargetMachine.h

@@ -52,8 +52,8 @@ public:
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
-  virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, 
+  virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
+  virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, 
                                   bool Verbose, raw_ostream &Out);
 };
 

test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0
+; RUN: llvm-as < %s | llc -fast
 
 define float @test(i32 %tmp12771278) {
         switch i32 %tmp12771278, label %bb1279 [

test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0
+; RUN: llvm-as < %s | llc -fast
 	
 %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
 @cl_pf_opts = external global %struct.cl_perfunc_opts		; <%struct.cl_perfunc_opts*> [#uses=2]

test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0
+; RUN: llvm-as < %s | llc -fast
 ; PR 1323
 
 ; ModuleID = 'test.bc'

test/CodeGen/PowerPC/cr_spilling.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
+; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -fast -relocation-model=pic -o -
 ; PR1638
 
 @.str242 = external constant [3 x i8]		; <[3 x i8]*> [#uses=1]

test/CodeGen/X86/2008-04-15-LiveVariableBug.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
+; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -fast -regalloc=local
 
 	%struct.CGPoint = type { double, double }
 	%struct.NSArray = type { %struct.NSObject }

test/CodeGen/X86/2008-05-21-CoalescerBug.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep mov | count 5
+; RUN: llvm-as < %s | llc -march=x86 -fast -fast-isel=false | grep mov | count 5
 ; PR2343
 
 	%llvm.dbg.anchor.type = type { i32, i32 }

test/CodeGen/X86/2009-03-23-LinearScanBug.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast
 
 define fastcc void @optimize_bit_field() nounwind {
 bb4:

test/CodeGen/X86/2009-04-14-IllegalRegs.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast -regalloc=local | not grep sil
 ; rdar://6787136
 
 	%struct.X = type { i8, [32 x i8] }

test/CodeGen/X86/add-with-overflow.ll

@@ -1,7 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
 ; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2
+; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2
+; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2
 
 @ok = internal constant [4 x i8] c"%d\0A\00"
 @no = internal constant [4 x i8] c"no\0A\00"

test/CodeGen/X86/fast-isel-bail.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -O0
+; RUN: llvm-as < %s | llc -march=x86 -fast
 
 ; This file is for regression tests for cases where FastISel needs
 ; to gracefully bail out and let SelectionDAGISel take over.

test/CodeGen/X86/fast-isel-gep-sext.ll

@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq
-; RUN: llvm-as < %s | llc -march=x86 -O0
+; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq
+; RUN: llvm-as < %s | llc -march=x86 -fast
 ; PR3181
 
 ; GEP indices are interpreted as signed integers, so they

test/CodeGen/X86/fast-isel-shift-imm.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl	\$80, %eax}
+; RUN: llvm-as < %s | llc -march=x86 -fast | grep {sarl	\$80, %eax}
 ; PR3242
 
 define i32 @foo(i32 %x) nounwind {

test/CodeGen/X86/pr1489.ll

@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 1082126238 | count 3
-; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 3058016715 | count 1
+; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 1082126238 | count 3
+; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 3058016715 | count 1
 ;; magic constants are 3.999f and half of 3.999
 ; ModuleID = '1489.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"

test/CodeGen/X86/volatile.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd | count 5
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd | count 5
+; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -fast | grep movsd | count 5
 
 @x = external global double
 

test/DebugInfo/2008-11-05-InlinedFuncStart.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc
-; RUN: llvm-as < %s | llc -O0
+; RUN: llvm-as < %s | llc -fast
 	%llvm.dbg.anchor.type = type { i32, i32 }
 	%llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 }
 	%llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }

test/DebugInfo/2009-01-30-Method.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0 | grep "\\"foo" | count 3
+; RUN: llvm-as < %s | llc -fast | grep "\\"foo" | count 3
 ; 1 declaration, 1 definition and 1 pubnames entry.
 target triple = "i386-apple-darwin*"
 	%llvm.dbg.anchor.type = type { i32, i32 }

test/DebugInfo/deaddebuglabel.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0 | grep "label" | count 8
+; RUN: llvm-as < %s | llc -fast | grep "label" | count 8
 ; PR2614
 ; XFAIL: *
 

test/DebugInfo/forwardDecl.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0 | %prcontext ST 1 | grep 0x1 | count 1
+; RUN: llvm-as < %s | llc -fast | %prcontext ST 1 | grep 0x1 | count 1
 
 target triple = "i386-apple-darwin9.6"
 	%llvm.dbg.anchor.type = type { i32, i32 }

test/FrontendC++/2006-11-06-StackTrace.cpp

@@ -1,7 +1,7 @@
 // This is a regression test on debug info to make sure that we can get a
 // meaningful stack trace from a C++ program.
 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
-// RUN:    llc --disable-fp-elim -o %t.s -f -O0 -relocation-model=pic
+// RUN:    llc --disable-fp-elim -o %t.s -f -fast -relocation-model=pic
 // RUN: %compile_c %t.s -o %t.o
 // RUN: %link %t.o -o %t.exe
 // RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in 

test/FrontendC++/2006-11-30-Pubnames.cpp

@@ -1,7 +1,7 @@
 // This is a regression test on debug info to make sure that we can access 
 // qualified global names.
 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
-// RUN:   llc --disable-fp-elim -o %t.s -f -O0
+// RUN:   llc --disable-fp-elim -o %t.s -f -fast
 // RUN: %compile_c %t.s -o %t.o
 // RUN: %link %t.o -o %t.exe
 // RUN: %llvmdsymutil %t.exe 

test/FrontendC++/2009-04-21-DtorNames-dbg.cpp

@@ -1,4 +1,4 @@
-// RUN: %llvmgcc -c -g %s -o - | llc -O0 -f -o %t.s
+// RUN: %llvmgcc -c -g %s -o - | llc -fast -f -o %t.s
 // RUN: %compile_c %t.s -o %t.o
 // PR4025
 

tools/llc/llc.cpp

@@ -55,13 +55,8 @@ OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename"));
 
 static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
 
-// Determine optimization level. Level -O0 is equivalent to "fast" code gen.
-static cl::opt<unsigned>
-OptLevel("O",
-         cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"),
-         cl::Prefix,
-         cl::ZeroOrMore,
-         cl::init(3));
+static cl::opt<bool> Fast("fast",
+      cl::desc("Generate code quickly, potentially sacrificing code quality"));
 
 static cl::opt<std::string>
 TargetTriple("mtriple", cl::desc("Override target triple for module"));
@@ -262,7 +257,7 @@ int main(int argc, char **argv) {
       PM.add(createVerifierPass());
 
     // Ask the target to add backend passes as necessary.
-    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) {
+    if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;
@@ -288,7 +283,7 @@ int main(int argc, char **argv) {
     // Override default to generate verbose assembly.
     Target.setAsmVerbosityDefault(true);
 
-    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) {
+    switch (Target.addPassesToEmitFile(Passes, *Out, FileType, Fast)) {
     default:
       assert(0 && "Invalid file model!");
       return 1;
@@ -309,7 +304,7 @@ int main(int argc, char **argv) {
       break;
     }
 
-    if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
+    if (Target.addPassesToEmitFileFinish(Passes, MCE, Fast)) {
       std::cerr << argv[0] << ": target does not support generation of this"
                 << " file type!\n";
       if (Out != &outs()) delete Out;

utils/TableGen/AsmWriterEmitter.cpp

@@ -650,7 +650,7 @@ void AsmWriterEmitter::run(std::ostream &O) {
   O << "\";\n\n";
 
   O << "  if (TAI->doesSupportDebugInformation() &&\n"
-    << "      DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
+    << "      DW->ShouldEmitDwarfDebug() && !Fast) {\n"
     << "    DebugLoc CurDL = MI->getDebugLoc();\n\n"
     << "    if (!CurDL.isUnknown()) {\n"
     << "      static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"

utils/TableGen/DAGISelEmitter.cpp

@@ -465,7 +465,7 @@ public:
       NumInputRootOps = N->getNumChildren();
 
       if (DisablePatternForFastISel(N, CGP))
-        emitCheck("OptLevel != 0");
+        emitCheck("!Fast");
 
       emitCheck(PredicateCheck);
     }