0002-RISC-V-Force-no-pie-code-generation-and-static-link.patch 1.6 KB

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  1. From 8491908238c4b3397571e9cff55765d59da03a45 Mon Sep 17 00:00:00 2001
  2. From: Julien Olivain <ju.o@free.fr>
  3. Date: Wed, 2 Aug 2023 23:57:17 +0200
  4. Subject: [PATCH] RISC-V: Force no-pie code generation and static link
  5. Some toolchains are now enabling PIE for security reasons by default.
  6. When XVisor is built with such a RISC-V toolchain, it is crashing
  7. just after OpenSBI, in early Xvisor startup (before any message is
  8. printed on the console).
  9. Hangs looks like those described in:
  10. https://github.com/xvisor/xvisor/issues/144
  11. https://github.com/xvisor/xvisor/issues/159
  12. Forcing -fno-pie code generation and -static link will explicitly disable
  13. PIE with those toolchains, hence fixing those issues.
  14. This issue was observed while using a riscv64 gcc toolchain from:
  15. https://toolchains.bootlin.com/downloads/releases/toolchains/riscv64-lp64d/tarballs/riscv64-lp64d--glibc--bleeding-edge-2022.08-1.tar.bz2
  16. Signed-off-by: Julien Olivain <ju.o@free.fr>
  17. Upstream: https://github.com/xvisor/xvisor/pull/170
  18. ---
  19. arch/riscv/cpu/generic/objects.mk | 5 +++++
  20. 1 file changed, 5 insertions(+)
  21. diff --git a/arch/riscv/cpu/generic/objects.mk b/arch/riscv/cpu/generic/objects.mk
  22. index 230da2a1..576603f6 100644
  23. --- a/arch/riscv/cpu/generic/objects.mk
  24. +++ b/arch/riscv/cpu/generic/objects.mk
  25. @@ -67,6 +67,11 @@ cpu-cflags += -fno-strict-aliasing -O2
  26. cpu-asflags += $(arch-cflags-y) -march=$(march-nonld-isa-y)
  27. cpu-ldflags += $(arch-ldflags-y) -march=$(march-ld-isa-y)
  28. +cpu-cflags += -fno-pie
  29. +cpu-asflags += -fno-pie
  30. +cpu-ldflags += -static
  31. +cpu-mergeflags += -static
  32. +
  33. cpu-objs-y+= cpu_entry.o
  34. cpu-objs-y+= cpu_proc.o
  35. cpu-objs-y+= cpu_tlb.o
  36. --
  37. 2.41.0