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pmu.c 24 KB

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  1. /*
  2. * QEMU PowerMac PMU device support
  3. *
  4. * Copyright (c) 2016 Benjamin Herrenschmidt, IBM Corp.
  5. * Copyright (c) 2018 Mark Cave-Ayland
  6. *
  7. * Based on the CUDA device by:
  8. *
  9. * Copyright (c) 2004-2007 Fabrice Bellard
  10. * Copyright (c) 2007 Jocelyn Mayer
  11. *
  12. * Permission is hereby granted, free of charge, to any person obtaining a copy
  13. * of this software and associated documentation files (the "Software"), to deal
  14. * in the Software without restriction, including without limitation the rights
  15. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16. * copies of the Software, and to permit persons to whom the Software is
  17. * furnished to do so, subject to the following conditions:
  18. *
  19. * The above copyright notice and this permission notice shall be included in
  20. * all copies or substantial portions of the Software.
  21. *
  22. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28. * THE SOFTWARE.
  29. */
  30. #include "qemu/osdep.h"
  31. #include "hw/qdev-properties.h"
  32. #include "migration/vmstate.h"
  33. #include "hw/irq.h"
  34. #include "hw/misc/macio/pmu.h"
  35. #include "qemu/timer.h"
  36. #include "sysemu/runstate.h"
  37. #include "sysemu/rtc.h"
  38. #include "qapi/error.h"
  39. #include "qemu/cutils.h"
  40. #include "qemu/log.h"
  41. #include "qemu/module.h"
  42. #include "trace.h"
  43. /* Bits in B data register: all active low */
  44. #define TACK 0x08 /* Transfer request (input) */
  45. #define TREQ 0x10 /* Transfer acknowledge (output) */
  46. /* PMU returns time_t's offset from Jan 1, 1904, not 1970 */
  47. #define RTC_OFFSET 2082844800
  48. #define VIA_TIMER_FREQ (4700000 / 6)
  49. static void via_set_sr_int(void *opaque)
  50. {
  51. PMUState *s = opaque;
  52. MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu);
  53. MOS6522State *ms = MOS6522(mps);
  54. qemu_irq irq = qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT);
  55. qemu_set_irq(irq, 1);
  56. }
  57. static void pmu_update_extirq(PMUState *s)
  58. {
  59. if ((s->intbits & s->intmask) != 0) {
  60. macio_set_gpio(s->gpio, 1, false);
  61. } else {
  62. macio_set_gpio(s->gpio, 1, true);
  63. }
  64. }
  65. static void pmu_adb_poll(void *opaque)
  66. {
  67. PMUState *s = opaque;
  68. ADBBusState *adb_bus = &s->adb_bus;
  69. int olen;
  70. if (!(s->intbits & PMU_INT_ADB)) {
  71. olen = adb_poll(adb_bus, s->adb_reply, adb_bus->autopoll_mask);
  72. trace_pmu_adb_poll(olen);
  73. if (olen > 0) {
  74. s->adb_reply_size = olen;
  75. s->intbits |= PMU_INT_ADB | PMU_INT_ADB_AUTO;
  76. pmu_update_extirq(s);
  77. }
  78. }
  79. }
  80. static void pmu_one_sec_timer(void *opaque)
  81. {
  82. PMUState *s = opaque;
  83. trace_pmu_one_sec_timer();
  84. s->intbits |= PMU_INT_TICK;
  85. pmu_update_extirq(s);
  86. s->one_sec_target += 1000;
  87. timer_mod(s->one_sec_timer, s->one_sec_target);
  88. }
  89. static void pmu_cmd_int_ack(PMUState *s,
  90. const uint8_t *in_data, uint8_t in_len,
  91. uint8_t *out_data, uint8_t *out_len)
  92. {
  93. if (in_len != 0) {
  94. qemu_log_mask(LOG_GUEST_ERROR,
  95. "PMU: INT_ACK command, invalid len: %d want: 0\n",
  96. in_len);
  97. return;
  98. }
  99. /* Make appropriate reply packet */
  100. if (s->intbits & PMU_INT_ADB) {
  101. if (!s->adb_reply_size) {
  102. qemu_log_mask(LOG_GUEST_ERROR,
  103. "Odd, PMU_INT_ADB set with no reply in buffer\n");
  104. }
  105. memcpy(out_data + 1, s->adb_reply, s->adb_reply_size);
  106. out_data[0] = s->intbits & (PMU_INT_ADB | PMU_INT_ADB_AUTO);
  107. *out_len = s->adb_reply_size + 1;
  108. s->intbits &= ~(PMU_INT_ADB | PMU_INT_ADB_AUTO);
  109. s->adb_reply_size = 0;
  110. } else {
  111. out_data[0] = s->intbits;
  112. s->intbits = 0;
  113. *out_len = 1;
  114. }
  115. pmu_update_extirq(s);
  116. }
  117. static void pmu_cmd_set_int_mask(PMUState *s,
  118. const uint8_t *in_data, uint8_t in_len,
  119. uint8_t *out_data, uint8_t *out_len)
  120. {
  121. if (in_len != 1) {
  122. qemu_log_mask(LOG_GUEST_ERROR,
  123. "PMU: SET_INT_MASK command, invalid len: %d want: 1\n",
  124. in_len);
  125. return;
  126. }
  127. trace_pmu_cmd_set_int_mask(s->intmask);
  128. s->intmask = in_data[0];
  129. pmu_update_extirq(s);
  130. }
  131. static void pmu_cmd_set_adb_autopoll(PMUState *s, uint16_t mask)
  132. {
  133. ADBBusState *adb_bus = &s->adb_bus;
  134. trace_pmu_cmd_set_adb_autopoll(mask);
  135. if (mask) {
  136. adb_set_autopoll_mask(adb_bus, mask);
  137. adb_set_autopoll_enabled(adb_bus, true);
  138. } else {
  139. adb_set_autopoll_enabled(adb_bus, false);
  140. }
  141. }
  142. static void pmu_cmd_adb(PMUState *s,
  143. const uint8_t *in_data, uint8_t in_len,
  144. uint8_t *out_data, uint8_t *out_len)
  145. {
  146. int len, adblen;
  147. uint8_t adb_cmd[255];
  148. if (in_len < 2) {
  149. qemu_log_mask(LOG_GUEST_ERROR,
  150. "PMU: ADB PACKET, invalid len: %d want at least 2\n",
  151. in_len);
  152. return;
  153. }
  154. *out_len = 0;
  155. if (!s->has_adb) {
  156. trace_pmu_cmd_adb_nobus();
  157. return;
  158. }
  159. /* Set autopoll is a special form of the command */
  160. if (in_data[0] == 0 && in_data[1] == 0x86) {
  161. uint16_t mask = in_data[2];
  162. mask = (mask << 8) | in_data[3];
  163. if (in_len != 4) {
  164. qemu_log_mask(LOG_GUEST_ERROR,
  165. "PMU: ADB Autopoll requires 4 bytes, got %d\n",
  166. in_len);
  167. return;
  168. }
  169. pmu_cmd_set_adb_autopoll(s, mask);
  170. return;
  171. }
  172. trace_pmu_cmd_adb_request(in_len, in_data[0], in_data[1], in_data[2],
  173. in_data[3], in_data[4]);
  174. *out_len = 0;
  175. /* Check ADB len */
  176. adblen = in_data[2];
  177. if (adblen > (in_len - 3)) {
  178. qemu_log_mask(LOG_GUEST_ERROR,
  179. "PMU: ADB len is %d > %d (in_len -3)...erroring\n",
  180. adblen, in_len - 3);
  181. len = -1;
  182. } else if (adblen > 252) {
  183. qemu_log_mask(LOG_GUEST_ERROR, "PMU: ADB command too big!\n");
  184. len = -1;
  185. } else {
  186. /* Format command */
  187. adb_cmd[0] = in_data[0];
  188. memcpy(&adb_cmd[1], &in_data[3], in_len - 3);
  189. len = adb_request(&s->adb_bus, s->adb_reply + 2, adb_cmd, in_len - 2);
  190. trace_pmu_cmd_adb_reply(len);
  191. }
  192. if (len > 0) {
  193. /* XXX Check this */
  194. s->adb_reply_size = len + 2;
  195. s->adb_reply[0] = 0x01;
  196. s->adb_reply[1] = len;
  197. } else {
  198. /* XXX Check this */
  199. s->adb_reply_size = 1;
  200. s->adb_reply[0] = 0x00;
  201. }
  202. s->intbits |= PMU_INT_ADB;
  203. pmu_update_extirq(s);
  204. }
  205. static void pmu_cmd_adb_poll_off(PMUState *s,
  206. const uint8_t *in_data, uint8_t in_len,
  207. uint8_t *out_data, uint8_t *out_len)
  208. {
  209. ADBBusState *adb_bus = &s->adb_bus;
  210. if (in_len != 0) {
  211. qemu_log_mask(LOG_GUEST_ERROR,
  212. "PMU: ADB POLL OFF command, invalid len: %d want: 0\n",
  213. in_len);
  214. return;
  215. }
  216. if (s->has_adb) {
  217. adb_set_autopoll_enabled(adb_bus, false);
  218. }
  219. }
  220. static void pmu_cmd_shutdown(PMUState *s,
  221. const uint8_t *in_data, uint8_t in_len,
  222. uint8_t *out_data, uint8_t *out_len)
  223. {
  224. if (in_len != 4) {
  225. qemu_log_mask(LOG_GUEST_ERROR,
  226. "PMU: SHUTDOWN command, invalid len: %d want: 4\n",
  227. in_len);
  228. return;
  229. }
  230. *out_len = 1;
  231. out_data[0] = 0;
  232. if (in_data[0] != 'M' || in_data[1] != 'A' || in_data[2] != 'T' ||
  233. in_data[3] != 'T') {
  234. qemu_log_mask(LOG_GUEST_ERROR,
  235. "PMU: SHUTDOWN command, Bad MATT signature\n");
  236. return;
  237. }
  238. qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  239. }
  240. static void pmu_cmd_reset(PMUState *s,
  241. const uint8_t *in_data, uint8_t in_len,
  242. uint8_t *out_data, uint8_t *out_len)
  243. {
  244. if (in_len != 0) {
  245. qemu_log_mask(LOG_GUEST_ERROR,
  246. "PMU: RESET command, invalid len: %d want: 0\n",
  247. in_len);
  248. return;
  249. }
  250. qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
  251. }
  252. static void pmu_cmd_get_rtc(PMUState *s,
  253. const uint8_t *in_data, uint8_t in_len,
  254. uint8_t *out_data, uint8_t *out_len)
  255. {
  256. uint32_t ti;
  257. if (in_len != 0) {
  258. qemu_log_mask(LOG_GUEST_ERROR,
  259. "PMU: GET_RTC command, invalid len: %d want: 0\n",
  260. in_len);
  261. return;
  262. }
  263. ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
  264. / NANOSECONDS_PER_SECOND);
  265. out_data[0] = ti >> 24;
  266. out_data[1] = ti >> 16;
  267. out_data[2] = ti >> 8;
  268. out_data[3] = ti;
  269. *out_len = 4;
  270. }
  271. static void pmu_cmd_set_rtc(PMUState *s,
  272. const uint8_t *in_data, uint8_t in_len,
  273. uint8_t *out_data, uint8_t *out_len)
  274. {
  275. uint32_t ti;
  276. if (in_len != 4) {
  277. qemu_log_mask(LOG_GUEST_ERROR,
  278. "PMU: SET_RTC command, invalid len: %d want: 4\n",
  279. in_len);
  280. return;
  281. }
  282. ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16)
  283. + (((uint32_t)in_data[2]) << 8) + in_data[3];
  284. s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
  285. / NANOSECONDS_PER_SECOND);
  286. }
  287. static void pmu_cmd_system_ready(PMUState *s,
  288. const uint8_t *in_data, uint8_t in_len,
  289. uint8_t *out_data, uint8_t *out_len)
  290. {
  291. /* Do nothing */
  292. }
  293. static void pmu_cmd_get_version(PMUState *s,
  294. const uint8_t *in_data, uint8_t in_len,
  295. uint8_t *out_data, uint8_t *out_len)
  296. {
  297. *out_len = 1;
  298. *out_data = 1; /* ??? Check what Apple does */
  299. }
  300. static void pmu_cmd_power_events(PMUState *s,
  301. const uint8_t *in_data, uint8_t in_len,
  302. uint8_t *out_data, uint8_t *out_len)
  303. {
  304. if (in_len < 1) {
  305. qemu_log_mask(LOG_GUEST_ERROR,
  306. "PMU: POWER EVENTS command, invalid len %d, want at least 1\n",
  307. in_len);
  308. return;
  309. }
  310. switch (in_data[0]) {
  311. /* Dummies for now */
  312. case PMU_PWR_GET_POWERUP_EVENTS:
  313. *out_len = 2;
  314. out_data[0] = 0;
  315. out_data[1] = 0;
  316. break;
  317. case PMU_PWR_SET_POWERUP_EVENTS:
  318. case PMU_PWR_CLR_POWERUP_EVENTS:
  319. break;
  320. case PMU_PWR_GET_WAKEUP_EVENTS:
  321. *out_len = 2;
  322. out_data[0] = 0;
  323. out_data[1] = 0;
  324. break;
  325. case PMU_PWR_SET_WAKEUP_EVENTS:
  326. case PMU_PWR_CLR_WAKEUP_EVENTS:
  327. break;
  328. default:
  329. qemu_log_mask(LOG_GUEST_ERROR,
  330. "PMU: POWER EVENTS unknown subcommand 0x%02x\n",
  331. in_data[0]);
  332. }
  333. }
  334. static void pmu_cmd_get_cover(PMUState *s,
  335. const uint8_t *in_data, uint8_t in_len,
  336. uint8_t *out_data, uint8_t *out_len)
  337. {
  338. /* Not 100% sure here, will have to check what a real Mac
  339. * returns other than byte 0 bit 0 is LID closed on laptops
  340. */
  341. *out_len = 1;
  342. *out_data = 0x00;
  343. }
  344. static void pmu_cmd_download_status(PMUState *s,
  345. const uint8_t *in_data, uint8_t in_len,
  346. uint8_t *out_data, uint8_t *out_len)
  347. {
  348. /* This has to do with PMU firmware updates as far as I can tell.
  349. *
  350. * We return 0x62 which is what OpenPMU expects
  351. */
  352. *out_len = 1;
  353. *out_data = 0x62;
  354. }
  355. static void pmu_cmd_read_pmu_ram(PMUState *s,
  356. const uint8_t *in_data, uint8_t in_len,
  357. uint8_t *out_data, uint8_t *out_len)
  358. {
  359. if (in_len < 3) {
  360. qemu_log_mask(LOG_GUEST_ERROR,
  361. "PMU: READ_PMU_RAM command, invalid len %d, expected 3\n",
  362. in_len);
  363. return;
  364. }
  365. qemu_log_mask(LOG_GUEST_ERROR,
  366. "PMU: Unsupported READ_PMU_RAM, args: %02x %02x %02x\n",
  367. in_data[0], in_data[1], in_data[2]);
  368. *out_len = 0;
  369. }
  370. /* description of commands */
  371. typedef struct PMUCmdHandler {
  372. uint8_t command;
  373. const char *name;
  374. void (*handler)(PMUState *s,
  375. const uint8_t *in_args, uint8_t in_len,
  376. uint8_t *out_args, uint8_t *out_len);
  377. } PMUCmdHandler;
  378. static const PMUCmdHandler PMUCmdHandlers[] = {
  379. { PMU_INT_ACK, "INT ACK", pmu_cmd_int_ack },
  380. { PMU_SET_INTR_MASK, "SET INT MASK", pmu_cmd_set_int_mask },
  381. { PMU_ADB_CMD, "ADB COMMAND", pmu_cmd_adb },
  382. { PMU_ADB_POLL_OFF, "ADB POLL OFF", pmu_cmd_adb_poll_off },
  383. { PMU_RESET, "REBOOT", pmu_cmd_reset },
  384. { PMU_SHUTDOWN, "SHUTDOWN", pmu_cmd_shutdown },
  385. { PMU_READ_RTC, "GET RTC", pmu_cmd_get_rtc },
  386. { PMU_SET_RTC, "SET RTC", pmu_cmd_set_rtc },
  387. { PMU_SYSTEM_READY, "SYSTEM READY", pmu_cmd_system_ready },
  388. { PMU_GET_VERSION, "GET VERSION", pmu_cmd_get_version },
  389. { PMU_POWER_EVENTS, "POWER EVENTS", pmu_cmd_power_events },
  390. { PMU_GET_COVER, "GET_COVER", pmu_cmd_get_cover },
  391. { PMU_DOWNLOAD_STATUS, "DOWNLOAD STATUS", pmu_cmd_download_status },
  392. { PMU_READ_PMU_RAM, "READ PMGR RAM", pmu_cmd_read_pmu_ram },
  393. };
  394. static void pmu_dispatch_cmd(PMUState *s)
  395. {
  396. unsigned int i;
  397. /* No response by default */
  398. s->cmd_rsp_sz = 0;
  399. for (i = 0; i < ARRAY_SIZE(PMUCmdHandlers); i++) {
  400. const PMUCmdHandler *desc = &PMUCmdHandlers[i];
  401. if (desc->command != s->cmd) {
  402. continue;
  403. }
  404. trace_pmu_dispatch_cmd(desc->name);
  405. desc->handler(s, s->cmd_buf, s->cmd_buf_pos,
  406. s->cmd_rsp, &s->cmd_rsp_sz);
  407. if (s->rsplen != -1 && s->rsplen != s->cmd_rsp_sz) {
  408. trace_pmu_debug_protocol_string("QEMU internal cmd resp mismatch!");
  409. } else {
  410. trace_pmu_debug_protocol_resp_size(s->cmd_rsp_sz);
  411. }
  412. return;
  413. }
  414. trace_pmu_dispatch_unknown_cmd(s->cmd);
  415. /* Manufacture fake response with 0's */
  416. if (s->rsplen == -1) {
  417. s->cmd_rsp_sz = 0;
  418. } else {
  419. s->cmd_rsp_sz = s->rsplen;
  420. memset(s->cmd_rsp, 0, s->rsplen);
  421. }
  422. }
  423. static void pmu_update(PMUState *s)
  424. {
  425. MOS6522PMUState *mps = &s->mos6522_pmu;
  426. MOS6522State *ms = MOS6522(mps);
  427. ADBBusState *adb_bus = &s->adb_bus;
  428. /* Only react to changes in reg B */
  429. if (ms->b == s->last_b) {
  430. return;
  431. }
  432. s->last_b = ms->b;
  433. /* Check the TREQ / TACK state */
  434. switch (ms->b & (TREQ | TACK)) {
  435. case TREQ:
  436. /* This is an ack release, handle it and bail out */
  437. ms->b |= TACK;
  438. s->last_b = ms->b;
  439. trace_pmu_debug_protocol_string("handshake: TREQ high, setting TACK");
  440. return;
  441. case TACK:
  442. /* This is a valid request, handle below */
  443. break;
  444. case TREQ | TACK:
  445. /* This is an idle state */
  446. return;
  447. default:
  448. /* Invalid state, log and ignore */
  449. trace_pmu_debug_protocol_error(ms->b);
  450. return;
  451. }
  452. /* If we wanted to handle commands asynchronously, this is where
  453. * we would delay the clearing of TACK until we are ready to send
  454. * the response
  455. */
  456. /* We have a request, handshake TACK so we don't stay in
  457. * an invalid state. If we were concurrent with the OS we
  458. * should only do this after we grabbed the SR but that isn't
  459. * a problem here.
  460. */
  461. trace_pmu_debug_protocol_clear_treq(s->cmd_state);
  462. ms->b &= ~TACK;
  463. s->last_b = ms->b;
  464. /* Act according to state */
  465. switch (s->cmd_state) {
  466. case pmu_state_idle:
  467. if (!(ms->acr & SR_OUT)) {
  468. trace_pmu_debug_protocol_string("protocol error! "
  469. "state idle, ACR reading");
  470. break;
  471. }
  472. s->cmd = ms->sr;
  473. via_set_sr_int(s);
  474. s->cmdlen = pmu_data_len[s->cmd][0];
  475. s->rsplen = pmu_data_len[s->cmd][1];
  476. s->cmd_buf_pos = 0;
  477. s->cmd_rsp_pos = 0;
  478. s->cmd_state = pmu_state_cmd;
  479. adb_autopoll_block(adb_bus);
  480. trace_pmu_debug_protocol_cmd(s->cmd, s->cmdlen, s->rsplen);
  481. break;
  482. case pmu_state_cmd:
  483. if (!(ms->acr & SR_OUT)) {
  484. trace_pmu_debug_protocol_string("protocol error! "
  485. "state cmd, ACR reading");
  486. break;
  487. }
  488. if (s->cmdlen == -1) {
  489. trace_pmu_debug_protocol_cmdlen(ms->sr);
  490. s->cmdlen = ms->sr;
  491. if (s->cmdlen > sizeof(s->cmd_buf)) {
  492. trace_pmu_debug_protocol_cmd_toobig(s->cmdlen);
  493. }
  494. } else if (s->cmd_buf_pos < sizeof(s->cmd_buf)) {
  495. s->cmd_buf[s->cmd_buf_pos++] = ms->sr;
  496. }
  497. via_set_sr_int(s);
  498. break;
  499. case pmu_state_rsp:
  500. if (ms->acr & SR_OUT) {
  501. trace_pmu_debug_protocol_string("protocol error! "
  502. "state resp, ACR writing");
  503. break;
  504. }
  505. if (s->rsplen == -1) {
  506. trace_pmu_debug_protocol_cmd_send_resp_size(s->cmd_rsp_sz);
  507. ms->sr = s->cmd_rsp_sz;
  508. s->rsplen = s->cmd_rsp_sz;
  509. } else if (s->cmd_rsp_pos < s->cmd_rsp_sz) {
  510. trace_pmu_debug_protocol_cmd_send_resp(s->cmd_rsp_pos, s->rsplen);
  511. ms->sr = s->cmd_rsp[s->cmd_rsp_pos++];
  512. }
  513. via_set_sr_int(s);
  514. break;
  515. }
  516. /* Check for state completion */
  517. if (s->cmd_state == pmu_state_cmd && s->cmdlen == s->cmd_buf_pos) {
  518. trace_pmu_debug_protocol_string("Command reception complete, "
  519. "dispatching...");
  520. pmu_dispatch_cmd(s);
  521. s->cmd_state = pmu_state_rsp;
  522. }
  523. if (s->cmd_state == pmu_state_rsp && s->rsplen == s->cmd_rsp_pos) {
  524. trace_pmu_debug_protocol_cmd_resp_complete(ms->ier);
  525. adb_autopoll_unblock(adb_bus);
  526. s->cmd_state = pmu_state_idle;
  527. }
  528. }
  529. static uint64_t mos6522_pmu_read(void *opaque, hwaddr addr, unsigned size)
  530. {
  531. PMUState *s = opaque;
  532. MOS6522PMUState *mps = &s->mos6522_pmu;
  533. MOS6522State *ms = MOS6522(mps);
  534. addr = (addr >> 9) & 0xf;
  535. return mos6522_read(ms, addr, size);
  536. }
  537. static void mos6522_pmu_write(void *opaque, hwaddr addr, uint64_t val,
  538. unsigned size)
  539. {
  540. PMUState *s = opaque;
  541. MOS6522PMUState *mps = &s->mos6522_pmu;
  542. MOS6522State *ms = MOS6522(mps);
  543. addr = (addr >> 9) & 0xf;
  544. mos6522_write(ms, addr, val, size);
  545. }
  546. static const MemoryRegionOps mos6522_pmu_ops = {
  547. .read = mos6522_pmu_read,
  548. .write = mos6522_pmu_write,
  549. .endianness = DEVICE_BIG_ENDIAN,
  550. .impl = {
  551. .min_access_size = 1,
  552. .max_access_size = 1,
  553. },
  554. };
  555. static bool pmu_adb_state_needed(void *opaque)
  556. {
  557. PMUState *s = opaque;
  558. return s->has_adb;
  559. }
  560. static const VMStateDescription vmstate_pmu_adb = {
  561. .name = "pmu/adb",
  562. .version_id = 1,
  563. .minimum_version_id = 1,
  564. .needed = pmu_adb_state_needed,
  565. .fields = (VMStateField[]) {
  566. VMSTATE_UINT8(adb_reply_size, PMUState),
  567. VMSTATE_BUFFER(adb_reply, PMUState),
  568. VMSTATE_END_OF_LIST()
  569. }
  570. };
  571. static const VMStateDescription vmstate_pmu = {
  572. .name = "pmu",
  573. .version_id = 1,
  574. .minimum_version_id = 1,
  575. .fields = (VMStateField[]) {
  576. VMSTATE_STRUCT(mos6522_pmu.parent_obj, PMUState, 0, vmstate_mos6522,
  577. MOS6522State),
  578. VMSTATE_UINT8(last_b, PMUState),
  579. VMSTATE_UINT8(cmd, PMUState),
  580. VMSTATE_UINT32(cmdlen, PMUState),
  581. VMSTATE_UINT32(rsplen, PMUState),
  582. VMSTATE_UINT8(cmd_buf_pos, PMUState),
  583. VMSTATE_BUFFER(cmd_buf, PMUState),
  584. VMSTATE_UINT8(cmd_rsp_pos, PMUState),
  585. VMSTATE_UINT8(cmd_rsp_sz, PMUState),
  586. VMSTATE_BUFFER(cmd_rsp, PMUState),
  587. VMSTATE_UINT8(intbits, PMUState),
  588. VMSTATE_UINT8(intmask, PMUState),
  589. VMSTATE_UINT32(tick_offset, PMUState),
  590. VMSTATE_TIMER_PTR(one_sec_timer, PMUState),
  591. VMSTATE_INT64(one_sec_target, PMUState),
  592. VMSTATE_END_OF_LIST()
  593. },
  594. .subsections = (const VMStateDescription * []) {
  595. &vmstate_pmu_adb,
  596. NULL
  597. }
  598. };
  599. static void pmu_reset(DeviceState *dev)
  600. {
  601. PMUState *s = VIA_PMU(dev);
  602. /* OpenBIOS needs to do this? MacOS 9 needs it */
  603. s->intmask = PMU_INT_ADB | PMU_INT_TICK;
  604. s->intbits = 0;
  605. s->cmd_state = pmu_state_idle;
  606. }
  607. static void pmu_realize(DeviceState *dev, Error **errp)
  608. {
  609. PMUState *s = VIA_PMU(dev);
  610. SysBusDevice *sbd;
  611. ADBBusState *adb_bus = &s->adb_bus;
  612. struct tm tm;
  613. if (!sysbus_realize(SYS_BUS_DEVICE(&s->mos6522_pmu), errp)) {
  614. return;
  615. }
  616. /* Pass IRQ from 6522 */
  617. sbd = SYS_BUS_DEVICE(s);
  618. sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->mos6522_pmu));
  619. qemu_get_timedate(&tm, 0);
  620. s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
  621. s->one_sec_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, pmu_one_sec_timer, s);
  622. s->one_sec_target = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000;
  623. timer_mod(s->one_sec_timer, s->one_sec_target);
  624. if (s->has_adb) {
  625. qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
  626. dev, "adb.0");
  627. adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s);
  628. }
  629. }
  630. static void pmu_init(Object *obj)
  631. {
  632. SysBusDevice *d = SYS_BUS_DEVICE(obj);
  633. PMUState *s = VIA_PMU(obj);
  634. object_property_add_link(obj, "gpio", TYPE_MACIO_GPIO,
  635. (Object **) &s->gpio,
  636. qdev_prop_allow_set_link_before_realize,
  637. 0);
  638. object_initialize_child(obj, "mos6522-pmu", &s->mos6522_pmu,
  639. TYPE_MOS6522_PMU);
  640. memory_region_init_io(&s->mem, obj, &mos6522_pmu_ops, s, "via-pmu",
  641. 0x2000);
  642. sysbus_init_mmio(d, &s->mem);
  643. }
  644. static Property pmu_properties[] = {
  645. DEFINE_PROP_BOOL("has-adb", PMUState, has_adb, true),
  646. DEFINE_PROP_END_OF_LIST()
  647. };
  648. static void pmu_class_init(ObjectClass *oc, void *data)
  649. {
  650. DeviceClass *dc = DEVICE_CLASS(oc);
  651. dc->realize = pmu_realize;
  652. dc->reset = pmu_reset;
  653. dc->vmsd = &vmstate_pmu;
  654. device_class_set_props(dc, pmu_properties);
  655. set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
  656. }
  657. static const TypeInfo pmu_type_info = {
  658. .name = TYPE_VIA_PMU,
  659. .parent = TYPE_SYS_BUS_DEVICE,
  660. .instance_size = sizeof(PMUState),
  661. .instance_init = pmu_init,
  662. .class_init = pmu_class_init,
  663. };
  664. static void mos6522_pmu_portB_write(MOS6522State *s)
  665. {
  666. MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj);
  667. PMUState *ps = container_of(mps, PMUState, mos6522_pmu);
  668. pmu_update(ps);
  669. }
  670. static void mos6522_pmu_reset_hold(Object *obj)
  671. {
  672. MOS6522State *ms = MOS6522(obj);
  673. MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj);
  674. PMUState *s = container_of(mps, PMUState, mos6522_pmu);
  675. MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
  676. if (mdc->parent_phases.hold) {
  677. mdc->parent_phases.hold(obj);
  678. }
  679. ms->timers[0].frequency = VIA_TIMER_FREQ;
  680. ms->timers[1].frequency = (SCALE_US * 6000) / 4700;
  681. s->last_b = ms->b = TACK | TREQ;
  682. }
  683. static void mos6522_pmu_class_init(ObjectClass *oc, void *data)
  684. {
  685. ResettableClass *rc = RESETTABLE_CLASS(oc);
  686. MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
  687. resettable_class_set_parent_phases(rc, NULL, mos6522_pmu_reset_hold,
  688. NULL, &mdc->parent_phases);
  689. mdc->portB_write = mos6522_pmu_portB_write;
  690. }
  691. static const TypeInfo mos6522_pmu_type_info = {
  692. .name = TYPE_MOS6522_PMU,
  693. .parent = TYPE_MOS6522,
  694. .instance_size = sizeof(MOS6522PMUState),
  695. .class_init = mos6522_pmu_class_init,
  696. };
  697. static void pmu_register_types(void)
  698. {
  699. type_register_static(&pmu_type_info);
  700. type_register_static(&mos6522_pmu_type_info);
  701. }
  702. type_init(pmu_register_types)