core.c 11 KB

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  1. /*
  2. * QEMU I2C bus interface.
  3. *
  4. * Copyright (c) 2007 CodeSourcery.
  5. * Written by Paul Brook
  6. *
  7. * This code is licensed under the LGPL.
  8. */
  9. #include "qemu/osdep.h"
  10. #include "hw/i2c/i2c.h"
  11. #include "hw/qdev-properties.h"
  12. #include "migration/vmstate.h"
  13. #include "qapi/error.h"
  14. #include "qemu/module.h"
  15. #include "qemu/main-loop.h"
  16. #include "trace.h"
  17. #define I2C_BROADCAST 0x00
  18. static Property i2c_props[] = {
  19. DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
  20. DEFINE_PROP_END_OF_LIST(),
  21. };
  22. static const TypeInfo i2c_bus_info = {
  23. .name = TYPE_I2C_BUS,
  24. .parent = TYPE_BUS,
  25. .instance_size = sizeof(I2CBus),
  26. };
  27. static int i2c_bus_pre_save(void *opaque)
  28. {
  29. I2CBus *bus = opaque;
  30. bus->saved_address = -1;
  31. if (!QLIST_EMPTY(&bus->current_devs)) {
  32. if (!bus->broadcast) {
  33. bus->saved_address = QLIST_FIRST(&bus->current_devs)->elt->address;
  34. } else {
  35. bus->saved_address = I2C_BROADCAST;
  36. }
  37. }
  38. return 0;
  39. }
  40. static const VMStateDescription vmstate_i2c_bus = {
  41. .name = "i2c_bus",
  42. .version_id = 1,
  43. .minimum_version_id = 1,
  44. .pre_save = i2c_bus_pre_save,
  45. .fields = (VMStateField[]) {
  46. VMSTATE_UINT8(saved_address, I2CBus),
  47. VMSTATE_END_OF_LIST()
  48. }
  49. };
  50. /* Create a new I2C bus. */
  51. I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
  52. {
  53. I2CBus *bus;
  54. bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
  55. QLIST_INIT(&bus->current_devs);
  56. QSIMPLEQ_INIT(&bus->pending_masters);
  57. vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_i2c_bus, bus);
  58. return bus;
  59. }
  60. void i2c_slave_set_address(I2CSlave *dev, uint8_t address)
  61. {
  62. dev->address = address;
  63. }
  64. /* Return nonzero if bus is busy. */
  65. int i2c_bus_busy(I2CBus *bus)
  66. {
  67. return !QLIST_EMPTY(&bus->current_devs) || bus->bh;
  68. }
  69. bool i2c_scan_bus(I2CBus *bus, uint8_t address, bool broadcast,
  70. I2CNodeList *current_devs)
  71. {
  72. BusChild *kid;
  73. QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
  74. DeviceState *qdev = kid->child;
  75. I2CSlave *candidate = I2C_SLAVE(qdev);
  76. I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(candidate);
  77. if (sc->match_and_add(candidate, address, broadcast, current_devs)) {
  78. if (!broadcast) {
  79. return true;
  80. }
  81. }
  82. }
  83. /*
  84. * If broadcast was true, and the list was full or empty, return true. If
  85. * broadcast was false, return false.
  86. */
  87. return broadcast;
  88. }
  89. /* TODO: Make this handle multiple masters. */
  90. /*
  91. * Start or continue an i2c transaction. When this is called for the
  92. * first time or after an i2c_end_transfer(), if it returns an error
  93. * the bus transaction is terminated (or really never started). If
  94. * this is called after another i2c_start_transfer() without an
  95. * intervening i2c_end_transfer(), and it returns an error, the
  96. * transaction will not be terminated. The caller must do it.
  97. *
  98. * This corresponds with the way real hardware works. The SMBus
  99. * protocol uses a start transfer to switch from write to read mode
  100. * without releasing the bus. If that fails, the bus is still
  101. * in a transaction.
  102. *
  103. * @event must be I2C_START_RECV or I2C_START_SEND.
  104. */
  105. static int i2c_do_start_transfer(I2CBus *bus, uint8_t address,
  106. enum i2c_event event)
  107. {
  108. I2CSlaveClass *sc;
  109. I2CNode *node;
  110. bool bus_scanned = false;
  111. if (address == I2C_BROADCAST) {
  112. /*
  113. * This is a broadcast, the current_devs will be all the devices of the
  114. * bus.
  115. */
  116. bus->broadcast = true;
  117. }
  118. /*
  119. * If there are already devices in the list, that means we are in
  120. * the middle of a transaction and we shouldn't rescan the bus.
  121. *
  122. * This happens with any SMBus transaction, even on a pure I2C
  123. * device. The interface does a transaction start without
  124. * terminating the previous transaction.
  125. */
  126. if (QLIST_EMPTY(&bus->current_devs)) {
  127. /* Disregard whether devices were found. */
  128. (void)i2c_scan_bus(bus, address, bus->broadcast, &bus->current_devs);
  129. bus_scanned = true;
  130. }
  131. if (QLIST_EMPTY(&bus->current_devs)) {
  132. return 1;
  133. }
  134. QLIST_FOREACH(node, &bus->current_devs, next) {
  135. I2CSlave *s = node->elt;
  136. int rv;
  137. sc = I2C_SLAVE_GET_CLASS(s);
  138. /* If the bus is already busy, assume this is a repeated
  139. start condition. */
  140. if (sc->event) {
  141. trace_i2c_event(event == I2C_START_SEND ? "start" : "start_async",
  142. s->address);
  143. rv = sc->event(s, event);
  144. if (rv && !bus->broadcast) {
  145. if (bus_scanned) {
  146. /* First call, terminate the transfer. */
  147. i2c_end_transfer(bus);
  148. }
  149. return rv;
  150. }
  151. }
  152. }
  153. return 0;
  154. }
  155. int i2c_start_transfer(I2CBus *bus, uint8_t address, bool is_recv)
  156. {
  157. return i2c_do_start_transfer(bus, address, is_recv
  158. ? I2C_START_RECV
  159. : I2C_START_SEND);
  160. }
  161. void i2c_bus_master(I2CBus *bus, QEMUBH *bh)
  162. {
  163. I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);
  164. node->bh = bh;
  165. QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);
  166. }
  167. void i2c_schedule_pending_master(I2CBus *bus)
  168. {
  169. I2CPendingMaster *node;
  170. if (i2c_bus_busy(bus)) {
  171. /* someone is already controlling the bus; wait for it to release it */
  172. return;
  173. }
  174. if (QSIMPLEQ_EMPTY(&bus->pending_masters)) {
  175. return;
  176. }
  177. node = QSIMPLEQ_FIRST(&bus->pending_masters);
  178. bus->bh = node->bh;
  179. QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);
  180. g_free(node);
  181. qemu_bh_schedule(bus->bh);
  182. }
  183. void i2c_bus_release(I2CBus *bus)
  184. {
  185. bus->bh = NULL;
  186. i2c_schedule_pending_master(bus);
  187. }
  188. int i2c_start_recv(I2CBus *bus, uint8_t address)
  189. {
  190. return i2c_do_start_transfer(bus, address, I2C_START_RECV);
  191. }
  192. int i2c_start_send(I2CBus *bus, uint8_t address)
  193. {
  194. return i2c_do_start_transfer(bus, address, I2C_START_SEND);
  195. }
  196. int i2c_start_send_async(I2CBus *bus, uint8_t address)
  197. {
  198. return i2c_do_start_transfer(bus, address, I2C_START_SEND_ASYNC);
  199. }
  200. void i2c_end_transfer(I2CBus *bus)
  201. {
  202. I2CSlaveClass *sc;
  203. I2CNode *node, *next;
  204. QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
  205. I2CSlave *s = node->elt;
  206. sc = I2C_SLAVE_GET_CLASS(s);
  207. if (sc->event) {
  208. trace_i2c_event("finish", s->address);
  209. sc->event(s, I2C_FINISH);
  210. }
  211. QLIST_REMOVE(node, next);
  212. g_free(node);
  213. }
  214. bus->broadcast = false;
  215. }
  216. int i2c_send(I2CBus *bus, uint8_t data)
  217. {
  218. I2CSlaveClass *sc;
  219. I2CSlave *s;
  220. I2CNode *node;
  221. int ret = 0;
  222. QLIST_FOREACH(node, &bus->current_devs, next) {
  223. s = node->elt;
  224. sc = I2C_SLAVE_GET_CLASS(s);
  225. if (sc->send) {
  226. trace_i2c_send(s->address, data);
  227. ret = ret || sc->send(s, data);
  228. } else {
  229. ret = -1;
  230. }
  231. }
  232. return ret ? -1 : 0;
  233. }
  234. int i2c_send_async(I2CBus *bus, uint8_t data)
  235. {
  236. I2CNode *node = QLIST_FIRST(&bus->current_devs);
  237. I2CSlave *slave = node->elt;
  238. I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(slave);
  239. if (!sc->send_async) {
  240. return -1;
  241. }
  242. trace_i2c_send_async(slave->address, data);
  243. sc->send_async(slave, data);
  244. return 0;
  245. }
  246. uint8_t i2c_recv(I2CBus *bus)
  247. {
  248. uint8_t data = 0xff;
  249. I2CSlaveClass *sc;
  250. I2CSlave *s;
  251. if (!QLIST_EMPTY(&bus->current_devs) && !bus->broadcast) {
  252. sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt);
  253. if (sc->recv) {
  254. s = QLIST_FIRST(&bus->current_devs)->elt;
  255. data = sc->recv(s);
  256. trace_i2c_recv(s->address, data);
  257. }
  258. }
  259. return data;
  260. }
  261. void i2c_nack(I2CBus *bus)
  262. {
  263. I2CSlaveClass *sc;
  264. I2CNode *node;
  265. if (QLIST_EMPTY(&bus->current_devs)) {
  266. return;
  267. }
  268. QLIST_FOREACH(node, &bus->current_devs, next) {
  269. sc = I2C_SLAVE_GET_CLASS(node->elt);
  270. if (sc->event) {
  271. trace_i2c_event("nack", node->elt->address);
  272. sc->event(node->elt, I2C_NACK);
  273. }
  274. }
  275. }
  276. void i2c_ack(I2CBus *bus)
  277. {
  278. if (!bus->bh) {
  279. return;
  280. }
  281. trace_i2c_ack();
  282. qemu_bh_schedule(bus->bh);
  283. }
  284. static int i2c_slave_post_load(void *opaque, int version_id)
  285. {
  286. I2CSlave *dev = opaque;
  287. I2CBus *bus;
  288. I2CNode *node;
  289. bus = I2C_BUS(qdev_get_parent_bus(DEVICE(dev)));
  290. if ((bus->saved_address == dev->address) ||
  291. (bus->saved_address == I2C_BROADCAST)) {
  292. node = g_new(struct I2CNode, 1);
  293. node->elt = dev;
  294. QLIST_INSERT_HEAD(&bus->current_devs, node, next);
  295. }
  296. return 0;
  297. }
  298. const VMStateDescription vmstate_i2c_slave = {
  299. .name = "I2CSlave",
  300. .version_id = 1,
  301. .minimum_version_id = 1,
  302. .post_load = i2c_slave_post_load,
  303. .fields = (VMStateField[]) {
  304. VMSTATE_UINT8(address, I2CSlave),
  305. VMSTATE_END_OF_LIST()
  306. }
  307. };
  308. I2CSlave *i2c_slave_new(const char *name, uint8_t addr)
  309. {
  310. DeviceState *dev;
  311. dev = qdev_new(name);
  312. qdev_prop_set_uint8(dev, "address", addr);
  313. return I2C_SLAVE(dev);
  314. }
  315. bool i2c_slave_realize_and_unref(I2CSlave *dev, I2CBus *bus, Error **errp)
  316. {
  317. return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
  318. }
  319. I2CSlave *i2c_slave_create_simple(I2CBus *bus, const char *name, uint8_t addr)
  320. {
  321. I2CSlave *dev = i2c_slave_new(name, addr);
  322. i2c_slave_realize_and_unref(dev, bus, &error_abort);
  323. return dev;
  324. }
  325. static bool i2c_slave_match(I2CSlave *candidate, uint8_t address,
  326. bool broadcast, I2CNodeList *current_devs)
  327. {
  328. if ((candidate->address == address) || (broadcast)) {
  329. I2CNode *node = g_new(struct I2CNode, 1);
  330. node->elt = candidate;
  331. QLIST_INSERT_HEAD(current_devs, node, next);
  332. return true;
  333. }
  334. /* Not found and not broadcast. */
  335. return false;
  336. }
  337. static void i2c_slave_class_init(ObjectClass *klass, void *data)
  338. {
  339. DeviceClass *k = DEVICE_CLASS(klass);
  340. I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
  341. set_bit(DEVICE_CATEGORY_MISC, k->categories);
  342. k->bus_type = TYPE_I2C_BUS;
  343. device_class_set_props(k, i2c_props);
  344. sc->match_and_add = i2c_slave_match;
  345. }
  346. static const TypeInfo i2c_slave_type_info = {
  347. .name = TYPE_I2C_SLAVE,
  348. .parent = TYPE_DEVICE,
  349. .instance_size = sizeof(I2CSlave),
  350. .abstract = true,
  351. .class_size = sizeof(I2CSlaveClass),
  352. .class_init = i2c_slave_class_init,
  353. };
  354. static void i2c_slave_register_types(void)
  355. {
  356. type_register_static(&i2c_bus_info);
  357. type_register_static(&i2c_slave_type_info);
  358. }
  359. type_init(i2c_slave_register_types)