intel-hda.c 40 KB

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  1. /*
  2. * Copyright (C) 2010 Red Hat, Inc.
  3. *
  4. * written by Gerd Hoffmann <kraxel@redhat.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 or
  9. * (at your option) version 3 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "qemu/osdep.h"
  20. #include "hw/pci/pci.h"
  21. #include "hw/qdev-properties.h"
  22. #include "hw/pci/msi.h"
  23. #include "qemu/timer.h"
  24. #include "qemu/bitops.h"
  25. #include "qemu/log.h"
  26. #include "qemu/module.h"
  27. #include "qemu/error-report.h"
  28. #include "hw/audio/soundhw.h"
  29. #include "intel-hda.h"
  30. #include "migration/vmstate.h"
  31. #include "intel-hda-defs.h"
  32. #include "sysemu/dma.h"
  33. #include "qapi/error.h"
  34. #include "qom/object.h"
  35. /* --------------------------------------------------------------------- */
  36. /* hda bus */
  37. static Property hda_props[] = {
  38. DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
  39. DEFINE_PROP_END_OF_LIST()
  40. };
  41. static const TypeInfo hda_codec_bus_info = {
  42. .name = TYPE_HDA_BUS,
  43. .parent = TYPE_BUS,
  44. .instance_size = sizeof(HDACodecBus),
  45. };
  46. void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
  47. hda_codec_response_func response,
  48. hda_codec_xfer_func xfer)
  49. {
  50. qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
  51. bus->response = response;
  52. bus->xfer = xfer;
  53. }
  54. static void hda_codec_dev_realize(DeviceState *qdev, Error **errp)
  55. {
  56. HDACodecBus *bus = HDA_BUS(qdev->parent_bus);
  57. HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
  58. HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
  59. if (dev->cad == -1) {
  60. dev->cad = bus->next_cad;
  61. }
  62. if (dev->cad >= 15) {
  63. error_setg(errp, "HDA audio codec address is full");
  64. return;
  65. }
  66. bus->next_cad = dev->cad + 1;
  67. if (cdc->init(dev) != 0) {
  68. error_setg(errp, "HDA audio init failed");
  69. }
  70. }
  71. static void hda_codec_dev_unrealize(DeviceState *qdev)
  72. {
  73. HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
  74. HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
  75. if (cdc->exit) {
  76. cdc->exit(dev);
  77. }
  78. }
  79. HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
  80. {
  81. BusChild *kid;
  82. HDACodecDevice *cdev;
  83. QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
  84. DeviceState *qdev = kid->child;
  85. cdev = HDA_CODEC_DEVICE(qdev);
  86. if (cdev->cad == cad) {
  87. return cdev;
  88. }
  89. }
  90. return NULL;
  91. }
  92. void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
  93. {
  94. HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
  95. bus->response(dev, solicited, response);
  96. }
  97. bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
  98. uint8_t *buf, uint32_t len)
  99. {
  100. HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
  101. return bus->xfer(dev, stnr, output, buf, len);
  102. }
  103. /* --------------------------------------------------------------------- */
  104. /* intel hda emulation */
  105. typedef struct IntelHDAStream IntelHDAStream;
  106. typedef struct IntelHDAState IntelHDAState;
  107. typedef struct IntelHDAReg IntelHDAReg;
  108. typedef struct bpl {
  109. uint64_t addr;
  110. uint32_t len;
  111. uint32_t flags;
  112. } bpl;
  113. struct IntelHDAStream {
  114. /* registers */
  115. uint32_t ctl;
  116. uint32_t lpib;
  117. uint32_t cbl;
  118. uint32_t lvi;
  119. uint32_t fmt;
  120. uint32_t bdlp_lbase;
  121. uint32_t bdlp_ubase;
  122. /* state */
  123. bpl *bpl;
  124. uint32_t bentries;
  125. uint32_t bsize, be, bp;
  126. };
  127. struct IntelHDAState {
  128. PCIDevice pci;
  129. const char *name;
  130. HDACodecBus codecs;
  131. /* registers */
  132. uint32_t g_ctl;
  133. uint32_t wake_en;
  134. uint32_t state_sts;
  135. uint32_t int_ctl;
  136. uint32_t int_sts;
  137. uint32_t wall_clk;
  138. uint32_t corb_lbase;
  139. uint32_t corb_ubase;
  140. uint32_t corb_rp;
  141. uint32_t corb_wp;
  142. uint32_t corb_ctl;
  143. uint32_t corb_sts;
  144. uint32_t corb_size;
  145. uint32_t rirb_lbase;
  146. uint32_t rirb_ubase;
  147. uint32_t rirb_wp;
  148. uint32_t rirb_cnt;
  149. uint32_t rirb_ctl;
  150. uint32_t rirb_sts;
  151. uint32_t rirb_size;
  152. uint32_t dp_lbase;
  153. uint32_t dp_ubase;
  154. uint32_t icw;
  155. uint32_t irr;
  156. uint32_t ics;
  157. /* streams */
  158. IntelHDAStream st[8];
  159. /* state */
  160. MemoryRegion container;
  161. MemoryRegion mmio;
  162. MemoryRegion alias;
  163. uint32_t rirb_count;
  164. int64_t wall_base_ns;
  165. /* debug logging */
  166. const IntelHDAReg *last_reg;
  167. uint32_t last_val;
  168. uint32_t last_write;
  169. uint32_t last_sec;
  170. uint32_t repeat_count;
  171. /* properties */
  172. uint32_t debug;
  173. OnOffAuto msi;
  174. bool old_msi_addr;
  175. };
  176. #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
  177. DECLARE_INSTANCE_CHECKER(IntelHDAState, INTEL_HDA,
  178. TYPE_INTEL_HDA_GENERIC)
  179. struct IntelHDAReg {
  180. const char *name; /* register name */
  181. uint32_t size; /* size in bytes */
  182. uint32_t reset; /* reset value */
  183. uint32_t wmask; /* write mask */
  184. uint32_t wclear; /* write 1 to clear bits */
  185. uint32_t offset; /* location in IntelHDAState */
  186. uint32_t shift; /* byte access entries for dwords */
  187. uint32_t stream;
  188. void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
  189. void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
  190. };
  191. /* --------------------------------------------------------------------- */
  192. static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
  193. {
  194. return ((uint64_t)ubase << 32) | lbase;
  195. }
  196. static void intel_hda_update_int_sts(IntelHDAState *d)
  197. {
  198. uint32_t sts = 0;
  199. uint32_t i;
  200. /* update controller status */
  201. if (d->rirb_sts & ICH6_RBSTS_IRQ) {
  202. sts |= (1 << 30);
  203. }
  204. if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
  205. sts |= (1 << 30);
  206. }
  207. if (d->state_sts & d->wake_en) {
  208. sts |= (1 << 30);
  209. }
  210. /* update stream status */
  211. for (i = 0; i < 8; i++) {
  212. /* buffer completion interrupt */
  213. if (d->st[i].ctl & (1 << 26)) {
  214. sts |= (1 << i);
  215. }
  216. }
  217. /* update global status */
  218. if (sts & d->int_ctl) {
  219. sts |= (1U << 31);
  220. }
  221. d->int_sts = sts;
  222. }
  223. static void intel_hda_update_irq(IntelHDAState *d)
  224. {
  225. bool msi = msi_enabled(&d->pci);
  226. int level;
  227. intel_hda_update_int_sts(d);
  228. if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) {
  229. level = 1;
  230. } else {
  231. level = 0;
  232. }
  233. dprint(d, 2, "%s: level %d [%s]\n", __func__,
  234. level, msi ? "msi" : "intx");
  235. if (msi) {
  236. if (level) {
  237. msi_notify(&d->pci, 0);
  238. }
  239. } else {
  240. pci_set_irq(&d->pci, level);
  241. }
  242. }
  243. static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
  244. {
  245. uint32_t cad, nid, data;
  246. HDACodecDevice *codec;
  247. HDACodecDeviceClass *cdc;
  248. cad = (verb >> 28) & 0x0f;
  249. if (verb & (1 << 27)) {
  250. /* indirect node addressing, not specified in HDA 1.0 */
  251. dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__);
  252. return -1;
  253. }
  254. nid = (verb >> 20) & 0x7f;
  255. data = verb & 0xfffff;
  256. codec = hda_codec_find(&d->codecs, cad);
  257. if (codec == NULL) {
  258. dprint(d, 1, "%s: addressed non-existing codec\n", __func__);
  259. return -1;
  260. }
  261. cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
  262. cdc->command(codec, nid, data);
  263. return 0;
  264. }
  265. static void intel_hda_corb_run(IntelHDAState *d)
  266. {
  267. hwaddr addr;
  268. uint32_t rp, verb;
  269. if (d->ics & ICH6_IRS_BUSY) {
  270. dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw);
  271. intel_hda_send_command(d, d->icw);
  272. return;
  273. }
  274. for (;;) {
  275. if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
  276. dprint(d, 2, "%s: !run\n", __func__);
  277. return;
  278. }
  279. if ((d->corb_rp & 0xff) == d->corb_wp) {
  280. dprint(d, 2, "%s: corb ring empty\n", __func__);
  281. return;
  282. }
  283. if (d->rirb_count == d->rirb_cnt) {
  284. dprint(d, 2, "%s: rirb count reached\n", __func__);
  285. return;
  286. }
  287. rp = (d->corb_rp + 1) & 0xff;
  288. addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
  289. ldl_le_pci_dma(&d->pci, addr + 4 * rp, &verb, MEMTXATTRS_UNSPECIFIED);
  290. d->corb_rp = rp;
  291. dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb);
  292. intel_hda_send_command(d, verb);
  293. }
  294. }
  295. static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
  296. {
  297. const MemTxAttrs attrs = { .memory = true };
  298. HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
  299. IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
  300. hwaddr addr;
  301. uint32_t wp, ex;
  302. MemTxResult res = MEMTX_OK;
  303. if (d->ics & ICH6_IRS_BUSY) {
  304. dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
  305. __func__, response, dev->cad);
  306. d->irr = response;
  307. d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
  308. d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
  309. return;
  310. }
  311. if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
  312. dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__);
  313. return;
  314. }
  315. ex = (solicited ? 0 : (1 << 4)) | dev->cad;
  316. wp = (d->rirb_wp + 1) & 0xff;
  317. addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
  318. res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs);
  319. res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs);
  320. if (res != MEMTX_OK && (d->rirb_ctl & ICH6_RBCTL_OVERRUN_EN)) {
  321. d->rirb_sts |= ICH6_RBSTS_OVERRUN;
  322. intel_hda_update_irq(d);
  323. }
  324. d->rirb_wp = wp;
  325. dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
  326. __func__, wp, response, ex);
  327. d->rirb_count++;
  328. if (d->rirb_count == d->rirb_cnt) {
  329. dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count);
  330. if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
  331. d->rirb_sts |= ICH6_RBSTS_IRQ;
  332. intel_hda_update_irq(d);
  333. }
  334. } else if ((d->corb_rp & 0xff) == d->corb_wp) {
  335. dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__,
  336. d->rirb_count, d->rirb_cnt);
  337. if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
  338. d->rirb_sts |= ICH6_RBSTS_IRQ;
  339. intel_hda_update_irq(d);
  340. }
  341. }
  342. }
  343. static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
  344. uint8_t *buf, uint32_t len)
  345. {
  346. const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
  347. HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
  348. IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
  349. hwaddr addr;
  350. uint32_t s, copy, left;
  351. IntelHDAStream *st;
  352. bool irq = false;
  353. st = output ? d->st + 4 : d->st;
  354. for (s = 0; s < 4; s++) {
  355. if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
  356. st = st + s;
  357. break;
  358. }
  359. }
  360. if (s == 4) {
  361. return false;
  362. }
  363. if (st->bpl == NULL) {
  364. return false;
  365. }
  366. left = len;
  367. s = st->bentries;
  368. while (left > 0 && s-- > 0) {
  369. copy = left;
  370. if (copy > st->bsize - st->lpib)
  371. copy = st->bsize - st->lpib;
  372. if (copy > st->bpl[st->be].len - st->bp)
  373. copy = st->bpl[st->be].len - st->bp;
  374. dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
  375. st->be, st->bp, st->bpl[st->be].len, copy);
  376. pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output,
  377. attrs);
  378. st->lpib += copy;
  379. st->bp += copy;
  380. buf += copy;
  381. left -= copy;
  382. if (st->bpl[st->be].len == st->bp) {
  383. /* bpl entry filled */
  384. if (st->bpl[st->be].flags & 0x01) {
  385. irq = true;
  386. }
  387. st->bp = 0;
  388. st->be++;
  389. if (st->be == st->bentries) {
  390. /* bpl wrap around */
  391. st->be = 0;
  392. st->lpib = 0;
  393. }
  394. }
  395. }
  396. if (d->dp_lbase & 0x01) {
  397. s = st - d->st;
  398. addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
  399. stl_le_pci_dma(&d->pci, addr + 8 * s, st->lpib, attrs);
  400. }
  401. dprint(d, 3, "dma: --\n");
  402. if (irq) {
  403. st->ctl |= (1 << 26); /* buffer completion interrupt */
  404. intel_hda_update_irq(d);
  405. }
  406. return true;
  407. }
  408. static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
  409. {
  410. hwaddr addr;
  411. uint8_t buf[16];
  412. uint32_t i;
  413. addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
  414. st->bentries = st->lvi +1;
  415. g_free(st->bpl);
  416. st->bpl = g_new(bpl, st->bentries);
  417. for (i = 0; i < st->bentries; i++, addr += 16) {
  418. pci_dma_read(&d->pci, addr, buf, 16);
  419. st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
  420. st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
  421. st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
  422. dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
  423. i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
  424. }
  425. st->bsize = st->cbl;
  426. st->lpib = 0;
  427. st->be = 0;
  428. st->bp = 0;
  429. }
  430. static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
  431. {
  432. BusChild *kid;
  433. HDACodecDevice *cdev;
  434. QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
  435. DeviceState *qdev = kid->child;
  436. HDACodecDeviceClass *cdc;
  437. cdev = HDA_CODEC_DEVICE(qdev);
  438. cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
  439. if (cdc->stream) {
  440. cdc->stream(cdev, stream, running, output);
  441. }
  442. }
  443. }
  444. /* --------------------------------------------------------------------- */
  445. static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  446. {
  447. if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
  448. device_cold_reset(DEVICE(d));
  449. }
  450. }
  451. static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  452. {
  453. intel_hda_update_irq(d);
  454. }
  455. static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  456. {
  457. intel_hda_update_irq(d);
  458. }
  459. static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  460. {
  461. intel_hda_update_irq(d);
  462. }
  463. static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
  464. {
  465. int64_t ns;
  466. ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
  467. d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
  468. }
  469. static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  470. {
  471. intel_hda_corb_run(d);
  472. }
  473. static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  474. {
  475. intel_hda_corb_run(d);
  476. }
  477. static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  478. {
  479. if (d->rirb_wp & ICH6_RIRBWP_RST) {
  480. d->rirb_wp = 0;
  481. }
  482. }
  483. static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  484. {
  485. intel_hda_update_irq(d);
  486. if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
  487. /* cleared ICH6_RBSTS_IRQ */
  488. d->rirb_count = 0;
  489. intel_hda_corb_run(d);
  490. }
  491. }
  492. static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  493. {
  494. if (d->ics & ICH6_IRS_BUSY) {
  495. intel_hda_corb_run(d);
  496. }
  497. }
  498. static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
  499. {
  500. bool output = reg->stream >= 4;
  501. IntelHDAStream *st = d->st + reg->stream;
  502. if (st->ctl & 0x01) {
  503. /* reset */
  504. dprint(d, 1, "st #%d: reset\n", reg->stream);
  505. st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET;
  506. }
  507. if ((st->ctl & 0x02) != (old & 0x02)) {
  508. uint32_t stnr = (st->ctl >> 20) & 0x0f;
  509. /* run bit flipped */
  510. if (st->ctl & 0x02) {
  511. /* start */
  512. dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
  513. reg->stream, stnr, st->cbl);
  514. intel_hda_parse_bdl(d, st);
  515. intel_hda_notify_codecs(d, stnr, true, output);
  516. } else {
  517. /* stop */
  518. dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
  519. intel_hda_notify_codecs(d, stnr, false, output);
  520. }
  521. }
  522. intel_hda_update_irq(d);
  523. }
  524. /* --------------------------------------------------------------------- */
  525. #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
  526. static const struct IntelHDAReg regtab[] = {
  527. /* global */
  528. [ ICH6_REG_GCAP ] = {
  529. .name = "GCAP",
  530. .size = 2,
  531. .reset = 0x4401,
  532. },
  533. [ ICH6_REG_VMIN ] = {
  534. .name = "VMIN",
  535. .size = 1,
  536. },
  537. [ ICH6_REG_VMAJ ] = {
  538. .name = "VMAJ",
  539. .size = 1,
  540. .reset = 1,
  541. },
  542. [ ICH6_REG_OUTPAY ] = {
  543. .name = "OUTPAY",
  544. .size = 2,
  545. .reset = 0x3c,
  546. },
  547. [ ICH6_REG_INPAY ] = {
  548. .name = "INPAY",
  549. .size = 2,
  550. .reset = 0x1d,
  551. },
  552. [ ICH6_REG_GCTL ] = {
  553. .name = "GCTL",
  554. .size = 4,
  555. .wmask = 0x0103,
  556. .offset = offsetof(IntelHDAState, g_ctl),
  557. .whandler = intel_hda_set_g_ctl,
  558. },
  559. [ ICH6_REG_WAKEEN ] = {
  560. .name = "WAKEEN",
  561. .size = 2,
  562. .wmask = 0x7fff,
  563. .offset = offsetof(IntelHDAState, wake_en),
  564. .whandler = intel_hda_set_wake_en,
  565. },
  566. [ ICH6_REG_STATESTS ] = {
  567. .name = "STATESTS",
  568. .size = 2,
  569. .wmask = 0x7fff,
  570. .wclear = 0x7fff,
  571. .offset = offsetof(IntelHDAState, state_sts),
  572. .whandler = intel_hda_set_state_sts,
  573. },
  574. /* interrupts */
  575. [ ICH6_REG_INTCTL ] = {
  576. .name = "INTCTL",
  577. .size = 4,
  578. .wmask = 0xc00000ff,
  579. .offset = offsetof(IntelHDAState, int_ctl),
  580. .whandler = intel_hda_set_int_ctl,
  581. },
  582. [ ICH6_REG_INTSTS ] = {
  583. .name = "INTSTS",
  584. .size = 4,
  585. .wmask = 0xc00000ff,
  586. .wclear = 0xc00000ff,
  587. .offset = offsetof(IntelHDAState, int_sts),
  588. },
  589. /* misc */
  590. [ ICH6_REG_WALLCLK ] = {
  591. .name = "WALLCLK",
  592. .size = 4,
  593. .offset = offsetof(IntelHDAState, wall_clk),
  594. .rhandler = intel_hda_get_wall_clk,
  595. },
  596. /* dma engine */
  597. [ ICH6_REG_CORBLBASE ] = {
  598. .name = "CORBLBASE",
  599. .size = 4,
  600. .wmask = 0xffffff80,
  601. .offset = offsetof(IntelHDAState, corb_lbase),
  602. },
  603. [ ICH6_REG_CORBUBASE ] = {
  604. .name = "CORBUBASE",
  605. .size = 4,
  606. .wmask = 0xffffffff,
  607. .offset = offsetof(IntelHDAState, corb_ubase),
  608. },
  609. [ ICH6_REG_CORBWP ] = {
  610. .name = "CORBWP",
  611. .size = 2,
  612. .wmask = 0xff,
  613. .offset = offsetof(IntelHDAState, corb_wp),
  614. .whandler = intel_hda_set_corb_wp,
  615. },
  616. [ ICH6_REG_CORBRP ] = {
  617. .name = "CORBRP",
  618. .size = 2,
  619. .wmask = 0x80ff,
  620. .offset = offsetof(IntelHDAState, corb_rp),
  621. },
  622. [ ICH6_REG_CORBCTL ] = {
  623. .name = "CORBCTL",
  624. .size = 1,
  625. .wmask = 0x03,
  626. .offset = offsetof(IntelHDAState, corb_ctl),
  627. .whandler = intel_hda_set_corb_ctl,
  628. },
  629. [ ICH6_REG_CORBSTS ] = {
  630. .name = "CORBSTS",
  631. .size = 1,
  632. .wmask = 0x01,
  633. .wclear = 0x01,
  634. .offset = offsetof(IntelHDAState, corb_sts),
  635. },
  636. [ ICH6_REG_CORBSIZE ] = {
  637. .name = "CORBSIZE",
  638. .size = 1,
  639. .reset = 0x42,
  640. .offset = offsetof(IntelHDAState, corb_size),
  641. },
  642. [ ICH6_REG_RIRBLBASE ] = {
  643. .name = "RIRBLBASE",
  644. .size = 4,
  645. .wmask = 0xffffff80,
  646. .offset = offsetof(IntelHDAState, rirb_lbase),
  647. },
  648. [ ICH6_REG_RIRBUBASE ] = {
  649. .name = "RIRBUBASE",
  650. .size = 4,
  651. .wmask = 0xffffffff,
  652. .offset = offsetof(IntelHDAState, rirb_ubase),
  653. },
  654. [ ICH6_REG_RIRBWP ] = {
  655. .name = "RIRBWP",
  656. .size = 2,
  657. .wmask = 0x8000,
  658. .offset = offsetof(IntelHDAState, rirb_wp),
  659. .whandler = intel_hda_set_rirb_wp,
  660. },
  661. [ ICH6_REG_RINTCNT ] = {
  662. .name = "RINTCNT",
  663. .size = 2,
  664. .wmask = 0xff,
  665. .offset = offsetof(IntelHDAState, rirb_cnt),
  666. },
  667. [ ICH6_REG_RIRBCTL ] = {
  668. .name = "RIRBCTL",
  669. .size = 1,
  670. .wmask = 0x07,
  671. .offset = offsetof(IntelHDAState, rirb_ctl),
  672. },
  673. [ ICH6_REG_RIRBSTS ] = {
  674. .name = "RIRBSTS",
  675. .size = 1,
  676. .wmask = 0x05,
  677. .wclear = 0x05,
  678. .offset = offsetof(IntelHDAState, rirb_sts),
  679. .whandler = intel_hda_set_rirb_sts,
  680. },
  681. [ ICH6_REG_RIRBSIZE ] = {
  682. .name = "RIRBSIZE",
  683. .size = 1,
  684. .reset = 0x42,
  685. .offset = offsetof(IntelHDAState, rirb_size),
  686. },
  687. [ ICH6_REG_DPLBASE ] = {
  688. .name = "DPLBASE",
  689. .size = 4,
  690. .wmask = 0xffffff81,
  691. .offset = offsetof(IntelHDAState, dp_lbase),
  692. },
  693. [ ICH6_REG_DPUBASE ] = {
  694. .name = "DPUBASE",
  695. .size = 4,
  696. .wmask = 0xffffffff,
  697. .offset = offsetof(IntelHDAState, dp_ubase),
  698. },
  699. [ ICH6_REG_IC ] = {
  700. .name = "ICW",
  701. .size = 4,
  702. .wmask = 0xffffffff,
  703. .offset = offsetof(IntelHDAState, icw),
  704. },
  705. [ ICH6_REG_IR ] = {
  706. .name = "IRR",
  707. .size = 4,
  708. .offset = offsetof(IntelHDAState, irr),
  709. },
  710. [ ICH6_REG_IRS ] = {
  711. .name = "ICS",
  712. .size = 2,
  713. .wmask = 0x0003,
  714. .wclear = 0x0002,
  715. .offset = offsetof(IntelHDAState, ics),
  716. .whandler = intel_hda_set_ics,
  717. },
  718. #define HDA_STREAM(_t, _i) \
  719. [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
  720. .stream = _i, \
  721. .name = _t stringify(_i) " CTL", \
  722. .size = 4, \
  723. .wmask = 0x1cff001f, \
  724. .offset = offsetof(IntelHDAState, st[_i].ctl), \
  725. .whandler = intel_hda_set_st_ctl, \
  726. }, \
  727. [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
  728. .stream = _i, \
  729. .name = _t stringify(_i) " CTL(stnr)", \
  730. .size = 1, \
  731. .shift = 16, \
  732. .wmask = 0x00ff0000, \
  733. .offset = offsetof(IntelHDAState, st[_i].ctl), \
  734. .whandler = intel_hda_set_st_ctl, \
  735. }, \
  736. [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
  737. .stream = _i, \
  738. .name = _t stringify(_i) " CTL(sts)", \
  739. .size = 1, \
  740. .shift = 24, \
  741. .wmask = 0x1c000000, \
  742. .wclear = 0x1c000000, \
  743. .offset = offsetof(IntelHDAState, st[_i].ctl), \
  744. .whandler = intel_hda_set_st_ctl, \
  745. .reset = SD_STS_FIFO_READY << 24 \
  746. }, \
  747. [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
  748. .stream = _i, \
  749. .name = _t stringify(_i) " LPIB", \
  750. .size = 4, \
  751. .offset = offsetof(IntelHDAState, st[_i].lpib), \
  752. }, \
  753. [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
  754. .stream = _i, \
  755. .name = _t stringify(_i) " CBL", \
  756. .size = 4, \
  757. .wmask = 0xffffffff, \
  758. .offset = offsetof(IntelHDAState, st[_i].cbl), \
  759. }, \
  760. [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
  761. .stream = _i, \
  762. .name = _t stringify(_i) " LVI", \
  763. .size = 2, \
  764. .wmask = 0x00ff, \
  765. .offset = offsetof(IntelHDAState, st[_i].lvi), \
  766. }, \
  767. [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
  768. .stream = _i, \
  769. .name = _t stringify(_i) " FIFOS", \
  770. .size = 2, \
  771. .reset = HDA_BUFFER_SIZE, \
  772. }, \
  773. [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
  774. .stream = _i, \
  775. .name = _t stringify(_i) " FMT", \
  776. .size = 2, \
  777. .wmask = 0x7f7f, \
  778. .offset = offsetof(IntelHDAState, st[_i].fmt), \
  779. }, \
  780. [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
  781. .stream = _i, \
  782. .name = _t stringify(_i) " BDLPL", \
  783. .size = 4, \
  784. .wmask = 0xffffff80, \
  785. .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
  786. }, \
  787. [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
  788. .stream = _i, \
  789. .name = _t stringify(_i) " BDLPU", \
  790. .size = 4, \
  791. .wmask = 0xffffffff, \
  792. .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
  793. }, \
  794. HDA_STREAM("IN", 0)
  795. HDA_STREAM("IN", 1)
  796. HDA_STREAM("IN", 2)
  797. HDA_STREAM("IN", 3)
  798. HDA_STREAM("OUT", 4)
  799. HDA_STREAM("OUT", 5)
  800. HDA_STREAM("OUT", 6)
  801. HDA_STREAM("OUT", 7)
  802. };
  803. static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
  804. {
  805. const IntelHDAReg *reg;
  806. if (addr >= ARRAY_SIZE(regtab)) {
  807. goto noreg;
  808. }
  809. reg = regtab+addr;
  810. if (reg->name == NULL) {
  811. goto noreg;
  812. }
  813. return reg;
  814. noreg:
  815. dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
  816. return NULL;
  817. }
  818. static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
  819. {
  820. uint8_t *addr = (void*)d;
  821. addr += reg->offset;
  822. return (uint32_t*)addr;
  823. }
  824. static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
  825. uint32_t wmask)
  826. {
  827. uint32_t *addr;
  828. uint32_t old;
  829. if (!reg) {
  830. return;
  831. }
  832. if (!reg->wmask) {
  833. qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n",
  834. reg->name);
  835. return;
  836. }
  837. if (d->debug) {
  838. time_t now = time(NULL);
  839. if (d->last_write && d->last_reg == reg && d->last_val == val) {
  840. d->repeat_count++;
  841. if (d->last_sec != now) {
  842. dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
  843. d->last_sec = now;
  844. d->repeat_count = 0;
  845. }
  846. } else {
  847. if (d->repeat_count) {
  848. dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
  849. }
  850. dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
  851. d->last_write = 1;
  852. d->last_reg = reg;
  853. d->last_val = val;
  854. d->last_sec = now;
  855. d->repeat_count = 0;
  856. }
  857. }
  858. assert(reg->offset != 0);
  859. addr = intel_hda_reg_addr(d, reg);
  860. old = *addr;
  861. if (reg->shift) {
  862. val <<= reg->shift;
  863. wmask <<= reg->shift;
  864. }
  865. wmask &= reg->wmask;
  866. *addr &= ~wmask;
  867. *addr |= wmask & val;
  868. *addr &= ~(val & reg->wclear);
  869. if (reg->whandler) {
  870. reg->whandler(d, reg, old);
  871. }
  872. }
  873. static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
  874. uint32_t rmask)
  875. {
  876. uint32_t *addr, ret;
  877. if (!reg) {
  878. return 0;
  879. }
  880. if (reg->rhandler) {
  881. reg->rhandler(d, reg);
  882. }
  883. if (reg->offset == 0) {
  884. /* constant read-only register */
  885. ret = reg->reset;
  886. } else {
  887. addr = intel_hda_reg_addr(d, reg);
  888. ret = *addr;
  889. if (reg->shift) {
  890. ret >>= reg->shift;
  891. }
  892. ret &= rmask;
  893. }
  894. if (d->debug) {
  895. time_t now = time(NULL);
  896. if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
  897. d->repeat_count++;
  898. if (d->last_sec != now) {
  899. dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
  900. d->last_sec = now;
  901. d->repeat_count = 0;
  902. }
  903. } else {
  904. if (d->repeat_count) {
  905. dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
  906. }
  907. dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
  908. d->last_write = 0;
  909. d->last_reg = reg;
  910. d->last_val = ret;
  911. d->last_sec = now;
  912. d->repeat_count = 0;
  913. }
  914. }
  915. return ret;
  916. }
  917. static void intel_hda_regs_reset(IntelHDAState *d)
  918. {
  919. uint32_t *addr;
  920. int i;
  921. for (i = 0; i < ARRAY_SIZE(regtab); i++) {
  922. if (regtab[i].name == NULL) {
  923. continue;
  924. }
  925. if (regtab[i].offset == 0) {
  926. continue;
  927. }
  928. addr = intel_hda_reg_addr(d, regtab + i);
  929. *addr = regtab[i].reset;
  930. }
  931. }
  932. /* --------------------------------------------------------------------- */
  933. static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val,
  934. unsigned size)
  935. {
  936. IntelHDAState *d = opaque;
  937. const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
  938. intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8));
  939. }
  940. static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size)
  941. {
  942. IntelHDAState *d = opaque;
  943. const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
  944. return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8));
  945. }
  946. static const MemoryRegionOps intel_hda_mmio_ops = {
  947. .read = intel_hda_mmio_read,
  948. .write = intel_hda_mmio_write,
  949. .impl = {
  950. .min_access_size = 1,
  951. .max_access_size = 4,
  952. },
  953. .endianness = DEVICE_NATIVE_ENDIAN,
  954. };
  955. /* --------------------------------------------------------------------- */
  956. static void intel_hda_reset(DeviceState *dev)
  957. {
  958. BusChild *kid;
  959. IntelHDAState *d = INTEL_HDA(dev);
  960. HDACodecDevice *cdev;
  961. intel_hda_regs_reset(d);
  962. d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  963. QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
  964. DeviceState *qdev = kid->child;
  965. cdev = HDA_CODEC_DEVICE(qdev);
  966. d->state_sts |= (1 << cdev->cad);
  967. }
  968. intel_hda_update_irq(d);
  969. }
  970. static void intel_hda_realize(PCIDevice *pci, Error **errp)
  971. {
  972. IntelHDAState *d = INTEL_HDA(pci);
  973. uint8_t *conf = d->pci.config;
  974. Error *err = NULL;
  975. int ret;
  976. d->name = object_get_typename(OBJECT(d));
  977. pci_config_set_interrupt_pin(conf, 1);
  978. /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
  979. conf[0x40] = 0x01;
  980. if (d->msi != ON_OFF_AUTO_OFF) {
  981. ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60,
  982. 1, true, false, &err);
  983. /* Any error other than -ENOTSUP(board's MSI support is broken)
  984. * is a programming error */
  985. assert(!ret || ret == -ENOTSUP);
  986. if (ret && d->msi == ON_OFF_AUTO_ON) {
  987. /* Can't satisfy user's explicit msi=on request, fail */
  988. error_append_hint(&err, "You have to use msi=auto (default) or "
  989. "msi=off with this machine type.\n");
  990. error_propagate(errp, err);
  991. return;
  992. }
  993. assert(!err || d->msi == ON_OFF_AUTO_AUTO);
  994. /* With msi=auto, we fall back to MSI off silently */
  995. error_free(err);
  996. }
  997. memory_region_init(&d->container, OBJECT(d),
  998. "intel-hda-container", 0x4000);
  999. memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
  1000. "intel-hda", 0x2000);
  1001. memory_region_add_subregion(&d->container, 0x0000, &d->mmio);
  1002. memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias",
  1003. &d->mmio, 0, 0x2000);
  1004. memory_region_add_subregion(&d->container, 0x2000, &d->alias);
  1005. pci_register_bar(&d->pci, 0, 0, &d->container);
  1006. hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
  1007. intel_hda_response, intel_hda_xfer);
  1008. }
  1009. static void intel_hda_exit(PCIDevice *pci)
  1010. {
  1011. IntelHDAState *d = INTEL_HDA(pci);
  1012. msi_uninit(&d->pci);
  1013. }
  1014. static int intel_hda_post_load(void *opaque, int version)
  1015. {
  1016. IntelHDAState* d = opaque;
  1017. int i;
  1018. dprint(d, 1, "%s\n", __func__);
  1019. for (i = 0; i < ARRAY_SIZE(d->st); i++) {
  1020. if (d->st[i].ctl & 0x02) {
  1021. intel_hda_parse_bdl(d, &d->st[i]);
  1022. }
  1023. }
  1024. intel_hda_update_irq(d);
  1025. return 0;
  1026. }
  1027. static const VMStateDescription vmstate_intel_hda_stream = {
  1028. .name = "intel-hda-stream",
  1029. .version_id = 1,
  1030. .fields = (VMStateField[]) {
  1031. VMSTATE_UINT32(ctl, IntelHDAStream),
  1032. VMSTATE_UINT32(lpib, IntelHDAStream),
  1033. VMSTATE_UINT32(cbl, IntelHDAStream),
  1034. VMSTATE_UINT32(lvi, IntelHDAStream),
  1035. VMSTATE_UINT32(fmt, IntelHDAStream),
  1036. VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
  1037. VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
  1038. VMSTATE_END_OF_LIST()
  1039. }
  1040. };
  1041. static const VMStateDescription vmstate_intel_hda = {
  1042. .name = "intel-hda",
  1043. .version_id = 1,
  1044. .post_load = intel_hda_post_load,
  1045. .fields = (VMStateField[]) {
  1046. VMSTATE_PCI_DEVICE(pci, IntelHDAState),
  1047. /* registers */
  1048. VMSTATE_UINT32(g_ctl, IntelHDAState),
  1049. VMSTATE_UINT32(wake_en, IntelHDAState),
  1050. VMSTATE_UINT32(state_sts, IntelHDAState),
  1051. VMSTATE_UINT32(int_ctl, IntelHDAState),
  1052. VMSTATE_UINT32(int_sts, IntelHDAState),
  1053. VMSTATE_UINT32(wall_clk, IntelHDAState),
  1054. VMSTATE_UINT32(corb_lbase, IntelHDAState),
  1055. VMSTATE_UINT32(corb_ubase, IntelHDAState),
  1056. VMSTATE_UINT32(corb_rp, IntelHDAState),
  1057. VMSTATE_UINT32(corb_wp, IntelHDAState),
  1058. VMSTATE_UINT32(corb_ctl, IntelHDAState),
  1059. VMSTATE_UINT32(corb_sts, IntelHDAState),
  1060. VMSTATE_UINT32(corb_size, IntelHDAState),
  1061. VMSTATE_UINT32(rirb_lbase, IntelHDAState),
  1062. VMSTATE_UINT32(rirb_ubase, IntelHDAState),
  1063. VMSTATE_UINT32(rirb_wp, IntelHDAState),
  1064. VMSTATE_UINT32(rirb_cnt, IntelHDAState),
  1065. VMSTATE_UINT32(rirb_ctl, IntelHDAState),
  1066. VMSTATE_UINT32(rirb_sts, IntelHDAState),
  1067. VMSTATE_UINT32(rirb_size, IntelHDAState),
  1068. VMSTATE_UINT32(dp_lbase, IntelHDAState),
  1069. VMSTATE_UINT32(dp_ubase, IntelHDAState),
  1070. VMSTATE_UINT32(icw, IntelHDAState),
  1071. VMSTATE_UINT32(irr, IntelHDAState),
  1072. VMSTATE_UINT32(ics, IntelHDAState),
  1073. VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
  1074. vmstate_intel_hda_stream,
  1075. IntelHDAStream),
  1076. /* additional state info */
  1077. VMSTATE_UINT32(rirb_count, IntelHDAState),
  1078. VMSTATE_INT64(wall_base_ns, IntelHDAState),
  1079. VMSTATE_END_OF_LIST()
  1080. }
  1081. };
  1082. static Property intel_hda_properties[] = {
  1083. DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
  1084. DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO),
  1085. DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false),
  1086. DEFINE_PROP_END_OF_LIST(),
  1087. };
  1088. static void intel_hda_class_init(ObjectClass *klass, void *data)
  1089. {
  1090. DeviceClass *dc = DEVICE_CLASS(klass);
  1091. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  1092. k->realize = intel_hda_realize;
  1093. k->exit = intel_hda_exit;
  1094. k->vendor_id = PCI_VENDOR_ID_INTEL;
  1095. k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
  1096. dc->reset = intel_hda_reset;
  1097. dc->vmsd = &vmstate_intel_hda;
  1098. device_class_set_props(dc, intel_hda_properties);
  1099. }
  1100. static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
  1101. {
  1102. DeviceClass *dc = DEVICE_CLASS(klass);
  1103. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  1104. k->device_id = 0x2668;
  1105. k->revision = 1;
  1106. set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
  1107. dc->desc = "Intel HD Audio Controller (ich6)";
  1108. }
  1109. static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
  1110. {
  1111. DeviceClass *dc = DEVICE_CLASS(klass);
  1112. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  1113. k->device_id = 0x293e;
  1114. k->revision = 3;
  1115. set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
  1116. dc->desc = "Intel HD Audio Controller (ich9)";
  1117. }
  1118. static const TypeInfo intel_hda_info = {
  1119. .name = TYPE_INTEL_HDA_GENERIC,
  1120. .parent = TYPE_PCI_DEVICE,
  1121. .instance_size = sizeof(IntelHDAState),
  1122. .class_init = intel_hda_class_init,
  1123. .abstract = true,
  1124. .interfaces = (InterfaceInfo[]) {
  1125. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  1126. { },
  1127. },
  1128. };
  1129. static const TypeInfo intel_hda_info_ich6 = {
  1130. .name = "intel-hda",
  1131. .parent = TYPE_INTEL_HDA_GENERIC,
  1132. .class_init = intel_hda_class_init_ich6,
  1133. };
  1134. static const TypeInfo intel_hda_info_ich9 = {
  1135. .name = "ich9-intel-hda",
  1136. .parent = TYPE_INTEL_HDA_GENERIC,
  1137. .class_init = intel_hda_class_init_ich9,
  1138. };
  1139. static void hda_codec_device_class_init(ObjectClass *klass, void *data)
  1140. {
  1141. DeviceClass *k = DEVICE_CLASS(klass);
  1142. k->realize = hda_codec_dev_realize;
  1143. k->unrealize = hda_codec_dev_unrealize;
  1144. set_bit(DEVICE_CATEGORY_SOUND, k->categories);
  1145. k->bus_type = TYPE_HDA_BUS;
  1146. device_class_set_props(k, hda_props);
  1147. }
  1148. static const TypeInfo hda_codec_device_type_info = {
  1149. .name = TYPE_HDA_CODEC_DEVICE,
  1150. .parent = TYPE_DEVICE,
  1151. .instance_size = sizeof(HDACodecDevice),
  1152. .abstract = true,
  1153. .class_size = sizeof(HDACodecDeviceClass),
  1154. .class_init = hda_codec_device_class_init,
  1155. };
  1156. /*
  1157. * create intel hda controller with codec attached to it,
  1158. * so '-soundhw hda' works.
  1159. */
  1160. static int intel_hda_and_codec_init(PCIBus *bus, const char *audiodev)
  1161. {
  1162. DeviceState *controller;
  1163. BusState *hdabus;
  1164. DeviceState *codec;
  1165. controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
  1166. hdabus = QLIST_FIRST(&controller->child_bus);
  1167. codec = qdev_new("hda-duplex");
  1168. qdev_prop_set_string(codec, "audiodev", audiodev);
  1169. qdev_realize_and_unref(codec, hdabus, &error_fatal);
  1170. return 0;
  1171. }
  1172. static void intel_hda_register_types(void)
  1173. {
  1174. type_register_static(&hda_codec_bus_info);
  1175. type_register_static(&intel_hda_info);
  1176. type_register_static(&intel_hda_info_ich6);
  1177. type_register_static(&intel_hda_info_ich9);
  1178. type_register_static(&hda_codec_device_type_info);
  1179. pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
  1180. }
  1181. type_init(intel_hda_register_types)