cpu_loop.c 11 KB

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  1. /*
  2. * qemu user cpu loop
  3. *
  4. * Copyright (c) 2003-2008 Fabrice Bellard
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "qemu/osdep.h"
  20. #include "qemu.h"
  21. #include "user-internals.h"
  22. #include "cpu_loop-common.h"
  23. #include "signal-common.h"
  24. #define SPARC64_STACK_BIAS 2047
  25. //#define DEBUG_WIN
  26. /* WARNING: dealing with register windows _is_ complicated. More info
  27. can be found at http://www.sics.se/~psm/sparcstack.html */
  28. static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
  29. {
  30. index = (index + cwp * 16) % (16 * env->nwindows);
  31. /* wrap handling : if cwp is on the last window, then we use the
  32. registers 'after' the end */
  33. if (index < 8 && env->cwp == env->nwindows - 1)
  34. index += 16 * env->nwindows;
  35. return index;
  36. }
  37. /* save the register window 'cwp1' */
  38. static inline void save_window_offset(CPUSPARCState *env, int cwp1)
  39. {
  40. unsigned int i;
  41. abi_ulong sp_ptr;
  42. sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
  43. #ifdef TARGET_SPARC64
  44. if (sp_ptr & 3)
  45. sp_ptr += SPARC64_STACK_BIAS;
  46. #endif
  47. #if defined(DEBUG_WIN)
  48. printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
  49. sp_ptr, cwp1);
  50. #endif
  51. for(i = 0; i < 16; i++) {
  52. /* FIXME - what to do if put_user() fails? */
  53. put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
  54. sp_ptr += sizeof(abi_ulong);
  55. }
  56. }
  57. static void save_window(CPUSPARCState *env)
  58. {
  59. #ifndef TARGET_SPARC64
  60. unsigned int new_wim;
  61. new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
  62. ((1LL << env->nwindows) - 1);
  63. save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
  64. env->wim = new_wim;
  65. #else
  66. /*
  67. * cansave is zero if the spill trap handler is triggered by `save` and
  68. * nonzero if triggered by a `flushw`
  69. */
  70. save_window_offset(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
  71. env->cansave++;
  72. env->canrestore--;
  73. #endif
  74. }
  75. static void restore_window(CPUSPARCState *env)
  76. {
  77. #ifndef TARGET_SPARC64
  78. unsigned int new_wim;
  79. #endif
  80. unsigned int i, cwp1;
  81. abi_ulong sp_ptr;
  82. #ifndef TARGET_SPARC64
  83. new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
  84. ((1LL << env->nwindows) - 1);
  85. #endif
  86. /* restore the invalid window */
  87. cwp1 = cpu_cwp_inc(env, env->cwp + 1);
  88. sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
  89. #ifdef TARGET_SPARC64
  90. if (sp_ptr & 3)
  91. sp_ptr += SPARC64_STACK_BIAS;
  92. #endif
  93. #if defined(DEBUG_WIN)
  94. printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
  95. sp_ptr, cwp1);
  96. #endif
  97. for(i = 0; i < 16; i++) {
  98. /* FIXME - what to do if get_user() fails? */
  99. get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
  100. sp_ptr += sizeof(abi_ulong);
  101. }
  102. #ifdef TARGET_SPARC64
  103. env->canrestore++;
  104. if (env->cleanwin < env->nwindows - 1)
  105. env->cleanwin++;
  106. env->cansave--;
  107. #else
  108. env->wim = new_wim;
  109. #endif
  110. }
  111. static void flush_windows(CPUSPARCState *env)
  112. {
  113. int offset, cwp1;
  114. offset = 1;
  115. for(;;) {
  116. /* if restore would invoke restore_window(), then we can stop */
  117. cwp1 = cpu_cwp_inc(env, env->cwp + offset);
  118. #ifndef TARGET_SPARC64
  119. if (env->wim & (1 << cwp1))
  120. break;
  121. #else
  122. if (env->canrestore == 0)
  123. break;
  124. env->cansave++;
  125. env->canrestore--;
  126. #endif
  127. save_window_offset(env, cwp1);
  128. offset++;
  129. }
  130. cwp1 = cpu_cwp_inc(env, env->cwp + 1);
  131. #ifndef TARGET_SPARC64
  132. /* set wim so that restore will reload the registers */
  133. env->wim = 1 << cwp1;
  134. #endif
  135. #if defined(DEBUG_WIN)
  136. printf("flush_windows: nb=%d\n", offset - 1);
  137. #endif
  138. }
  139. static void next_instruction(CPUSPARCState *env)
  140. {
  141. env->pc = env->npc;
  142. env->npc = env->npc + 4;
  143. }
  144. static uint32_t do_getcc(CPUSPARCState *env)
  145. {
  146. #ifdef TARGET_SPARC64
  147. return cpu_get_ccr(env) & 0xf;
  148. #else
  149. return extract32(cpu_get_psr(env), 20, 4);
  150. #endif
  151. }
  152. static void do_setcc(CPUSPARCState *env, uint32_t icc)
  153. {
  154. #ifdef TARGET_SPARC64
  155. cpu_put_ccr(env, (cpu_get_ccr(env) & 0xf0) | (icc & 0xf));
  156. #else
  157. cpu_put_psr(env, deposit32(cpu_get_psr(env), 20, 4, icc));
  158. #endif
  159. }
  160. static uint32_t do_getpsr(CPUSPARCState *env)
  161. {
  162. #ifdef TARGET_SPARC64
  163. const uint64_t TSTATE_CWP = 0x1f;
  164. const uint64_t TSTATE_ICC = 0xfull << 32;
  165. const uint64_t TSTATE_XCC = 0xfull << 36;
  166. const uint32_t PSR_S = 0x00000080u;
  167. const uint32_t PSR_V8PLUS = 0xff000000u;
  168. uint64_t tstate = sparc64_tstate(env);
  169. /* See <asm/psrcompat.h>, tstate_to_psr. */
  170. return ((tstate & TSTATE_CWP) |
  171. PSR_S |
  172. ((tstate & TSTATE_ICC) >> 12) |
  173. ((tstate & TSTATE_XCC) >> 20) |
  174. PSR_V8PLUS);
  175. #else
  176. return (cpu_get_psr(env) & (PSR_ICC | PSR_CWP)) | PSR_S;
  177. #endif
  178. }
  179. /* Avoid ifdefs below for the abi32 and abi64 paths. */
  180. #ifdef TARGET_ABI32
  181. #define TARGET_TT_SYSCALL (TT_TRAP + 0x10) /* t_linux */
  182. #define syscall_cc psr
  183. #else
  184. #define TARGET_TT_SYSCALL (TT_TRAP + 0x6d) /* tl0_linux64 */
  185. #define syscall_cc xcc
  186. #endif
  187. /* Avoid ifdefs below for the v9 and pre-v9 hw traps. */
  188. #ifdef TARGET_SPARC64
  189. #define TARGET_TT_SPILL TT_SPILL
  190. #define TARGET_TT_FILL TT_FILL
  191. #else
  192. #define TARGET_TT_SPILL TT_WIN_OVF
  193. #define TARGET_TT_FILL TT_WIN_UNF
  194. #endif
  195. void cpu_loop (CPUSPARCState *env)
  196. {
  197. CPUState *cs = env_cpu(env);
  198. int trapnr;
  199. abi_long ret;
  200. while (1) {
  201. cpu_exec_start(cs);
  202. trapnr = cpu_exec(cs);
  203. cpu_exec_end(cs);
  204. process_queued_cpu_work(cs);
  205. /* Compute PSR before exposing state. */
  206. if (env->cc_op != CC_OP_FLAGS) {
  207. cpu_get_psr(env);
  208. }
  209. switch (trapnr) {
  210. case TARGET_TT_SYSCALL:
  211. ret = do_syscall (env, env->gregs[1],
  212. env->regwptr[0], env->regwptr[1],
  213. env->regwptr[2], env->regwptr[3],
  214. env->regwptr[4], env->regwptr[5],
  215. 0, 0);
  216. if (ret == -QEMU_ERESTARTSYS || ret == -QEMU_ESIGRETURN) {
  217. break;
  218. }
  219. if ((abi_ulong)ret >= (abi_ulong)(-515)) {
  220. env->syscall_cc |= PSR_CARRY;
  221. ret = -ret;
  222. } else {
  223. env->syscall_cc &= ~PSR_CARRY;
  224. }
  225. env->regwptr[0] = ret;
  226. /* next instruction */
  227. env->pc = env->npc;
  228. env->npc = env->npc + 4;
  229. break;
  230. case TT_TRAP + 0x01: /* breakpoint */
  231. case EXCP_DEBUG:
  232. force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
  233. break;
  234. case TT_TRAP + 0x02: /* div0 */
  235. case TT_DIV_ZERO:
  236. force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc);
  237. break;
  238. case TT_TRAP + 0x03: /* flush windows */
  239. flush_windows(env);
  240. next_instruction(env);
  241. break;
  242. case TT_TRAP + 0x20: /* getcc */
  243. env->gregs[1] = do_getcc(env);
  244. next_instruction(env);
  245. break;
  246. case TT_TRAP + 0x21: /* setcc */
  247. do_setcc(env, env->gregs[1]);
  248. next_instruction(env);
  249. break;
  250. case TT_TRAP + 0x22: /* getpsr */
  251. env->gregs[1] = do_getpsr(env);
  252. next_instruction(env);
  253. break;
  254. #ifdef TARGET_SPARC64
  255. case TT_TRAP + 0x6e:
  256. flush_windows(env);
  257. sparc64_get_context(env);
  258. break;
  259. case TT_TRAP + 0x6f:
  260. flush_windows(env);
  261. sparc64_set_context(env);
  262. break;
  263. #endif
  264. case TARGET_TT_SPILL: /* window overflow */
  265. save_window(env);
  266. break;
  267. case TARGET_TT_FILL: /* window underflow */
  268. restore_window(env);
  269. break;
  270. case TT_FP_EXCP:
  271. {
  272. int code = TARGET_FPE_FLTUNK;
  273. target_ulong fsr = env->fsr;
  274. if ((fsr & FSR_FTT_MASK) == FSR_FTT_IEEE_EXCP) {
  275. if (fsr & FSR_NVC) {
  276. code = TARGET_FPE_FLTINV;
  277. } else if (fsr & FSR_OFC) {
  278. code = TARGET_FPE_FLTOVF;
  279. } else if (fsr & FSR_UFC) {
  280. code = TARGET_FPE_FLTUND;
  281. } else if (fsr & FSR_DZC) {
  282. code = TARGET_FPE_FLTDIV;
  283. } else if (fsr & FSR_NXC) {
  284. code = TARGET_FPE_FLTRES;
  285. }
  286. }
  287. force_sig_fault(TARGET_SIGFPE, code, env->pc);
  288. }
  289. break;
  290. case EXCP_INTERRUPT:
  291. /* just indicate that signals should be handled asap */
  292. break;
  293. case TT_ILL_INSN:
  294. force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc);
  295. break;
  296. case TT_PRIV_INSN:
  297. force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc);
  298. break;
  299. case TT_TOVF:
  300. force_sig_fault(TARGET_SIGEMT, TARGET_EMT_TAGOVF, env->pc);
  301. break;
  302. #ifdef TARGET_SPARC64
  303. case TT_PRIV_ACT:
  304. /* Note do_privact defers to do_privop. */
  305. force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc);
  306. break;
  307. #else
  308. case TT_NCP_INSN:
  309. force_sig_fault(TARGET_SIGILL, TARGET_ILL_COPROC, env->pc);
  310. break;
  311. case TT_UNIMP_FLUSH:
  312. next_instruction(env);
  313. break;
  314. #endif
  315. case EXCP_ATOMIC:
  316. cpu_exec_step_atomic(cs);
  317. break;
  318. default:
  319. /*
  320. * Most software trap numbers vector to BAD_TRAP.
  321. * Handle anything not explicitly matched above.
  322. */
  323. if (trapnr >= TT_TRAP && trapnr <= TT_TRAP + 0x7f) {
  324. force_sig_fault(TARGET_SIGILL, ILL_ILLTRP, env->pc);
  325. break;
  326. }
  327. fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
  328. cpu_dump_state(cs, stderr, 0);
  329. exit(EXIT_FAILURE);
  330. }
  331. process_pending_signals (env);
  332. }
  333. }
  334. void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
  335. {
  336. int i;
  337. env->pc = regs->pc;
  338. env->npc = regs->npc;
  339. env->y = regs->y;
  340. for(i = 0; i < 8; i++)
  341. env->gregs[i] = regs->u_regs[i];
  342. for(i = 0; i < 8; i++)
  343. env->regwptr[i] = regs->u_regs[i + 8];
  344. }