2
0

aspeed_intc.h 1.4 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162
  1. /*
  2. * ASPEED INTC Controller
  3. *
  4. * Copyright (C) 2024 ASPEED Technology Inc.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0-or-later
  7. */
  8. #ifndef ASPEED_INTC_H
  9. #define ASPEED_INTC_H
  10. #include "hw/sysbus.h"
  11. #include "qom/object.h"
  12. #include "hw/or-irq.h"
  13. #define TYPE_ASPEED_INTC "aspeed.intc"
  14. #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
  15. #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
  16. OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
  17. #define ASPEED_INTC_MAX_INPINS 10
  18. #define ASPEED_INTC_MAX_OUTPINS 19
  19. typedef struct AspeedINTCIRQ {
  20. int inpin_idx;
  21. int outpin_idx;
  22. int num_outpins;
  23. uint32_t enable_reg;
  24. uint32_t status_reg;
  25. } AspeedINTCIRQ;
  26. struct AspeedINTCState {
  27. /*< private >*/
  28. SysBusDevice parent_obj;
  29. /*< public >*/
  30. MemoryRegion iomem;
  31. MemoryRegion iomem_container;
  32. uint32_t *regs;
  33. OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
  34. qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
  35. uint32_t enable[ASPEED_INTC_MAX_INPINS];
  36. uint32_t mask[ASPEED_INTC_MAX_INPINS];
  37. uint32_t pending[ASPEED_INTC_MAX_INPINS];
  38. };
  39. struct AspeedINTCClass {
  40. SysBusDeviceClass parent_class;
  41. uint32_t num_lines;
  42. uint32_t num_inpins;
  43. uint32_t num_outpins;
  44. uint64_t mem_size;
  45. uint64_t nr_regs;
  46. uint64_t reg_offset;
  47. const MemoryRegionOps *reg_ops;
  48. const AspeedINTCIRQ *irq_table;
  49. int irq_table_count;
  50. };
  51. #endif /* ASPEED_INTC_H */