allwinner-r40.h 4.2 KB

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  1. /*
  2. * Allwinner R40/A40i/T3 System on Chip emulation
  3. *
  4. * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
  5. *
  6. * This program is free software: you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation, either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef HW_ARM_ALLWINNER_R40_H
  20. #define HW_ARM_ALLWINNER_R40_H
  21. #include "qom/object.h"
  22. #include "hw/timer/allwinner-a10-pit.h"
  23. #include "hw/ide/ahci-sysbus.h"
  24. #include "hw/intc/arm_gic.h"
  25. #include "hw/sd/allwinner-sdhost.h"
  26. #include "hw/misc/allwinner-r40-ccu.h"
  27. #include "hw/misc/allwinner-r40-dramc.h"
  28. #include "hw/misc/allwinner-sramc.h"
  29. #include "hw/i2c/allwinner-i2c.h"
  30. #include "hw/net/allwinner_emac.h"
  31. #include "hw/net/allwinner-sun8i-emac.h"
  32. #include "hw/usb/hcd-ohci.h"
  33. #include "hw/usb/hcd-ehci.h"
  34. #include "hw/watchdog/allwinner-wdt.h"
  35. #include "target/arm/cpu.h"
  36. #include "system/block-backend.h"
  37. enum {
  38. AW_R40_DEV_SRAM_A1,
  39. AW_R40_DEV_SRAM_A2,
  40. AW_R40_DEV_SRAM_A3,
  41. AW_R40_DEV_SRAM_A4,
  42. AW_R40_DEV_SRAMC,
  43. AW_R40_DEV_EMAC,
  44. AW_R40_DEV_MMC0,
  45. AW_R40_DEV_MMC1,
  46. AW_R40_DEV_MMC2,
  47. AW_R40_DEV_MMC3,
  48. AW_R40_DEV_AHCI,
  49. AW_R40_DEV_EHCI1,
  50. AW_R40_DEV_OHCI1,
  51. AW_R40_DEV_EHCI2,
  52. AW_R40_DEV_OHCI2,
  53. AW_R40_DEV_CCU,
  54. AW_R40_DEV_PIT,
  55. AW_R40_DEV_WDT,
  56. AW_R40_DEV_UART0,
  57. AW_R40_DEV_UART1,
  58. AW_R40_DEV_UART2,
  59. AW_R40_DEV_UART3,
  60. AW_R40_DEV_UART4,
  61. AW_R40_DEV_UART5,
  62. AW_R40_DEV_UART6,
  63. AW_R40_DEV_UART7,
  64. AW_R40_DEV_TWI0,
  65. AW_R40_DEV_GMAC,
  66. AW_R40_DEV_GIC_DIST,
  67. AW_R40_DEV_GIC_CPU,
  68. AW_R40_DEV_GIC_HYP,
  69. AW_R40_DEV_GIC_VCPU,
  70. AW_R40_DEV_SDRAM,
  71. AW_R40_DEV_DRAMCOM,
  72. AW_R40_DEV_DRAMCTL,
  73. AW_R40_DEV_DRAMPHY,
  74. };
  75. #define AW_R40_NUM_CPUS (4)
  76. /**
  77. * Allwinner R40 object model
  78. * @{
  79. */
  80. /** Object type for the Allwinner R40 SoC */
  81. #define TYPE_AW_R40 "allwinner-r40"
  82. /** Convert input object to Allwinner R40 state object */
  83. OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
  84. /** @} */
  85. /**
  86. * Allwinner R40 object
  87. *
  88. * This struct contains the state of all the devices
  89. * which are currently emulated by the R40 SoC code.
  90. */
  91. #define AW_R40_NUM_MMCS 4
  92. #define AW_R40_NUM_USB 2
  93. #define AW_R40_NUM_UARTS 8
  94. struct AwR40State {
  95. /*< private >*/
  96. DeviceState parent_obj;
  97. /*< public >*/
  98. /** Physical base address for start of RAM */
  99. hwaddr ram_addr;
  100. /** Total RAM size in megabytes */
  101. uint32_t ram_size;
  102. ARMCPU cpus[AW_R40_NUM_CPUS];
  103. const hwaddr *memmap;
  104. AwSRAMCState sramc;
  105. AwA10PITState timer;
  106. AwWdtState wdt;
  107. AllwinnerAHCIState sata;
  108. AwSdHostState mmc[AW_R40_NUM_MMCS];
  109. EHCISysBusState ehci[AW_R40_NUM_USB];
  110. OHCISysBusState ohci[AW_R40_NUM_USB];
  111. AwR40ClockCtlState ccu;
  112. AwR40DramCtlState dramc;
  113. AWI2CState i2c0;
  114. AwEmacState emac;
  115. AwSun8iEmacState gmac;
  116. GICState gic;
  117. MemoryRegion sram_a1;
  118. MemoryRegion sram_a2;
  119. MemoryRegion sram_a3;
  120. MemoryRegion sram_a4;
  121. };
  122. /**
  123. * Emulate Boot ROM firmware setup functionality.
  124. *
  125. * A real Allwinner R40 SoC contains a Boot ROM
  126. * which is the first code that runs right after
  127. * the SoC is powered on. The Boot ROM is responsible
  128. * for loading user code (e.g. a bootloader) from any
  129. * of the supported external devices and writing the
  130. * downloaded code to internal SRAM. After loading the SoC
  131. * begins executing the code written to SRAM.
  132. *
  133. * This function emulates the Boot ROM by copying 32 KiB
  134. * of data from the given block device and writes it to
  135. * the start of the first internal SRAM memory.
  136. *
  137. * @s: Allwinner R40 state object pointer
  138. * @blk: Block backend device object pointer
  139. * @unit: the mmc control's unit
  140. */
  141. bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit);
  142. #endif /* HW_ARM_ALLWINNER_R40_H */