memattrs.h 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990
  1. /*
  2. * Memory transaction attributes
  3. *
  4. * Copyright (c) 2015 Linaro Limited.
  5. *
  6. * Authors:
  7. * Peter Maydell <peter.maydell@linaro.org>
  8. *
  9. * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10. * See the COPYING file in the top-level directory.
  11. *
  12. */
  13. #ifndef MEMATTRS_H
  14. #define MEMATTRS_H
  15. /* Every memory transaction has associated with it a set of
  16. * attributes. Some of these are generic (such as the ID of
  17. * the bus master); some are specific to a particular kind of
  18. * bus (such as the ARM Secure/NonSecure bit). We define them
  19. * all as non-overlapping bitfields in a single struct to avoid
  20. * confusion if different parts of QEMU used the same bit for
  21. * different semantics.
  22. */
  23. typedef struct MemTxAttrs {
  24. /*
  25. * ARM/AMBA: TrustZone Secure access
  26. * x86: System Management Mode access
  27. */
  28. unsigned int secure:1;
  29. /*
  30. * ARM: ArmSecuritySpace. This partially overlaps secure, but it is
  31. * easier to have both fields to assist code that does not understand
  32. * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash).
  33. */
  34. unsigned int space:2;
  35. /* Memory access is usermode (unprivileged) */
  36. unsigned int user:1;
  37. /*
  38. * Bus interconnect and peripherals can access anything (memories,
  39. * devices) by default. By setting the 'memory' bit, bus transaction
  40. * are restricted to "normal" memories (per the AMBA documentation)
  41. * versus devices. Access to devices will be logged and rejected
  42. * (see MEMTX_ACCESS_ERROR).
  43. */
  44. unsigned int memory:1;
  45. /* Debug access that can even write to ROM. */
  46. unsigned int debug:1;
  47. /* Requester ID (for MSI for example) */
  48. unsigned int requester_id:16;
  49. /*
  50. * PID (PCI PASID) support: Limited to 8 bits process identifier.
  51. */
  52. unsigned int pid:8;
  53. /*
  54. * Bus masters which don't specify any attributes will get this
  55. * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
  56. * distinguish "all attributes deliberately clear" from
  57. * "didn't specify" if necessary. "debug" can be set alongside
  58. * "unspecified".
  59. */
  60. bool unspecified;
  61. uint8_t _reserved1;
  62. uint16_t _reserved2;
  63. } MemTxAttrs;
  64. QEMU_BUILD_BUG_ON(sizeof(MemTxAttrs) > 8);
  65. /* Bus masters which don't specify any attributes will get this,
  66. * which has all attribute bits clear except the topmost one
  67. * (so that we can distinguish "all attributes deliberately clear"
  68. * from "didn't specify" if necessary).
  69. */
  70. #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = true })
  71. /* New-style MMIO accessors can indicate that the transaction failed.
  72. * A zero (MEMTX_OK) response means success; anything else is a failure
  73. * of some kind. The memory subsystem will bitwise-OR together results
  74. * if it is synthesizing an operation from multiple smaller accesses.
  75. */
  76. #define MEMTX_OK 0
  77. #define MEMTX_ERROR (1U << 0) /* device returned an error */
  78. #define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */
  79. #define MEMTX_ACCESS_ERROR (1U << 2) /* access denied */
  80. typedef uint32_t MemTxResult;
  81. #endif