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cpu-interrupt.h 2.1 KB

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  1. /*
  2. * Flags for use with cpu_interrupt()
  3. *
  4. * Copyright (c) 2003 Fabrice Bellard
  5. * SPDX-License-Identifier: LGPL-2.1-or-later
  6. */
  7. #ifndef CPU_INTERRUPT_H
  8. #define CPU_INTERRUPT_H
  9. /*
  10. * The numbers assigned here are non-sequential in order to preserve binary
  11. * compatibility with the vmstate dump. Bit 0 (0x0001) was previously used
  12. * for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump.
  13. */
  14. /*
  15. * External hardware interrupt pending.
  16. * This is typically used for interrupts from devices.
  17. */
  18. #define CPU_INTERRUPT_HARD 0x0002
  19. /*
  20. * Exit the current TB. This is typically used when some system-level device
  21. * makes some change to the memory mapping. E.g. the a20 line change.
  22. */
  23. #define CPU_INTERRUPT_EXITTB 0x0004
  24. /* Halt the CPU. */
  25. #define CPU_INTERRUPT_HALT 0x0020
  26. /* Debug event pending. */
  27. #define CPU_INTERRUPT_DEBUG 0x0080
  28. /* Reset signal. */
  29. #define CPU_INTERRUPT_RESET 0x0400
  30. /*
  31. * Several target-specific external hardware interrupts. Each target/cpu.h
  32. * should define proper names based on these defines.
  33. */
  34. #define CPU_INTERRUPT_TGT_EXT_0 0x0008
  35. #define CPU_INTERRUPT_TGT_EXT_1 0x0010
  36. #define CPU_INTERRUPT_TGT_EXT_2 0x0040
  37. #define CPU_INTERRUPT_TGT_EXT_3 0x0200
  38. #define CPU_INTERRUPT_TGT_EXT_4 0x1000
  39. /*
  40. * Several target-specific internal interrupts. These differ from the
  41. * preceding target-specific interrupts in that they are intended to
  42. * originate from within the cpu itself, typically in response to some
  43. * instruction being executed. These, therefore, are not masked while
  44. * single-stepping within the debugger.
  45. */
  46. #define CPU_INTERRUPT_TGT_INT_0 0x0100
  47. #define CPU_INTERRUPT_TGT_INT_1 0x0800
  48. #define CPU_INTERRUPT_TGT_INT_2 0x2000
  49. /* First unused bit: 0x4000. */
  50. /* The set of all bits that should be masked when single-stepping. */
  51. #define CPU_INTERRUPT_SSTEP_MASK \
  52. (CPU_INTERRUPT_HARD \
  53. | CPU_INTERRUPT_TGT_EXT_0 \
  54. | CPU_INTERRUPT_TGT_EXT_1 \
  55. | CPU_INTERRUPT_TGT_EXT_2 \
  56. | CPU_INTERRUPT_TGT_EXT_3 \
  57. | CPU_INTERRUPT_TGT_EXT_4)
  58. #endif /* CPU_INTERRUPT_H */