cpu-common.h 9.4 KB

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  1. /*
  2. * CPU interfaces that are target independent.
  3. *
  4. * Copyright (c) 2003 Fabrice Bellard
  5. *
  6. * SPDX-License-Identifier: LGPL-2.1+
  7. */
  8. #ifndef CPU_COMMON_H
  9. #define CPU_COMMON_H
  10. #include "exec/vaddr.h"
  11. #ifndef CONFIG_USER_ONLY
  12. #include "exec/hwaddr.h"
  13. #endif
  14. #include "hw/core/cpu.h"
  15. #include "tcg/debug-assert.h"
  16. #include "exec/page-protection.h"
  17. #define EXCP_INTERRUPT 0x10000 /* async interruption */
  18. #define EXCP_HLT 0x10001 /* hlt instruction reached */
  19. #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
  20. #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
  21. #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
  22. #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
  23. void cpu_exec_init_all(void);
  24. void cpu_exec_step_atomic(CPUState *cpu);
  25. #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size())
  26. /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
  27. extern QemuMutex qemu_cpu_list_lock;
  28. void qemu_init_cpu_list(void);
  29. void cpu_list_lock(void);
  30. void cpu_list_unlock(void);
  31. unsigned int cpu_list_generation_id_get(void);
  32. int cpu_get_free_index(void);
  33. void tcg_iommu_init_notifier_list(CPUState *cpu);
  34. void tcg_iommu_free_notifier_list(CPUState *cpu);
  35. #if !defined(CONFIG_USER_ONLY)
  36. enum device_endian {
  37. DEVICE_NATIVE_ENDIAN,
  38. DEVICE_BIG_ENDIAN,
  39. DEVICE_LITTLE_ENDIAN,
  40. };
  41. #if HOST_BIG_ENDIAN
  42. #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
  43. #else
  44. #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
  45. #endif
  46. /* address in the RAM (different from a physical address) */
  47. #if defined(CONFIG_XEN_BACKEND)
  48. typedef uint64_t ram_addr_t;
  49. # define RAM_ADDR_MAX UINT64_MAX
  50. # define RAM_ADDR_FMT "%" PRIx64
  51. #else
  52. typedef uintptr_t ram_addr_t;
  53. # define RAM_ADDR_MAX UINTPTR_MAX
  54. # define RAM_ADDR_FMT "%" PRIxPTR
  55. #endif
  56. /* memory API */
  57. void qemu_ram_remap(ram_addr_t addr);
  58. /* This should not be used by devices. */
  59. ram_addr_t qemu_ram_addr_from_host(void *ptr);
  60. ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
  61. RAMBlock *qemu_ram_block_by_name(const char *name);
  62. /*
  63. * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock.
  64. *
  65. * @ptr: The host pointer to translate.
  66. * @round_offset: Whether to round the result offset down to a target page
  67. * @offset: Will be set to the offset within the returned RAMBlock.
  68. *
  69. * Returns: RAMBlock (or NULL if not found)
  70. *
  71. * By the time this function returns, the returned pointer is not protected
  72. * by RCU anymore. If the caller is not within an RCU critical section and
  73. * does not hold the BQL, it must have other means of protecting the
  74. * pointer, such as a reference to the memory region that owns the RAMBlock.
  75. */
  76. RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
  77. ram_addr_t *offset);
  78. ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
  79. void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
  80. void qemu_ram_unset_idstr(RAMBlock *block);
  81. const char *qemu_ram_get_idstr(RAMBlock *rb);
  82. void *qemu_ram_get_host_addr(RAMBlock *rb);
  83. ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
  84. ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
  85. ram_addr_t qemu_ram_get_max_length(RAMBlock *rb);
  86. bool qemu_ram_is_shared(RAMBlock *rb);
  87. bool qemu_ram_is_noreserve(RAMBlock *rb);
  88. bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
  89. void qemu_ram_set_uf_zeroable(RAMBlock *rb);
  90. bool qemu_ram_is_migratable(RAMBlock *rb);
  91. void qemu_ram_set_migratable(RAMBlock *rb);
  92. void qemu_ram_unset_migratable(RAMBlock *rb);
  93. bool qemu_ram_is_named_file(RAMBlock *rb);
  94. int qemu_ram_get_fd(RAMBlock *rb);
  95. size_t qemu_ram_pagesize(RAMBlock *block);
  96. size_t qemu_ram_pagesize_largest(void);
  97. /**
  98. * cpu_address_space_init:
  99. * @cpu: CPU to add this address space to
  100. * @asidx: integer index of this address space
  101. * @prefix: prefix to be used as name of address space
  102. * @mr: the root memory region of address space
  103. *
  104. * Add the specified address space to the CPU's cpu_ases list.
  105. * The address space added with @asidx 0 is the one used for the
  106. * convenience pointer cpu->as.
  107. * The target-specific code which registers ASes is responsible
  108. * for defining what semantics address space 0, 1, 2, etc have.
  109. *
  110. * Before the first call to this function, the caller must set
  111. * cpu->num_ases to the total number of address spaces it needs
  112. * to support.
  113. *
  114. * Note that with KVM only one address space is supported.
  115. */
  116. void cpu_address_space_init(CPUState *cpu, int asidx,
  117. const char *prefix, MemoryRegion *mr);
  118. /**
  119. * cpu_address_space_destroy:
  120. * @cpu: CPU for which address space needs to be destroyed
  121. * @asidx: integer index of this address space
  122. *
  123. * Note that with KVM only one address space is supported.
  124. */
  125. void cpu_address_space_destroy(CPUState *cpu, int asidx);
  126. void cpu_physical_memory_rw(hwaddr addr, void *buf,
  127. hwaddr len, bool is_write);
  128. static inline void cpu_physical_memory_read(hwaddr addr,
  129. void *buf, hwaddr len)
  130. {
  131. cpu_physical_memory_rw(addr, buf, len, false);
  132. }
  133. static inline void cpu_physical_memory_write(hwaddr addr,
  134. const void *buf, hwaddr len)
  135. {
  136. cpu_physical_memory_rw(addr, (void *)buf, len, true);
  137. }
  138. void *cpu_physical_memory_map(hwaddr addr,
  139. hwaddr *plen,
  140. bool is_write);
  141. void cpu_physical_memory_unmap(void *buffer, hwaddr len,
  142. bool is_write, hwaddr access_len);
  143. bool cpu_physical_memory_is_io(hwaddr phys_addr);
  144. /* Coalesced MMIO regions are areas where write operations can be reordered.
  145. * This usually implies that write operations are side-effect free. This allows
  146. * batching which can make a major impact on performance when using
  147. * virtualization.
  148. */
  149. void qemu_flush_coalesced_mmio_buffer(void);
  150. void cpu_flush_icache_range(hwaddr start, hwaddr len);
  151. typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
  152. int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
  153. int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
  154. int ram_block_discard_guest_memfd_range(RAMBlock *rb, uint64_t start,
  155. size_t length);
  156. #endif
  157. /* Returns: 0 on success, -1 on error */
  158. int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
  159. void *ptr, size_t len, bool is_write);
  160. /* vl.c */
  161. void list_cpus(void);
  162. #ifdef CONFIG_TCG
  163. #include "qemu/atomic.h"
  164. /**
  165. * cpu_unwind_state_data:
  166. * @cpu: the cpu context
  167. * @host_pc: the host pc within the translation
  168. * @data: output data
  169. *
  170. * Attempt to load the the unwind state for a host pc occurring in
  171. * translated code. If @host_pc is not in translated code, the
  172. * function returns false; otherwise @data is loaded.
  173. * This is the same unwind info as given to restore_state_to_opc.
  174. */
  175. bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data);
  176. /**
  177. * cpu_restore_state:
  178. * @cpu: the cpu context
  179. * @host_pc: the host pc within the translation
  180. * @return: true if state was restored, false otherwise
  181. *
  182. * Attempt to restore the state for a fault occurring in translated
  183. * code. If @host_pc is not in translated code no state is
  184. * restored and the function returns false.
  185. */
  186. bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc);
  187. /**
  188. * cpu_loop_exit_requested:
  189. * @cpu: The CPU state to be tested
  190. *
  191. * Indicate if somebody asked for a return of the CPU to the main loop
  192. * (e.g., via cpu_exit() or cpu_interrupt()).
  193. *
  194. * This is helpful for architectures that support interruptible
  195. * instructions. After writing back all state to registers/memory, this
  196. * call can be used to check if it makes sense to return to the main loop
  197. * or to continue executing the interruptible instruction.
  198. */
  199. static inline bool cpu_loop_exit_requested(CPUState *cpu)
  200. {
  201. return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0;
  202. }
  203. G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu);
  204. G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
  205. #endif /* CONFIG_TCG */
  206. G_NORETURN void cpu_loop_exit(CPUState *cpu);
  207. G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
  208. /* accel/tcg/cpu-exec.c */
  209. int cpu_exec(CPUState *cpu);
  210. /**
  211. * env_archcpu(env)
  212. * @env: The architecture environment
  213. *
  214. * Return the ArchCPU associated with the environment.
  215. */
  216. static inline ArchCPU *env_archcpu(CPUArchState *env)
  217. {
  218. return (void *)env - sizeof(CPUState);
  219. }
  220. /**
  221. * env_cpu_const(env)
  222. * @env: The architecture environment
  223. *
  224. * Return the CPUState associated with the environment.
  225. */
  226. static inline const CPUState *env_cpu_const(const CPUArchState *env)
  227. {
  228. return (void *)env - sizeof(CPUState);
  229. }
  230. /**
  231. * env_cpu(env)
  232. * @env: The architecture environment
  233. *
  234. * Return the CPUState associated with the environment.
  235. */
  236. static inline CPUState *env_cpu(CPUArchState *env)
  237. {
  238. return (CPUState *)env_cpu_const(env);
  239. }
  240. #ifndef CONFIG_USER_ONLY
  241. /**
  242. * cpu_mmu_index:
  243. * @env: The cpu environment
  244. * @ifetch: True for code access, false for data access.
  245. *
  246. * Return the core mmu index for the current translation regime.
  247. * This function is used by generic TCG code paths.
  248. *
  249. * The user-only version of this function is inline in cpu-all.h,
  250. * where it always returns MMU_USER_IDX.
  251. */
  252. static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
  253. {
  254. int ret = cs->cc->mmu_index(cs, ifetch);
  255. tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES);
  256. return ret;
  257. }
  258. #endif /* !CONFIG_USER_ONLY */
  259. #endif /* CPU_COMMON_H */