virt-acpi-build.c 30 KB

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  1. /*
  2. * Support for generating ACPI tables and passing them to Guests
  3. *
  4. * RISC-V virt ACPI generation
  5. *
  6. * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
  7. * Copyright (C) 2006 Fabrice Bellard
  8. * Copyright (C) 2013 Red Hat Inc
  9. * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
  10. * Copyright (C) 2021-2023 Ventana Micro Systems Inc
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. * You should have received a copy of the GNU General Public License along
  21. * with this program; if not, see <http://www.gnu.org/licenses/>.
  22. */
  23. #include "qemu/osdep.h"
  24. #include "hw/acpi/acpi-defs.h"
  25. #include "hw/acpi/acpi.h"
  26. #include "hw/acpi/aml-build.h"
  27. #include "hw/acpi/pci.h"
  28. #include "hw/acpi/utils.h"
  29. #include "hw/intc/riscv_aclint.h"
  30. #include "hw/nvram/fw_cfg_acpi.h"
  31. #include "hw/pci-host/gpex.h"
  32. #include "hw/riscv/virt.h"
  33. #include "hw/riscv/numa.h"
  34. #include "hw/virtio/virtio-acpi.h"
  35. #include "migration/vmstate.h"
  36. #include "qapi/error.h"
  37. #include "qemu/error-report.h"
  38. #include "system/reset.h"
  39. #define ACPI_BUILD_TABLE_SIZE 0x20000
  40. #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
  41. typedef struct AcpiBuildState {
  42. /* Copy of table in RAM (for patching) */
  43. MemoryRegion *table_mr;
  44. MemoryRegion *rsdp_mr;
  45. MemoryRegion *linker_mr;
  46. /* Is table patched? */
  47. bool patched;
  48. } AcpiBuildState;
  49. static void acpi_align_size(GArray *blob, unsigned align)
  50. {
  51. /*
  52. * Align size to multiple of given size. This reduces the chance
  53. * we need to change size in the future (breaking cross version migration).
  54. */
  55. g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
  56. }
  57. static void riscv_acpi_madt_add_rintc(uint32_t uid,
  58. const CPUArchIdList *arch_ids,
  59. GArray *entry,
  60. RISCVVirtState *s)
  61. {
  62. uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
  63. uint64_t hart_id = arch_ids->cpus[uid].arch_id;
  64. uint32_t imsic_size, local_cpu_id, socket_id;
  65. uint64_t imsic_socket_addr, imsic_addr;
  66. MachineState *ms = MACHINE(s);
  67. socket_id = arch_ids->cpus[uid].props.node_id;
  68. local_cpu_id = (arch_ids->cpus[uid].arch_id -
  69. riscv_socket_first_hartid(ms, socket_id)) %
  70. riscv_socket_hart_count(ms, socket_id);
  71. imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
  72. (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
  73. imsic_size = IMSIC_HART_SIZE(guest_index_bits);
  74. imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size;
  75. build_append_int_noprefix(entry, 0x18, 1); /* Type */
  76. build_append_int_noprefix(entry, 36, 1); /* Length */
  77. build_append_int_noprefix(entry, 1, 1); /* Version */
  78. build_append_int_noprefix(entry, 0, 1); /* Reserved */
  79. build_append_int_noprefix(entry, 0x1, 4); /* Flags */
  80. build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */
  81. build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */
  82. /* External Interrupt Controller ID */
  83. if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
  84. build_append_int_noprefix(entry,
  85. ACPI_BUILD_INTC_ID(
  86. arch_ids->cpus[uid].props.node_id,
  87. local_cpu_id),
  88. 4);
  89. } else if (s->aia_type == VIRT_AIA_TYPE_NONE) {
  90. build_append_int_noprefix(entry,
  91. ACPI_BUILD_INTC_ID(
  92. arch_ids->cpus[uid].props.node_id,
  93. 2 * local_cpu_id + 1),
  94. 4);
  95. } else {
  96. build_append_int_noprefix(entry, 0, 4);
  97. }
  98. if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
  99. /* IMSIC Base address */
  100. build_append_int_noprefix(entry, imsic_addr, 8);
  101. /* IMSIC Size */
  102. build_append_int_noprefix(entry, imsic_size, 4);
  103. } else {
  104. build_append_int_noprefix(entry, 0, 8);
  105. build_append_int_noprefix(entry, 0, 4);
  106. }
  107. }
  108. static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
  109. {
  110. MachineClass *mc = MACHINE_GET_CLASS(s);
  111. MachineState *ms = MACHINE(s);
  112. const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
  113. for (int i = 0; i < arch_ids->len; i++) {
  114. Aml *dev;
  115. GArray *madt_buf = g_array_new(0, 1, 1);
  116. dev = aml_device("C%.03X", i);
  117. aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
  118. aml_append(dev, aml_name_decl("_UID",
  119. aml_int(arch_ids->cpus[i].arch_id)));
  120. /* build _MAT object */
  121. riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s);
  122. aml_append(dev, aml_name_decl("_MAT",
  123. aml_buffer(madt_buf->len,
  124. (uint8_t *)madt_buf->data)));
  125. g_array_free(madt_buf, true);
  126. aml_append(scope, dev);
  127. }
  128. }
  129. static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,
  130. uint64_t mmio_base, uint64_t mmio_size,
  131. const char *hid)
  132. {
  133. uint64_t plic_aplic_addr;
  134. uint32_t gsi_base;
  135. uint8_t socket;
  136. for (socket = 0; socket < socket_count; socket++) {
  137. plic_aplic_addr = mmio_base + mmio_size * socket;
  138. gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
  139. Aml *dev = aml_device("IC%.02X", socket);
  140. aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid)));
  141. aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
  142. aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
  143. Aml *crs = aml_resource_template();
  144. aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size,
  145. AML_READ_WRITE));
  146. aml_append(dev, aml_name_decl("_CRS", crs));
  147. aml_append(scope, dev);
  148. }
  149. }
  150. static void
  151. acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
  152. uint32_t uart_irq)
  153. {
  154. Aml *dev = aml_device("COM0");
  155. aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0003")));
  156. aml_append(dev, aml_name_decl("_UID", aml_int(0)));
  157. Aml *crs = aml_resource_template();
  158. aml_append(crs, aml_memory32_fixed(uart_memmap->base,
  159. uart_memmap->size, AML_READ_WRITE));
  160. aml_append(crs,
  161. aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  162. AML_EXCLUSIVE, &uart_irq, 1));
  163. aml_append(dev, aml_name_decl("_CRS", crs));
  164. Aml *pkg = aml_package(2);
  165. aml_append(pkg, aml_string("clock-frequency"));
  166. aml_append(pkg, aml_int(3686400));
  167. Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
  168. Aml *pkg1 = aml_package(1);
  169. aml_append(pkg1, pkg);
  170. Aml *package = aml_package(2);
  171. aml_append(package, UUID);
  172. aml_append(package, pkg1);
  173. aml_append(dev, aml_name_decl("_DSD", package));
  174. aml_append(scope, dev);
  175. }
  176. /*
  177. * Serial Port Console Redirection Table (SPCR)
  178. * Rev: 1.10
  179. */
  180. static void
  181. spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
  182. {
  183. const char name[] = ".";
  184. AcpiSpcrData serial = {
  185. .interface_type = 0x12, /* 16550 compatible */
  186. .base_addr.id = AML_AS_SYSTEM_MEMORY,
  187. .base_addr.width = 32,
  188. .base_addr.offset = 0,
  189. .base_addr.size = 1,
  190. .base_addr.addr = s->memmap[VIRT_UART0].base,
  191. .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */
  192. .pc_interrupt = 0,
  193. .interrupt = UART0_IRQ,
  194. .baud_rate = 7, /* 15200 */
  195. .parity = 0,
  196. .stop_bits = 1,
  197. .flow_control = 0,
  198. .terminal_type = 3, /* ANSI */
  199. .language = 0, /* Language */
  200. .pci_device_id = 0xffff, /* not a PCI device*/
  201. .pci_vendor_id = 0xffff, /* not a PCI device*/
  202. .pci_bus = 0,
  203. .pci_device = 0,
  204. .pci_function = 0,
  205. .pci_flags = 0,
  206. .pci_segment = 0,
  207. .uart_clk_freq = 0,
  208. .precise_baudrate = 0,
  209. .namespace_string_length = sizeof(name),
  210. .namespace_string_offset = 88,
  211. };
  212. build_spcr(table_data, linker, &serial, 4, s->oem_id, s->oem_table_id,
  213. name);
  214. }
  215. /* RHCT Node[N] starts at offset 56 */
  216. #define RHCT_NODE_ARRAY_OFFSET 56
  217. /*
  218. * ACPI spec, Revision 6.5+
  219. * 5.2.36 RISC-V Hart Capabilities Table (RHCT)
  220. * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
  221. * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
  222. * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
  223. */
  224. static void build_rhct(GArray *table_data,
  225. BIOSLinker *linker,
  226. RISCVVirtState *s)
  227. {
  228. MachineClass *mc = MACHINE_GET_CLASS(s);
  229. MachineState *ms = MACHINE(s);
  230. const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
  231. size_t len, aligned_len;
  232. uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
  233. RISCVCPU *cpu = &s->soc[0].harts[0];
  234. uint32_t mmu_offset = 0;
  235. uint8_t satp_mode_max;
  236. g_autofree char *isa = NULL;
  237. AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
  238. .oem_table_id = s->oem_table_id };
  239. acpi_table_begin(&table, table_data);
  240. build_append_int_noprefix(table_data, 0x0, 4); /* Reserved */
  241. /* Time Base Frequency */
  242. build_append_int_noprefix(table_data,
  243. RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8);
  244. /* ISA + N hart info */
  245. num_rhct_nodes = 1 + ms->smp.cpus;
  246. if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
  247. num_rhct_nodes++;
  248. }
  249. if (cpu->cfg.satp_mode.supported != 0) {
  250. num_rhct_nodes++;
  251. }
  252. /* Number of RHCT nodes*/
  253. build_append_int_noprefix(table_data, num_rhct_nodes, 4);
  254. /* Offset to the RHCT node array */
  255. build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4);
  256. /* ISA String Node */
  257. isa_offset = table_data->len - table.table_offset;
  258. build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
  259. isa = riscv_isa_string(cpu);
  260. len = 8 + strlen(isa) + 1;
  261. aligned_len = (len % 2) ? (len + 1) : len;
  262. build_append_int_noprefix(table_data, aligned_len, 2); /* Length */
  263. build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
  264. /* ISA string length including NUL */
  265. build_append_int_noprefix(table_data, strlen(isa) + 1, 2);
  266. g_array_append_vals(table_data, isa, strlen(isa) + 1); /* ISA string */
  267. if (aligned_len != len) {
  268. build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
  269. }
  270. /* CMO node */
  271. if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
  272. cmo_offset = table_data->len - table.table_offset;
  273. build_append_int_noprefix(table_data, 1, 2); /* Type */
  274. build_append_int_noprefix(table_data, 10, 2); /* Length */
  275. build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
  276. build_append_int_noprefix(table_data, 0, 1); /* Reserved */
  277. /* CBOM block size */
  278. if (cpu->cfg.cbom_blocksize) {
  279. build_append_int_noprefix(table_data,
  280. __builtin_ctz(cpu->cfg.cbom_blocksize),
  281. 1);
  282. } else {
  283. build_append_int_noprefix(table_data, 0, 1);
  284. }
  285. /* CBOP block size */
  286. build_append_int_noprefix(table_data, 0, 1);
  287. /* CBOZ block size */
  288. if (cpu->cfg.cboz_blocksize) {
  289. build_append_int_noprefix(table_data,
  290. __builtin_ctz(cpu->cfg.cboz_blocksize),
  291. 1);
  292. } else {
  293. build_append_int_noprefix(table_data, 0, 1);
  294. }
  295. }
  296. /* MMU node structure */
  297. if (cpu->cfg.satp_mode.supported != 0) {
  298. satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
  299. mmu_offset = table_data->len - table.table_offset;
  300. build_append_int_noprefix(table_data, 2, 2); /* Type */
  301. build_append_int_noprefix(table_data, 8, 2); /* Length */
  302. build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
  303. build_append_int_noprefix(table_data, 0, 1); /* Reserved */
  304. /* MMU Type */
  305. if (satp_mode_max == VM_1_10_SV57) {
  306. build_append_int_noprefix(table_data, 2, 1); /* Sv57 */
  307. } else if (satp_mode_max == VM_1_10_SV48) {
  308. build_append_int_noprefix(table_data, 1, 1); /* Sv48 */
  309. } else if (satp_mode_max == VM_1_10_SV39) {
  310. build_append_int_noprefix(table_data, 0, 1); /* Sv39 */
  311. } else {
  312. assert(1);
  313. }
  314. }
  315. /* Hart Info Node */
  316. for (int i = 0; i < arch_ids->len; i++) {
  317. len = 16;
  318. int num_offsets = 1;
  319. build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */
  320. /* Length */
  321. if (cmo_offset) {
  322. len += 4;
  323. num_offsets++;
  324. }
  325. if (mmu_offset) {
  326. len += 4;
  327. num_offsets++;
  328. }
  329. build_append_int_noprefix(table_data, len, 2);
  330. build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
  331. /* Number of offsets */
  332. build_append_int_noprefix(table_data, num_offsets, 2);
  333. build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
  334. /* Offsets */
  335. build_append_int_noprefix(table_data, isa_offset, 4);
  336. if (cmo_offset) {
  337. build_append_int_noprefix(table_data, cmo_offset, 4);
  338. }
  339. if (mmu_offset) {
  340. build_append_int_noprefix(table_data, mmu_offset, 4);
  341. }
  342. }
  343. acpi_table_end(linker, &table);
  344. }
  345. /* FADT */
  346. static void build_fadt_rev6(GArray *table_data,
  347. BIOSLinker *linker,
  348. RISCVVirtState *s,
  349. unsigned dsdt_tbl_offset)
  350. {
  351. AcpiFadtData fadt = {
  352. .rev = 6,
  353. .minor_ver = 5,
  354. .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
  355. .xdsdt_tbl_offset = &dsdt_tbl_offset,
  356. };
  357. build_fadt(table_data, linker, &fadt, s->oem_id, s->oem_table_id);
  358. }
  359. /* DSDT */
  360. static void build_dsdt(GArray *table_data,
  361. BIOSLinker *linker,
  362. RISCVVirtState *s)
  363. {
  364. Aml *scope, *dsdt;
  365. MachineState *ms = MACHINE(s);
  366. uint8_t socket_count;
  367. const MemMapEntry *memmap = s->memmap;
  368. AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
  369. .oem_table_id = s->oem_table_id };
  370. acpi_table_begin(&table, table_data);
  371. dsdt = init_aml_allocator();
  372. /*
  373. * When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
  374. * While UEFI can use libfdt to disable the RTC device node in the DTB that
  375. * it passes to the OS, it cannot modify AML. Therefore, we won't generate
  376. * the RTC ACPI device at all when using UEFI.
  377. */
  378. scope = aml_scope("\\_SB");
  379. acpi_dsdt_add_cpus(scope, s);
  380. fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
  381. socket_count = riscv_socket_count(ms);
  382. if (s->aia_type == VIRT_AIA_TYPE_NONE) {
  383. acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base,
  384. memmap[VIRT_PLIC].size, "RSCV0001");
  385. } else {
  386. acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base,
  387. memmap[VIRT_APLIC_S].size, "RSCV0002");
  388. }
  389. acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
  390. if (socket_count == 1) {
  391. virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
  392. memmap[VIRT_VIRTIO].size,
  393. VIRTIO_IRQ, 0, VIRTIO_COUNT);
  394. acpi_dsdt_add_gpex_host(scope, PCIE_IRQ);
  395. } else if (socket_count == 2) {
  396. virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
  397. memmap[VIRT_VIRTIO].size,
  398. VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
  399. VIRTIO_COUNT);
  400. acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);
  401. } else {
  402. virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
  403. memmap[VIRT_VIRTIO].size,
  404. VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
  405. VIRTIO_COUNT);
  406. acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2);
  407. }
  408. aml_append(dsdt, scope);
  409. /* copy AML table into ACPI tables blob and patch header there */
  410. g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
  411. acpi_table_end(linker, &table);
  412. free_aml_allocator();
  413. }
  414. /*
  415. * ACPI spec, Revision 6.5+
  416. * 5.2.12 Multiple APIC Description Table (MADT)
  417. * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
  418. * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
  419. * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
  420. */
  421. static void build_madt(GArray *table_data,
  422. BIOSLinker *linker,
  423. RISCVVirtState *s)
  424. {
  425. MachineClass *mc = MACHINE_GET_CLASS(s);
  426. MachineState *ms = MACHINE(s);
  427. const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
  428. uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms));
  429. uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1);
  430. uint16_t imsic_max_hart_per_socket = 0;
  431. uint8_t hart_index_bits;
  432. uint64_t aplic_addr;
  433. uint32_t gsi_base;
  434. uint8_t socket;
  435. for (socket = 0; socket < riscv_socket_count(ms); socket++) {
  436. if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
  437. imsic_max_hart_per_socket = s->soc[socket].num_harts;
  438. }
  439. }
  440. hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket);
  441. AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
  442. .oem_table_id = s->oem_table_id };
  443. acpi_table_begin(&table, table_data);
  444. /* Local Interrupt Controller Address */
  445. build_append_int_noprefix(table_data, 0, 4);
  446. build_append_int_noprefix(table_data, 0, 4); /* MADT Flags */
  447. /* RISC-V Local INTC structures per HART */
  448. for (int i = 0; i < arch_ids->len; i++) {
  449. riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s);
  450. }
  451. /* IMSIC */
  452. if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
  453. /* IMSIC */
  454. build_append_int_noprefix(table_data, 0x19, 1); /* Type */
  455. build_append_int_noprefix(table_data, 16, 1); /* Length */
  456. build_append_int_noprefix(table_data, 1, 1); /* Version */
  457. build_append_int_noprefix(table_data, 0, 1); /* Reserved */
  458. build_append_int_noprefix(table_data, 0, 4); /* Flags */
  459. /* Number of supervisor mode Interrupt Identities */
  460. build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
  461. /* Number of guest mode Interrupt Identities */
  462. build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
  463. /* Guest Index Bits */
  464. build_append_int_noprefix(table_data, guest_index_bits, 1);
  465. /* Hart Index Bits */
  466. build_append_int_noprefix(table_data, hart_index_bits, 1);
  467. /* Group Index Bits */
  468. build_append_int_noprefix(table_data, group_index_bits, 1);
  469. /* Group Index Shift */
  470. build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1);
  471. }
  472. if (s->aia_type != VIRT_AIA_TYPE_NONE) {
  473. /* APLICs */
  474. for (socket = 0; socket < riscv_socket_count(ms); socket++) {
  475. aplic_addr = s->memmap[VIRT_APLIC_S].base +
  476. s->memmap[VIRT_APLIC_S].size * socket;
  477. gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
  478. build_append_int_noprefix(table_data, 0x1A, 1); /* Type */
  479. build_append_int_noprefix(table_data, 36, 1); /* Length */
  480. build_append_int_noprefix(table_data, 1, 1); /* Version */
  481. build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */
  482. build_append_int_noprefix(table_data, 0, 4); /* Flags */
  483. build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
  484. /* Number of IDCs */
  485. if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
  486. build_append_int_noprefix(table_data,
  487. s->soc[socket].num_harts,
  488. 2);
  489. } else {
  490. build_append_int_noprefix(table_data, 0, 2);
  491. }
  492. /* Total External Interrupt Sources Supported */
  493. build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2);
  494. /* Global System Interrupt Base */
  495. build_append_int_noprefix(table_data, gsi_base, 4);
  496. /* APLIC Address */
  497. build_append_int_noprefix(table_data, aplic_addr, 8);
  498. /* APLIC size */
  499. build_append_int_noprefix(table_data,
  500. s->memmap[VIRT_APLIC_S].size, 4);
  501. }
  502. } else {
  503. /* PLICs */
  504. for (socket = 0; socket < riscv_socket_count(ms); socket++) {
  505. aplic_addr = s->memmap[VIRT_PLIC].base +
  506. s->memmap[VIRT_PLIC].size * socket;
  507. gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
  508. build_append_int_noprefix(table_data, 0x1B, 1); /* Type */
  509. build_append_int_noprefix(table_data, 36, 1); /* Length */
  510. build_append_int_noprefix(table_data, 1, 1); /* Version */
  511. build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */
  512. build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
  513. /* Total External Interrupt Sources Supported */
  514. build_append_int_noprefix(table_data,
  515. VIRT_IRQCHIP_NUM_SOURCES - 1, 2);
  516. build_append_int_noprefix(table_data, 0, 2); /* Max Priority */
  517. build_append_int_noprefix(table_data, 0, 4); /* Flags */
  518. /* PLIC Size */
  519. build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4);
  520. /* PLIC Address */
  521. build_append_int_noprefix(table_data, aplic_addr, 8);
  522. /* Global System Interrupt Vector Base */
  523. build_append_int_noprefix(table_data, gsi_base, 4);
  524. }
  525. }
  526. acpi_table_end(linker, &table);
  527. }
  528. /*
  529. * ACPI spec, Revision 6.5+
  530. * 5.2.16 System Resource Affinity Table (SRAT)
  531. * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/25
  532. * https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view
  533. */
  534. static void
  535. build_srat(GArray *table_data, BIOSLinker *linker, RISCVVirtState *vms)
  536. {
  537. int i;
  538. uint64_t mem_base;
  539. MachineClass *mc = MACHINE_GET_CLASS(vms);
  540. MachineState *ms = MACHINE(vms);
  541. const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
  542. AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
  543. .oem_table_id = vms->oem_table_id };
  544. acpi_table_begin(&table, table_data);
  545. build_append_int_noprefix(table_data, 1, 4); /* Reserved */
  546. build_append_int_noprefix(table_data, 0, 8); /* Reserved */
  547. for (i = 0; i < cpu_list->len; ++i) {
  548. uint32_t nodeid = cpu_list->cpus[i].props.node_id;
  549. /*
  550. * 5.2.16.8 RINTC Affinity Structure
  551. */
  552. build_append_int_noprefix(table_data, 7, 1); /* Type */
  553. build_append_int_noprefix(table_data, 20, 1); /* Length */
  554. build_append_int_noprefix(table_data, 0, 2); /* Reserved */
  555. build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
  556. build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
  557. /* Flags, Table 5-70 */
  558. build_append_int_noprefix(table_data, 1 /* Flags: Enabled */, 4);
  559. build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
  560. }
  561. mem_base = vms->memmap[VIRT_DRAM].base;
  562. for (i = 0; i < ms->numa_state->num_nodes; ++i) {
  563. if (ms->numa_state->nodes[i].node_mem > 0) {
  564. build_srat_memory(table_data, mem_base,
  565. ms->numa_state->nodes[i].node_mem, i,
  566. MEM_AFFINITY_ENABLED);
  567. mem_base += ms->numa_state->nodes[i].node_mem;
  568. }
  569. }
  570. acpi_table_end(linker, &table);
  571. }
  572. static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
  573. {
  574. GArray *table_offsets;
  575. unsigned dsdt, xsdt;
  576. GArray *tables_blob = tables->table_data;
  577. MachineState *ms = MACHINE(s);
  578. table_offsets = g_array_new(false, true,
  579. sizeof(uint32_t));
  580. bios_linker_loader_alloc(tables->linker,
  581. ACPI_BUILD_TABLE_FILE, tables_blob,
  582. 64, false);
  583. /* DSDT is pointed to by FADT */
  584. dsdt = tables_blob->len;
  585. build_dsdt(tables_blob, tables->linker, s);
  586. /* FADT and others pointed to by XSDT */
  587. acpi_add_table(table_offsets, tables_blob);
  588. build_fadt_rev6(tables_blob, tables->linker, s, dsdt);
  589. acpi_add_table(table_offsets, tables_blob);
  590. build_madt(tables_blob, tables->linker, s);
  591. acpi_add_table(table_offsets, tables_blob);
  592. build_rhct(tables_blob, tables->linker, s);
  593. acpi_add_table(table_offsets, tables_blob);
  594. spcr_setup(tables_blob, tables->linker, s);
  595. acpi_add_table(table_offsets, tables_blob);
  596. {
  597. AcpiMcfgInfo mcfg = {
  598. .base = s->memmap[VIRT_PCIE_ECAM].base,
  599. .size = s->memmap[VIRT_PCIE_ECAM].size,
  600. };
  601. build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id,
  602. s->oem_table_id);
  603. }
  604. if (ms->numa_state->num_nodes > 0) {
  605. acpi_add_table(table_offsets, tables_blob);
  606. build_srat(tables_blob, tables->linker, s);
  607. if (ms->numa_state->have_numa_distance) {
  608. acpi_add_table(table_offsets, tables_blob);
  609. build_slit(tables_blob, tables->linker, ms, s->oem_id,
  610. s->oem_table_id);
  611. }
  612. }
  613. /* XSDT is pointed to by RSDP */
  614. xsdt = tables_blob->len;
  615. build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
  616. s->oem_table_id);
  617. /* RSDP is in FSEG memory, so allocate it separately */
  618. {
  619. AcpiRsdpData rsdp_data = {
  620. .revision = 2,
  621. .oem_id = s->oem_id,
  622. .xsdt_tbl_offset = &xsdt,
  623. .rsdt_tbl_offset = NULL,
  624. };
  625. build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
  626. }
  627. /*
  628. * The align size is 128, warn if 64k is not enough therefore
  629. * the align size could be resized.
  630. */
  631. if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
  632. warn_report("ACPI table size %u exceeds %d bytes,"
  633. " migration may not work",
  634. tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
  635. error_printf("Try removing some objects.");
  636. }
  637. acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
  638. /* Clean up memory that's no longer used */
  639. g_array_free(table_offsets, true);
  640. }
  641. static void acpi_ram_update(MemoryRegion *mr, GArray *data)
  642. {
  643. uint32_t size = acpi_data_len(data);
  644. /*
  645. * Make sure RAM size is correct - in case it got changed
  646. * e.g. by migration
  647. */
  648. memory_region_ram_resize(mr, size, &error_abort);
  649. memcpy(memory_region_get_ram_ptr(mr), data->data, size);
  650. memory_region_set_dirty(mr, 0, size);
  651. }
  652. static void virt_acpi_build_update(void *build_opaque)
  653. {
  654. AcpiBuildState *build_state = build_opaque;
  655. AcpiBuildTables tables;
  656. /* No state to update or already patched? Nothing to do. */
  657. if (!build_state || build_state->patched) {
  658. return;
  659. }
  660. build_state->patched = true;
  661. acpi_build_tables_init(&tables);
  662. virt_acpi_build(RISCV_VIRT_MACHINE(qdev_get_machine()), &tables);
  663. acpi_ram_update(build_state->table_mr, tables.table_data);
  664. acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
  665. acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
  666. acpi_build_tables_cleanup(&tables, true);
  667. }
  668. static void virt_acpi_build_reset(void *build_opaque)
  669. {
  670. AcpiBuildState *build_state = build_opaque;
  671. build_state->patched = false;
  672. }
  673. static const VMStateDescription vmstate_virt_acpi_build = {
  674. .name = "virt_acpi_build",
  675. .version_id = 1,
  676. .minimum_version_id = 1,
  677. .fields = (const VMStateField[]) {
  678. VMSTATE_BOOL(patched, AcpiBuildState),
  679. VMSTATE_END_OF_LIST()
  680. },
  681. };
  682. void virt_acpi_setup(RISCVVirtState *s)
  683. {
  684. AcpiBuildTables tables;
  685. AcpiBuildState *build_state;
  686. build_state = g_malloc0(sizeof *build_state);
  687. acpi_build_tables_init(&tables);
  688. virt_acpi_build(s, &tables);
  689. /* Now expose it all to Guest */
  690. build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
  691. build_state, tables.table_data,
  692. ACPI_BUILD_TABLE_FILE);
  693. assert(build_state->table_mr != NULL);
  694. build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
  695. build_state,
  696. tables.linker->cmd_blob,
  697. ACPI_BUILD_LOADER_FILE);
  698. build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
  699. build_state, tables.rsdp,
  700. ACPI_BUILD_RSDP_FILE);
  701. qemu_register_reset(virt_acpi_build_reset, build_state);
  702. virt_acpi_build_reset(build_state);
  703. vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
  704. /*
  705. * Clean up tables but don't free the memory: we track it
  706. * in build_state.
  707. */
  708. acpi_build_tables_cleanup(&tables, false);
  709. }