spapr_nested.c 65 KB

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  1. #include "qemu/osdep.h"
  2. #include "qemu/cutils.h"
  3. #include "exec/exec-all.h"
  4. #include "exec/cputlb.h"
  5. #include "helper_regs.h"
  6. #include "hw/ppc/ppc.h"
  7. #include "hw/ppc/spapr.h"
  8. #include "hw/ppc/spapr_cpu_core.h"
  9. #include "hw/ppc/spapr_nested.h"
  10. #include "mmu-book3s-v3.h"
  11. #include "cpu-models.h"
  12. #include "qemu/log.h"
  13. void spapr_nested_reset(SpaprMachineState *spapr)
  14. {
  15. if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) {
  16. spapr_unregister_nested_hv();
  17. spapr_register_nested_hv();
  18. } else if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_PAPR)) {
  19. spapr->nested.capabilities_set = false;
  20. spapr_unregister_nested_papr();
  21. spapr_register_nested_papr();
  22. spapr_nested_gsb_init();
  23. } else {
  24. spapr->nested.api = 0;
  25. }
  26. }
  27. uint8_t spapr_nested_api(SpaprMachineState *spapr)
  28. {
  29. return spapr->nested.api;
  30. }
  31. #ifdef CONFIG_TCG
  32. bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
  33. target_ulong lpid, ppc_v3_pate_t *entry)
  34. {
  35. uint64_t patb, pats;
  36. assert(lpid != 0);
  37. patb = spapr->nested.ptcr & PTCR_PATB;
  38. pats = spapr->nested.ptcr & PTCR_PATS;
  39. /* Check if partition table is properly aligned */
  40. if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
  41. return false;
  42. }
  43. /* Calculate number of entries */
  44. pats = 1ull << (pats + 12 - 4);
  45. if (pats <= lpid) {
  46. return false;
  47. }
  48. /* Grab entry */
  49. patb += 16 * lpid;
  50. entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
  51. entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
  52. return true;
  53. }
  54. static
  55. SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *spapr,
  56. target_ulong guestid)
  57. {
  58. return spapr->nested.guests ?
  59. g_hash_table_lookup(spapr->nested.guests,
  60. GINT_TO_POINTER(guestid)) : NULL;
  61. }
  62. bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu,
  63. target_ulong lpid, ppc_v3_pate_t *entry)
  64. {
  65. SpaprMachineStateNestedGuest *guest;
  66. assert(lpid != 0);
  67. guest = spapr_get_nested_guest(spapr, lpid);
  68. if (!guest) {
  69. return false;
  70. }
  71. entry->dw0 = guest->parttbl[0];
  72. entry->dw1 = guest->parttbl[1];
  73. return true;
  74. }
  75. #define PRTS_MASK 0x1f
  76. static target_ulong h_set_ptbl(PowerPCCPU *cpu,
  77. SpaprMachineState *spapr,
  78. target_ulong opcode,
  79. target_ulong *args)
  80. {
  81. target_ulong ptcr = args[0];
  82. if (!spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) {
  83. return H_FUNCTION;
  84. }
  85. if ((ptcr & PRTS_MASK) + 12 - 4 > 12) {
  86. return H_PARAMETER;
  87. }
  88. spapr->nested.ptcr = ptcr; /* Save new partition table */
  89. return H_SUCCESS;
  90. }
  91. static target_ulong h_tlb_invalidate(PowerPCCPU *cpu,
  92. SpaprMachineState *spapr,
  93. target_ulong opcode,
  94. target_ulong *args)
  95. {
  96. /*
  97. * The spapr virtual hypervisor nested HV implementation retains no L2
  98. * translation state except for TLB. And the TLB is always invalidated
  99. * across L1<->L2 transitions, so nothing is required here.
  100. */
  101. return H_SUCCESS;
  102. }
  103. static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu,
  104. SpaprMachineState *spapr,
  105. target_ulong opcode,
  106. target_ulong *args)
  107. {
  108. /*
  109. * This HCALL is not required, L1 KVM will take a slow path and walk the
  110. * page tables manually to do the data copy.
  111. */
  112. return H_FUNCTION;
  113. }
  114. static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU *cpu)
  115. {
  116. CPUPPCState *env = &cpu->env;
  117. SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  118. memcpy(save->gpr, env->gpr, sizeof(save->gpr));
  119. save->lr = env->lr;
  120. save->ctr = env->ctr;
  121. save->cfar = env->cfar;
  122. save->msr = env->msr;
  123. save->nip = env->nip;
  124. save->cr = ppc_get_cr(env);
  125. save->xer = cpu_read_xer(env);
  126. save->lpcr = env->spr[SPR_LPCR];
  127. save->lpidr = env->spr[SPR_LPIDR];
  128. save->pcr = env->spr[SPR_PCR];
  129. save->dpdes = env->spr[SPR_DPDES];
  130. save->hfscr = env->spr[SPR_HFSCR];
  131. save->srr0 = env->spr[SPR_SRR0];
  132. save->srr1 = env->spr[SPR_SRR1];
  133. save->sprg0 = env->spr[SPR_SPRG0];
  134. save->sprg1 = env->spr[SPR_SPRG1];
  135. save->sprg2 = env->spr[SPR_SPRG2];
  136. save->sprg3 = env->spr[SPR_SPRG3];
  137. save->pidr = env->spr[SPR_BOOKS_PID];
  138. save->ppr = env->spr[SPR_PPR];
  139. if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
  140. save->amor = env->spr[SPR_AMOR];
  141. save->dawr0 = env->spr[SPR_DAWR0];
  142. save->dawrx0 = env->spr[SPR_DAWRX0];
  143. save->ciabr = env->spr[SPR_CIABR];
  144. save->purr = env->spr[SPR_PURR];
  145. save->spurr = env->spr[SPR_SPURR];
  146. save->ic = env->spr[SPR_IC];
  147. save->vtb = env->spr[SPR_VTB];
  148. save->hdar = env->spr[SPR_HDAR];
  149. save->hdsisr = env->spr[SPR_HDSISR];
  150. save->heir = env->spr[SPR_HEIR];
  151. save->asdr = env->spr[SPR_ASDR];
  152. save->dawr1 = env->spr[SPR_DAWR1];
  153. save->dawrx1 = env->spr[SPR_DAWRX1];
  154. save->dexcr = env->spr[SPR_DEXCR];
  155. save->hdexcr = env->spr[SPR_HDEXCR];
  156. save->hashkeyr = env->spr[SPR_HASHKEYR];
  157. save->hashpkeyr = env->spr[SPR_HASHPKEYR];
  158. memcpy(save->vsr, env->vsr, sizeof(save->vsr));
  159. save->ebbhr = env->spr[SPR_EBBHR];
  160. save->tar = env->spr[SPR_TAR];
  161. save->ebbrr = env->spr[SPR_EBBRR];
  162. save->bescr = env->spr[SPR_BESCR];
  163. save->iamr = env->spr[SPR_IAMR];
  164. save->amr = env->spr[SPR_AMR];
  165. save->uamor = env->spr[SPR_UAMOR];
  166. save->dscr = env->spr[SPR_DSCR];
  167. save->fscr = env->spr[SPR_FSCR];
  168. save->pspb = env->spr[SPR_PSPB];
  169. save->ctrl = env->spr[SPR_CTRL];
  170. save->vrsave = env->spr[SPR_VRSAVE];
  171. save->dar = env->spr[SPR_DAR];
  172. save->dsisr = env->spr[SPR_DSISR];
  173. save->pmc1 = env->spr[SPR_POWER_PMC1];
  174. save->pmc2 = env->spr[SPR_POWER_PMC2];
  175. save->pmc3 = env->spr[SPR_POWER_PMC3];
  176. save->pmc4 = env->spr[SPR_POWER_PMC4];
  177. save->pmc5 = env->spr[SPR_POWER_PMC5];
  178. save->pmc6 = env->spr[SPR_POWER_PMC6];
  179. save->mmcr0 = env->spr[SPR_POWER_MMCR0];
  180. save->mmcr1 = env->spr[SPR_POWER_MMCR1];
  181. save->mmcr2 = env->spr[SPR_POWER_MMCR2];
  182. save->mmcra = env->spr[SPR_POWER_MMCRA];
  183. save->sdar = env->spr[SPR_POWER_SDAR];
  184. save->siar = env->spr[SPR_POWER_SIAR];
  185. save->sier = env->spr[SPR_POWER_SIER];
  186. save->vscr = ppc_get_vscr(env);
  187. save->fpscr = env->fpscr;
  188. } else if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
  189. save->tb_offset = env->tb_env->tb_offset;
  190. }
  191. }
  192. static void nested_post_load_state(CPUPPCState *env, CPUState *cs)
  193. {
  194. /*
  195. * compute hflags and possible interrupts.
  196. */
  197. hreg_compute_hflags(env);
  198. ppc_maybe_interrupt(env);
  199. /*
  200. * Nested HV does not tag TLB entries between L1 and L2, so must
  201. * flush on transition.
  202. */
  203. tlb_flush(cs);
  204. env->reserve_addr = -1; /* Reset the reservation */
  205. }
  206. static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *load)
  207. {
  208. CPUPPCState *env = &cpu->env;
  209. SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  210. memcpy(env->gpr, load->gpr, sizeof(env->gpr));
  211. env->lr = load->lr;
  212. env->ctr = load->ctr;
  213. env->cfar = load->cfar;
  214. env->msr = load->msr;
  215. env->nip = load->nip;
  216. ppc_set_cr(env, load->cr);
  217. cpu_write_xer(env, load->xer);
  218. env->spr[SPR_LPCR] = load->lpcr;
  219. env->spr[SPR_LPIDR] = load->lpidr;
  220. env->spr[SPR_PCR] = load->pcr;
  221. env->spr[SPR_DPDES] = load->dpdes;
  222. env->spr[SPR_HFSCR] = load->hfscr;
  223. env->spr[SPR_SRR0] = load->srr0;
  224. env->spr[SPR_SRR1] = load->srr1;
  225. env->spr[SPR_SPRG0] = load->sprg0;
  226. env->spr[SPR_SPRG1] = load->sprg1;
  227. env->spr[SPR_SPRG2] = load->sprg2;
  228. env->spr[SPR_SPRG3] = load->sprg3;
  229. env->spr[SPR_BOOKS_PID] = load->pidr;
  230. env->spr[SPR_PPR] = load->ppr;
  231. if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
  232. env->spr[SPR_AMOR] = load->amor;
  233. env->spr[SPR_DAWR0] = load->dawr0;
  234. env->spr[SPR_DAWRX0] = load->dawrx0;
  235. env->spr[SPR_CIABR] = load->ciabr;
  236. env->spr[SPR_PURR] = load->purr;
  237. env->spr[SPR_SPURR] = load->purr;
  238. env->spr[SPR_IC] = load->ic;
  239. env->spr[SPR_VTB] = load->vtb;
  240. env->spr[SPR_HDAR] = load->hdar;
  241. env->spr[SPR_HDSISR] = load->hdsisr;
  242. env->spr[SPR_HEIR] = load->heir;
  243. env->spr[SPR_ASDR] = load->asdr;
  244. env->spr[SPR_DAWR1] = load->dawr1;
  245. env->spr[SPR_DAWRX1] = load->dawrx1;
  246. env->spr[SPR_DEXCR] = load->dexcr;
  247. env->spr[SPR_HDEXCR] = load->hdexcr;
  248. env->spr[SPR_HASHKEYR] = load->hashkeyr;
  249. env->spr[SPR_HASHPKEYR] = load->hashpkeyr;
  250. memcpy(env->vsr, load->vsr, sizeof(env->vsr));
  251. env->spr[SPR_EBBHR] = load->ebbhr;
  252. env->spr[SPR_TAR] = load->tar;
  253. env->spr[SPR_EBBRR] = load->ebbrr;
  254. env->spr[SPR_BESCR] = load->bescr;
  255. env->spr[SPR_IAMR] = load->iamr;
  256. env->spr[SPR_AMR] = load->amr;
  257. env->spr[SPR_UAMOR] = load->uamor;
  258. env->spr[SPR_DSCR] = load->dscr;
  259. env->spr[SPR_FSCR] = load->fscr;
  260. env->spr[SPR_PSPB] = load->pspb;
  261. env->spr[SPR_CTRL] = load->ctrl;
  262. env->spr[SPR_VRSAVE] = load->vrsave;
  263. env->spr[SPR_DAR] = load->dar;
  264. env->spr[SPR_DSISR] = load->dsisr;
  265. env->spr[SPR_POWER_PMC1] = load->pmc1;
  266. env->spr[SPR_POWER_PMC2] = load->pmc2;
  267. env->spr[SPR_POWER_PMC3] = load->pmc3;
  268. env->spr[SPR_POWER_PMC4] = load->pmc4;
  269. env->spr[SPR_POWER_PMC5] = load->pmc5;
  270. env->spr[SPR_POWER_PMC6] = load->pmc6;
  271. env->spr[SPR_POWER_MMCR0] = load->mmcr0;
  272. env->spr[SPR_POWER_MMCR1] = load->mmcr1;
  273. env->spr[SPR_POWER_MMCR2] = load->mmcr2;
  274. env->spr[SPR_POWER_MMCRA] = load->mmcra;
  275. env->spr[SPR_POWER_SDAR] = load->sdar;
  276. env->spr[SPR_POWER_SIAR] = load->siar;
  277. env->spr[SPR_POWER_SIER] = load->sier;
  278. ppc_store_vscr(env, load->vscr);
  279. ppc_store_fpscr(env, load->fpscr);
  280. } else if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
  281. env->tb_env->tb_offset = load->tb_offset;
  282. }
  283. }
  284. /*
  285. * When this handler returns, the environment is switched to the L2 guest
  286. * and TCG begins running that. spapr_exit_nested() performs the switch from
  287. * L2 back to L1 and returns from the H_ENTER_NESTED hcall.
  288. */
  289. static target_ulong h_enter_nested(PowerPCCPU *cpu,
  290. SpaprMachineState *spapr,
  291. target_ulong opcode,
  292. target_ulong *args)
  293. {
  294. PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  295. CPUPPCState *env = &cpu->env;
  296. CPUState *cs = CPU(cpu);
  297. SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  298. struct nested_ppc_state l2_state;
  299. target_ulong hv_ptr = args[0];
  300. target_ulong regs_ptr = args[1];
  301. target_ulong hdec, now = cpu_ppc_load_tbl(env);
  302. target_ulong lpcr, lpcr_mask;
  303. struct kvmppc_hv_guest_state *hvstate;
  304. struct kvmppc_hv_guest_state hv_state;
  305. struct kvmppc_pt_regs *regs;
  306. hwaddr len;
  307. if (spapr->nested.ptcr == 0) {
  308. return H_NOT_AVAILABLE;
  309. }
  310. len = sizeof(*hvstate);
  311. hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, false,
  312. MEMTXATTRS_UNSPECIFIED);
  313. if (len != sizeof(*hvstate)) {
  314. address_space_unmap(CPU(cpu)->as, hvstate, len, 0, false);
  315. return H_PARAMETER;
  316. }
  317. memcpy(&hv_state, hvstate, len);
  318. address_space_unmap(CPU(cpu)->as, hvstate, len, len, false);
  319. /*
  320. * We accept versions 1 and 2. Version 2 fields are unused because TCG
  321. * does not implement DAWR*.
  322. */
  323. if (hv_state.version > HV_GUEST_STATE_VERSION) {
  324. return H_PARAMETER;
  325. }
  326. if (hv_state.lpid == 0) {
  327. return H_PARAMETER;
  328. }
  329. spapr_cpu->nested_host_state = g_try_new(struct nested_ppc_state, 1);
  330. if (!spapr_cpu->nested_host_state) {
  331. return H_NO_MEM;
  332. }
  333. assert(env->spr[SPR_LPIDR] == 0);
  334. assert(env->spr[SPR_DPDES] == 0);
  335. nested_save_state(spapr_cpu->nested_host_state, cpu);
  336. len = sizeof(*regs);
  337. regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, false,
  338. MEMTXATTRS_UNSPECIFIED);
  339. if (!regs || len != sizeof(*regs)) {
  340. address_space_unmap(CPU(cpu)->as, regs, len, 0, false);
  341. g_free(spapr_cpu->nested_host_state);
  342. return H_P2;
  343. }
  344. len = sizeof(l2_state.gpr);
  345. assert(len == sizeof(regs->gpr));
  346. memcpy(l2_state.gpr, regs->gpr, len);
  347. l2_state.lr = regs->link;
  348. l2_state.ctr = regs->ctr;
  349. l2_state.xer = regs->xer;
  350. l2_state.cr = regs->ccr;
  351. l2_state.msr = regs->msr;
  352. l2_state.nip = regs->nip;
  353. address_space_unmap(CPU(cpu)->as, regs, len, len, false);
  354. l2_state.cfar = hv_state.cfar;
  355. l2_state.lpidr = hv_state.lpid;
  356. lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER;
  357. lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask);
  358. lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE;
  359. lpcr &= ~LPCR_LPES0;
  360. l2_state.lpcr = lpcr & pcc->lpcr_mask;
  361. l2_state.pcr = hv_state.pcr;
  362. /* hv_state.amor is not used */
  363. l2_state.dpdes = hv_state.dpdes;
  364. l2_state.hfscr = hv_state.hfscr;
  365. /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/
  366. l2_state.srr0 = hv_state.srr0;
  367. l2_state.srr1 = hv_state.srr1;
  368. l2_state.sprg0 = hv_state.sprg[0];
  369. l2_state.sprg1 = hv_state.sprg[1];
  370. l2_state.sprg2 = hv_state.sprg[2];
  371. l2_state.sprg3 = hv_state.sprg[3];
  372. l2_state.pidr = hv_state.pidr;
  373. l2_state.ppr = hv_state.ppr;
  374. l2_state.tb_offset = env->tb_env->tb_offset + hv_state.tb_offset;
  375. /*
  376. * Switch to the nested guest environment and start the "hdec" timer.
  377. */
  378. nested_load_state(cpu, &l2_state);
  379. nested_post_load_state(env, cs);
  380. hdec = hv_state.hdec_expiry - now;
  381. cpu_ppc_hdecr_init(env);
  382. cpu_ppc_store_hdecr(env, hdec);
  383. /*
  384. * The hv_state.vcpu_token is not needed. It is used by the KVM
  385. * implementation to remember which L2 vCPU last ran on which physical
  386. * CPU so as to invalidate process scope translations if it is moved
  387. * between physical CPUs. For now TLBs are always flushed on L1<->L2
  388. * transitions so this is not a problem.
  389. *
  390. * Could validate that the same vcpu_token does not attempt to run on
  391. * different L1 vCPUs at the same time, but that would be a L1 KVM bug
  392. * and it's not obviously worth a new data structure to do it.
  393. */
  394. spapr_cpu->in_nested = true;
  395. /*
  396. * The spapr hcall helper sets env->gpr[3] to the return value, but at
  397. * this point the L1 is not returning from the hcall but rather we
  398. * start running the L2, so r3 must not be clobbered, so return env->gpr[3]
  399. * to leave it unchanged.
  400. */
  401. return env->gpr[3];
  402. }
  403. static void spapr_exit_nested_hv(PowerPCCPU *cpu, int excp)
  404. {
  405. CPUPPCState *env = &cpu->env;
  406. CPUState *cs = CPU(cpu);
  407. SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  408. struct nested_ppc_state l2_state;
  409. target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4];
  410. target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5];
  411. target_ulong hsrr0, hsrr1, hdar, asdr, hdsisr;
  412. struct kvmppc_hv_guest_state *hvstate;
  413. struct kvmppc_pt_regs *regs;
  414. hwaddr len;
  415. nested_save_state(&l2_state, cpu);
  416. hsrr0 = env->spr[SPR_HSRR0];
  417. hsrr1 = env->spr[SPR_HSRR1];
  418. hdar = env->spr[SPR_HDAR];
  419. hdsisr = env->spr[SPR_HDSISR];
  420. asdr = env->spr[SPR_ASDR];
  421. /*
  422. * Switch back to the host environment (including for any error).
  423. */
  424. assert(env->spr[SPR_LPIDR] != 0);
  425. nested_load_state(cpu, spapr_cpu->nested_host_state);
  426. nested_post_load_state(env, cs);
  427. env->gpr[3] = env->excp_vectors[excp]; /* hcall return value */
  428. cpu_ppc_hdecr_exit(env);
  429. spapr_cpu->in_nested = false;
  430. g_free(spapr_cpu->nested_host_state);
  431. spapr_cpu->nested_host_state = NULL;
  432. len = sizeof(*hvstate);
  433. hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true,
  434. MEMTXATTRS_UNSPECIFIED);
  435. if (len != sizeof(*hvstate)) {
  436. address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true);
  437. env->gpr[3] = H_PARAMETER;
  438. return;
  439. }
  440. hvstate->cfar = l2_state.cfar;
  441. hvstate->lpcr = l2_state.lpcr;
  442. hvstate->pcr = l2_state.pcr;
  443. hvstate->dpdes = l2_state.dpdes;
  444. hvstate->hfscr = l2_state.hfscr;
  445. if (excp == POWERPC_EXCP_HDSI) {
  446. hvstate->hdar = hdar;
  447. hvstate->hdsisr = hdsisr;
  448. hvstate->asdr = asdr;
  449. } else if (excp == POWERPC_EXCP_HISI) {
  450. hvstate->asdr = asdr;
  451. }
  452. /* HEIR should be implemented for HV mode and saved here. */
  453. hvstate->srr0 = l2_state.srr0;
  454. hvstate->srr1 = l2_state.srr1;
  455. hvstate->sprg[0] = l2_state.sprg0;
  456. hvstate->sprg[1] = l2_state.sprg1;
  457. hvstate->sprg[2] = l2_state.sprg2;
  458. hvstate->sprg[3] = l2_state.sprg3;
  459. hvstate->pidr = l2_state.pidr;
  460. hvstate->ppr = l2_state.ppr;
  461. /* Is it okay to specify write length larger than actual data written? */
  462. address_space_unmap(CPU(cpu)->as, hvstate, len, len, true);
  463. len = sizeof(*regs);
  464. regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true,
  465. MEMTXATTRS_UNSPECIFIED);
  466. if (!regs || len != sizeof(*regs)) {
  467. address_space_unmap(CPU(cpu)->as, regs, len, 0, true);
  468. env->gpr[3] = H_P2;
  469. return;
  470. }
  471. len = sizeof(env->gpr);
  472. assert(len == sizeof(regs->gpr));
  473. memcpy(regs->gpr, l2_state.gpr, len);
  474. regs->link = l2_state.lr;
  475. regs->ctr = l2_state.ctr;
  476. regs->xer = l2_state.xer;
  477. regs->ccr = l2_state.cr;
  478. if (excp == POWERPC_EXCP_MCHECK ||
  479. excp == POWERPC_EXCP_RESET ||
  480. excp == POWERPC_EXCP_SYSCALL) {
  481. regs->nip = l2_state.srr0;
  482. regs->msr = l2_state.srr1 & env->msr_mask;
  483. } else {
  484. regs->nip = hsrr0;
  485. regs->msr = hsrr1 & env->msr_mask;
  486. }
  487. /* Is it okay to specify write length larger than actual data written? */
  488. address_space_unmap(CPU(cpu)->as, regs, len, len, true);
  489. }
  490. static bool spapr_nested_vcpu_check(SpaprMachineStateNestedGuest *guest,
  491. target_ulong vcpuid, bool inoutbuf)
  492. {
  493. struct SpaprMachineStateNestedGuestVcpu *vcpu;
  494. /*
  495. * Perform sanity checks for the provided vcpuid of a guest.
  496. * For now, ensure its valid, allocated and enabled for use.
  497. */
  498. if (vcpuid >= PAPR_NESTED_GUEST_VCPU_MAX) {
  499. return false;
  500. }
  501. if (!(vcpuid < guest->nr_vcpus)) {
  502. return false;
  503. }
  504. vcpu = &guest->vcpus[vcpuid];
  505. if (!vcpu->enabled) {
  506. return false;
  507. }
  508. if (!inoutbuf) {
  509. return true;
  510. }
  511. /* Check to see if the in/out buffers are registered */
  512. if (vcpu->runbufin.addr && vcpu->runbufout.addr) {
  513. return true;
  514. }
  515. return false;
  516. }
  517. static void *get_vcpu_state_ptr(SpaprMachineState *spapr,
  518. SpaprMachineStateNestedGuest *guest,
  519. target_ulong vcpuid)
  520. {
  521. assert(spapr_nested_vcpu_check(guest, vcpuid, false));
  522. return &guest->vcpus[vcpuid].state;
  523. }
  524. static void *get_vcpu_ptr(SpaprMachineState *spapr,
  525. SpaprMachineStateNestedGuest *guest,
  526. target_ulong vcpuid)
  527. {
  528. assert(spapr_nested_vcpu_check(guest, vcpuid, false));
  529. return &guest->vcpus[vcpuid];
  530. }
  531. static void *get_guest_ptr(SpaprMachineState *spapr,
  532. SpaprMachineStateNestedGuest *guest,
  533. target_ulong vcpuid)
  534. {
  535. return guest; /* for GSBE_NESTED */
  536. }
  537. static void *get_machine_ptr(SpaprMachineState *spapr,
  538. SpaprMachineStateNestedGuest *guest,
  539. target_ulong vcpuid)
  540. {
  541. /* ignore guest and vcpuid for this */
  542. return &spapr->nested;
  543. }
  544. /*
  545. * set=1 means the L1 is trying to set some state
  546. * set=0 means the L1 is trying to get some state
  547. */
  548. static void copy_state_8to8(void *a, void *b, bool set)
  549. {
  550. /* set takes from the Big endian element_buf and sets internal buffer */
  551. if (set) {
  552. *(uint64_t *)a = be64_to_cpu(*(uint64_t *)b);
  553. } else {
  554. *(uint64_t *)b = cpu_to_be64(*(uint64_t *)a);
  555. }
  556. }
  557. static void copy_state_4to4(void *a, void *b, bool set)
  558. {
  559. if (set) {
  560. *(uint32_t *)a = be32_to_cpu(*(uint32_t *)b);
  561. } else {
  562. *(uint32_t *)b = cpu_to_be32(*((uint32_t *)a));
  563. }
  564. }
  565. static void copy_state_16to16(void *a, void *b, bool set)
  566. {
  567. uint64_t *src, *dst;
  568. if (set) {
  569. src = b;
  570. dst = a;
  571. dst[1] = be64_to_cpu(src[0]);
  572. dst[0] = be64_to_cpu(src[1]);
  573. } else {
  574. src = a;
  575. dst = b;
  576. dst[1] = cpu_to_be64(src[0]);
  577. dst[0] = cpu_to_be64(src[1]);
  578. }
  579. }
  580. static void copy_state_4to8(void *a, void *b, bool set)
  581. {
  582. if (set) {
  583. *(uint64_t *)a = (uint64_t) be32_to_cpu(*(uint32_t *)b);
  584. } else {
  585. *(uint32_t *)b = cpu_to_be32((uint32_t) (*((uint64_t *)a)));
  586. }
  587. }
  588. static void copy_state_pagetbl(void *a, void *b, bool set)
  589. {
  590. uint64_t *pagetbl;
  591. uint64_t *buf; /* 3 double words */
  592. uint64_t rts;
  593. assert(set);
  594. pagetbl = a;
  595. buf = b;
  596. *pagetbl = be64_to_cpu(buf[0]);
  597. /* as per ISA section 6.7.6.1 */
  598. *pagetbl |= PATE0_HR; /* Host Radix bit is 1 */
  599. /* RTS */
  600. rts = be64_to_cpu(buf[1]);
  601. assert(rts == 52);
  602. rts = rts - 31; /* since radix tree size = 2^(RTS+31) */
  603. *pagetbl |= ((rts & 0x7) << 5); /* RTS2 is bit 56:58 */
  604. *pagetbl |= (((rts >> 3) & 0x3) << 61); /* RTS1 is bit 1:2 */
  605. /* RPDS {Size = 2^(RPDS+3) , RPDS >=5} */
  606. *pagetbl |= 63 - clz64(be64_to_cpu(buf[2])) - 3;
  607. }
  608. static void copy_state_proctbl(void *a, void *b, bool set)
  609. {
  610. uint64_t *proctbl;
  611. uint64_t *buf; /* 2 double words */
  612. assert(set);
  613. proctbl = a;
  614. buf = b;
  615. /* PRTB: Process Table Base */
  616. *proctbl = be64_to_cpu(buf[0]);
  617. /* PRTS: Process Table Size = 2^(12+PRTS) */
  618. if (be64_to_cpu(buf[1]) == (1ULL << 12)) {
  619. *proctbl |= 0;
  620. } else if (be64_to_cpu(buf[1]) == (1ULL << 24)) {
  621. *proctbl |= 12;
  622. } else {
  623. g_assert_not_reached();
  624. }
  625. }
  626. static void copy_state_runbuf(void *a, void *b, bool set)
  627. {
  628. uint64_t *buf; /* 2 double words */
  629. struct SpaprMachineStateNestedGuestVcpuRunBuf *runbuf;
  630. assert(set);
  631. runbuf = a;
  632. buf = b;
  633. runbuf->addr = be64_to_cpu(buf[0]);
  634. assert(runbuf->addr);
  635. /* per spec */
  636. assert(be64_to_cpu(buf[1]) <= 16384);
  637. /*
  638. * This will also hit in the input buffer but should be fine for
  639. * now. If not we can split this function.
  640. */
  641. assert(be64_to_cpu(buf[1]) >= VCPU_OUT_BUF_MIN_SZ);
  642. runbuf->size = be64_to_cpu(buf[1]);
  643. }
  644. /* tell the L1 how big we want the output vcpu run buffer */
  645. static void out_buf_min_size(void *a, void *b, bool set)
  646. {
  647. uint64_t *buf; /* 1 double word */
  648. assert(!set);
  649. buf = b;
  650. buf[0] = cpu_to_be64(VCPU_OUT_BUF_MIN_SZ);
  651. }
  652. static void copy_logical_pvr(void *a, void *b, bool set)
  653. {
  654. SpaprMachineStateNestedGuest *guest;
  655. uint32_t *buf; /* 1 word */
  656. uint32_t *pvr_logical_ptr;
  657. uint32_t pvr_logical;
  658. target_ulong pcr = 0;
  659. pvr_logical_ptr = a;
  660. buf = b;
  661. if (!set) {
  662. buf[0] = cpu_to_be32(*pvr_logical_ptr);
  663. return;
  664. }
  665. pvr_logical = be32_to_cpu(buf[0]);
  666. *pvr_logical_ptr = pvr_logical;
  667. if (*pvr_logical_ptr) {
  668. switch (*pvr_logical_ptr) {
  669. case CPU_POWERPC_LOGICAL_3_10_P11:
  670. case CPU_POWERPC_LOGICAL_3_10:
  671. pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00;
  672. break;
  673. case CPU_POWERPC_LOGICAL_3_00:
  674. pcr = PCR_COMPAT_3_00;
  675. break;
  676. default:
  677. qemu_log_mask(LOG_GUEST_ERROR,
  678. "Could not set PCR for LPVR=0x%08x\n",
  679. *pvr_logical_ptr);
  680. return;
  681. }
  682. }
  683. guest = container_of(pvr_logical_ptr,
  684. struct SpaprMachineStateNestedGuest,
  685. pvr_logical);
  686. for (int i = 0; i < guest->nr_vcpus; i++) {
  687. guest->vcpus[i].state.pcr = ~pcr | HVMASK_PCR;
  688. }
  689. }
  690. static void copy_tb_offset(void *a, void *b, bool set)
  691. {
  692. SpaprMachineStateNestedGuest *guest;
  693. uint64_t *buf; /* 1 double word */
  694. uint64_t *tb_offset_ptr;
  695. uint64_t tb_offset;
  696. tb_offset_ptr = a;
  697. buf = b;
  698. if (!set) {
  699. buf[0] = cpu_to_be64(*tb_offset_ptr);
  700. return;
  701. }
  702. tb_offset = be64_to_cpu(buf[0]);
  703. /* need to copy this to the individual tb_offset for each vcpu */
  704. guest = container_of(tb_offset_ptr,
  705. struct SpaprMachineStateNestedGuest,
  706. tb_offset);
  707. for (int i = 0; i < guest->nr_vcpus; i++) {
  708. guest->vcpus[i].tb_offset = tb_offset;
  709. }
  710. }
  711. static void copy_state_hdecr(void *a, void *b, bool set)
  712. {
  713. uint64_t *buf; /* 1 double word */
  714. uint64_t *hdecr_expiry_tb;
  715. hdecr_expiry_tb = a;
  716. buf = b;
  717. if (!set) {
  718. buf[0] = cpu_to_be64(*hdecr_expiry_tb);
  719. return;
  720. }
  721. *hdecr_expiry_tb = be64_to_cpu(buf[0]);
  722. }
  723. struct guest_state_element_type guest_state_element_types[] = {
  724. GUEST_STATE_ELEMENT_NOP(GSB_HV_VCPU_IGNORED_ID, 0),
  725. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR0, gpr[0]),
  726. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR1, gpr[1]),
  727. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR2, gpr[2]),
  728. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR3, gpr[3]),
  729. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR4, gpr[4]),
  730. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR5, gpr[5]),
  731. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR6, gpr[6]),
  732. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR7, gpr[7]),
  733. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR8, gpr[8]),
  734. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR9, gpr[9]),
  735. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR10, gpr[10]),
  736. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR11, gpr[11]),
  737. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR12, gpr[12]),
  738. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR13, gpr[13]),
  739. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR14, gpr[14]),
  740. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR15, gpr[15]),
  741. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR16, gpr[16]),
  742. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR17, gpr[17]),
  743. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR18, gpr[18]),
  744. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR19, gpr[19]),
  745. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR20, gpr[20]),
  746. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR21, gpr[21]),
  747. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR22, gpr[22]),
  748. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR23, gpr[23]),
  749. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR24, gpr[24]),
  750. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR25, gpr[25]),
  751. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR26, gpr[26]),
  752. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR27, gpr[27]),
  753. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR28, gpr[28]),
  754. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR29, gpr[29]),
  755. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR30, gpr[30]),
  756. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR31, gpr[31]),
  757. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_NIA, nip),
  758. GSE_ENV_DWM(GSB_VCPU_SPR_MSR, msr, HVMASK_MSR),
  759. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTR, ctr),
  760. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_LR, lr),
  761. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_XER, xer),
  762. GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_CR, cr),
  763. GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_MMCR3),
  764. GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER2),
  765. GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER3),
  766. GUEST_STATE_ELEMENT_NOP_W(GSB_VCPU_SPR_WORT),
  767. GSE_ENV_DWM(GSB_VCPU_SPR_LPCR, lpcr, HVMASK_LPCR),
  768. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMOR, amor),
  769. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HFSCR, hfscr),
  770. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR0, dawr0),
  771. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX0, dawrx0),
  772. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CIABR, ciabr),
  773. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PURR, purr),
  774. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPURR, spurr),
  775. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IC, ic),
  776. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_VTB, vtb),
  777. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HDAR, hdar),
  778. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HDSISR, hdsisr),
  779. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HEIR, heir),
  780. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_ASDR, asdr),
  781. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR0, srr0),
  782. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR1, srr1),
  783. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG0, sprg0),
  784. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG1, sprg1),
  785. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG2, sprg2),
  786. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG3, sprg3),
  787. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PIDR, pidr),
  788. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CFAR, cfar),
  789. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PPR, ppr),
  790. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR1, dawr1),
  791. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX1, dawrx1),
  792. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DEXCR, dexcr),
  793. GSE_ENV_DWM(GSB_VCPU_SPR_HDEXCR, hdexcr, HVMASK_HDEXCR),
  794. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHKEYR, hashkeyr),
  795. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHPKEYR, hashpkeyr),
  796. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR0, vsr[0]),
  797. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR1, vsr[1]),
  798. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR2, vsr[2]),
  799. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR3, vsr[3]),
  800. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR4, vsr[4]),
  801. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR5, vsr[5]),
  802. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR6, vsr[6]),
  803. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR7, vsr[7]),
  804. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR8, vsr[8]),
  805. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR9, vsr[9]),
  806. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR10, vsr[10]),
  807. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR11, vsr[11]),
  808. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR12, vsr[12]),
  809. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR13, vsr[13]),
  810. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR14, vsr[14]),
  811. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR15, vsr[15]),
  812. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR16, vsr[16]),
  813. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR17, vsr[17]),
  814. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR18, vsr[18]),
  815. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR19, vsr[19]),
  816. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR20, vsr[20]),
  817. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR21, vsr[21]),
  818. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR22, vsr[22]),
  819. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR23, vsr[23]),
  820. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR24, vsr[24]),
  821. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR25, vsr[25]),
  822. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR26, vsr[26]),
  823. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR27, vsr[27]),
  824. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR28, vsr[28]),
  825. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR29, vsr[29]),
  826. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR30, vsr[30]),
  827. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR31, vsr[31]),
  828. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR32, vsr[32]),
  829. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR33, vsr[33]),
  830. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR34, vsr[34]),
  831. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR35, vsr[35]),
  832. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR36, vsr[36]),
  833. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR37, vsr[37]),
  834. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR38, vsr[38]),
  835. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR39, vsr[39]),
  836. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR40, vsr[40]),
  837. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR41, vsr[41]),
  838. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR42, vsr[42]),
  839. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR43, vsr[43]),
  840. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR44, vsr[44]),
  841. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR45, vsr[45]),
  842. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR46, vsr[46]),
  843. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR47, vsr[47]),
  844. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR48, vsr[48]),
  845. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR49, vsr[49]),
  846. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR50, vsr[50]),
  847. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR51, vsr[51]),
  848. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR52, vsr[52]),
  849. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR53, vsr[53]),
  850. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR54, vsr[54]),
  851. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR55, vsr[55]),
  852. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR56, vsr[56]),
  853. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR57, vsr[57]),
  854. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR58, vsr[58]),
  855. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR59, vsr[59]),
  856. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR60, vsr[60]),
  857. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR61, vsr[61]),
  858. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR62, vsr[62]),
  859. GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR63, vsr[63]),
  860. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBHR, ebbhr),
  861. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_TAR, tar),
  862. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBRR, ebbrr),
  863. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_BESCR, bescr),
  864. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IAMR, iamr),
  865. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMR, amr),
  866. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_UAMOR, uamor),
  867. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DSCR, dscr),
  868. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FSCR, fscr),
  869. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PSPB, pspb),
  870. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTRL, ctrl),
  871. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DPDES, dpdes),
  872. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_VRSAVE, vrsave),
  873. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAR, dar),
  874. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DSISR, dsisr),
  875. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC1, pmc1),
  876. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC2, pmc2),
  877. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC3, pmc3),
  878. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC4, pmc4),
  879. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC5, pmc5),
  880. GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC6, pmc6),
  881. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR0, mmcr0),
  882. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR1, mmcr1),
  883. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR2, mmcr2),
  884. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCRA, mmcra),
  885. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SDAR , sdar),
  886. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIAR , siar),
  887. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIER , sier),
  888. GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_VSCR, vscr),
  889. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FPSCR, fpscr),
  890. GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_DEC_EXPIRE_TB, dec_expiry_tb),
  891. GSBE_NESTED(GSB_PART_SCOPED_PAGETBL, 0x18, parttbl[0], copy_state_pagetbl),
  892. GSBE_NESTED(GSB_PROCESS_TBL, 0x10, parttbl[1], copy_state_proctbl),
  893. GSBE_NESTED(GSB_VCPU_LPVR, 0x4, pvr_logical, copy_logical_pvr),
  894. GSBE_NESTED_MSK(GSB_TB_OFFSET, 0x8, tb_offset, copy_tb_offset,
  895. HVMASK_TB_OFFSET),
  896. GSBE_NESTED_VCPU(GSB_VCPU_IN_BUFFER, 0x10, runbufin, copy_state_runbuf),
  897. GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUFFER, 0x10, runbufout, copy_state_runbuf),
  898. GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUF_MIN_SZ, 0x8, runbufout, out_buf_min_size),
  899. GSBE_NESTED_VCPU(GSB_VCPU_HDEC_EXPIRY_TB, 0x8, hdecr_expiry_tb,
  900. copy_state_hdecr),
  901. GSBE_NESTED_MACHINE_DW(GSB_L0_GUEST_HEAP_INUSE, l0_guest_heap_inuse),
  902. GSBE_NESTED_MACHINE_DW(GSB_L0_GUEST_HEAP_MAX, l0_guest_heap_max),
  903. GSBE_NESTED_MACHINE_DW(GSB_L0_GUEST_PGTABLE_SIZE_INUSE,
  904. l0_guest_pgtable_size_inuse),
  905. GSBE_NESTED_MACHINE_DW(GSB_L0_GUEST_PGTABLE_SIZE_MAX,
  906. l0_guest_pgtable_size_max),
  907. GSBE_NESTED_MACHINE_DW(GSB_L0_GUEST_PGTABLE_RECLAIMED,
  908. l0_guest_pgtable_reclaimed),
  909. };
  910. void spapr_nested_gsb_init(void)
  911. {
  912. struct guest_state_element_type *type;
  913. /* Init the guest state elements lookup table, flags for now */
  914. for (int i = 0; i < ARRAY_SIZE(guest_state_element_types); i++) {
  915. type = &guest_state_element_types[i];
  916. assert(type->id <= GSB_LAST);
  917. if (type->id >= GSB_VCPU_SPR_HDAR)
  918. /* 0xf000 - 0xf005 Thread + RO */
  919. type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY;
  920. else if (type->id >= GSB_VCPU_IN_BUFFER)
  921. /* 0x0c00 - 0xf000 Thread + RW */
  922. type->flags = 0;
  923. else if (type->id >= GSB_L0_GUEST_HEAP_INUSE)
  924. /*0x0800 - 0x0804 Hostwide Counters + RO */
  925. type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_HOST_WIDE |
  926. GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY;
  927. else if (type->id >= GSB_VCPU_LPVR)
  928. /* 0x0003 - 0x07ff Guest + RW */
  929. type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE;
  930. else if (type->id >= GSB_HV_VCPU_STATE_SIZE)
  931. /* 0x0001 - 0x0002 Guest + RO */
  932. type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY |
  933. GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE;
  934. }
  935. }
  936. static struct guest_state_element *guest_state_element_next(
  937. struct guest_state_element *element,
  938. int64_t *len,
  939. int64_t *num_elements)
  940. {
  941. uint16_t size;
  942. /* size is of element->value[] only. Not whole guest_state_element */
  943. size = be16_to_cpu(element->size);
  944. if (len) {
  945. *len -= size + offsetof(struct guest_state_element, value);
  946. }
  947. if (num_elements) {
  948. *num_elements -= 1;
  949. }
  950. return (struct guest_state_element *)(element->value + size);
  951. }
  952. static
  953. struct guest_state_element_type *guest_state_element_type_find(uint16_t id)
  954. {
  955. int i;
  956. for (i = 0; i < ARRAY_SIZE(guest_state_element_types); i++)
  957. if (id == guest_state_element_types[i].id) {
  958. return &guest_state_element_types[i];
  959. }
  960. return NULL;
  961. }
  962. static void log_element(struct guest_state_element *element,
  963. struct guest_state_request *gsr)
  964. {
  965. qemu_log_mask(LOG_GUEST_ERROR, "h_guest_%s_state id:0x%04x size:0x%04x",
  966. gsr->flags & GUEST_STATE_REQUEST_SET ? "set" : "get",
  967. be16_to_cpu(element->id), be16_to_cpu(element->size));
  968. qemu_log_mask(LOG_GUEST_ERROR, "buf:0x%016"PRIx64" ...\n",
  969. be64_to_cpu(*(uint64_t *)element->value));
  970. }
  971. static bool guest_state_request_check(struct guest_state_request *gsr)
  972. {
  973. int64_t num_elements, len = gsr->len;
  974. struct guest_state_buffer *gsb = gsr->gsb;
  975. struct guest_state_element *element;
  976. struct guest_state_element_type *type;
  977. uint16_t id, size;
  978. /* gsb->num_elements = 0 == 32 bits long */
  979. assert(len >= 4);
  980. num_elements = be32_to_cpu(gsb->num_elements);
  981. element = gsb->elements;
  982. len -= sizeof(gsb->num_elements);
  983. /* Walk the buffer to validate the length */
  984. while (num_elements) {
  985. id = be16_to_cpu(element->id);
  986. size = be16_to_cpu(element->size);
  987. if (false) {
  988. log_element(element, gsr);
  989. }
  990. /* buffer size too small */
  991. if (len < 0) {
  992. return false;
  993. }
  994. type = guest_state_element_type_find(id);
  995. if (!type) {
  996. qemu_log_mask(LOG_GUEST_ERROR, "Element ID %04x unknown\n", id);
  997. log_element(element, gsr);
  998. return false;
  999. }
  1000. if (id == GSB_HV_VCPU_IGNORED_ID) {
  1001. goto next_element;
  1002. }
  1003. if (size != type->size) {
  1004. qemu_log_mask(LOG_GUEST_ERROR, "Size mismatch. Element ID:%04x."
  1005. "Size Exp:%i Got:%i\n", id, type->size, size);
  1006. log_element(element, gsr);
  1007. return false;
  1008. }
  1009. if ((type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY) &&
  1010. (gsr->flags & GUEST_STATE_REQUEST_SET)) {
  1011. qemu_log_mask(LOG_GUEST_ERROR, "Trying to set a read-only Element "
  1012. "ID:%04x.\n", id);
  1013. return false;
  1014. }
  1015. if (type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_HOST_WIDE) {
  1016. /* Hostwide elements cant be clubbed with other types */
  1017. if (!(gsr->flags & GUEST_STATE_REQUEST_HOST_WIDE)) {
  1018. qemu_log_mask(LOG_GUEST_ERROR, "trying to get/set a host wide "
  1019. "Element ID:%04x.\n", id);
  1020. return false;
  1021. }
  1022. } else if (type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE) {
  1023. /* guest wide element type */
  1024. if (!(gsr->flags & GUEST_STATE_REQUEST_GUEST_WIDE)) {
  1025. qemu_log_mask(LOG_GUEST_ERROR, "trying to get/set a guest wide "
  1026. "Element ID:%04x.\n", id);
  1027. return false;
  1028. }
  1029. } else {
  1030. /* thread wide element type */
  1031. if (gsr->flags & (GUEST_STATE_REQUEST_GUEST_WIDE |
  1032. GUEST_STATE_REQUEST_HOST_WIDE)) {
  1033. qemu_log_mask(LOG_GUEST_ERROR, "trying to get/set a thread wide"
  1034. " Element ID:%04x.\n", id);
  1035. return false;
  1036. }
  1037. }
  1038. next_element:
  1039. element = guest_state_element_next(element, &len, &num_elements);
  1040. }
  1041. return true;
  1042. }
  1043. static bool is_gsr_invalid(struct guest_state_request *gsr,
  1044. struct guest_state_element *element,
  1045. struct guest_state_element_type *type)
  1046. {
  1047. if ((gsr->flags & GUEST_STATE_REQUEST_SET) &&
  1048. (*(uint64_t *)(element->value) & ~(type->mask))) {
  1049. log_element(element, gsr);
  1050. qemu_log_mask(LOG_GUEST_ERROR, "L1 can't set reserved bits "
  1051. "(allowed mask: 0x%08"PRIx64")\n", type->mask);
  1052. return true;
  1053. }
  1054. return false;
  1055. }
  1056. static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu,
  1057. SpaprMachineState *spapr,
  1058. target_ulong opcode,
  1059. target_ulong *args)
  1060. {
  1061. CPUPPCState *env = &cpu->env;
  1062. target_ulong flags = args[0];
  1063. if (flags) { /* don't handle any flags capabilities for now */
  1064. return H_PARAMETER;
  1065. }
  1066. /* P11 capabilities */
  1067. if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10_P11, 0,
  1068. spapr->max_compat_pvr)) {
  1069. env->gpr[4] |= H_GUEST_CAPABILITIES_P11_MODE;
  1070. }
  1071. /* P10 capabilities */
  1072. if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
  1073. spapr->max_compat_pvr)) {
  1074. env->gpr[4] |= H_GUEST_CAPABILITIES_P10_MODE;
  1075. }
  1076. /* P9 capabilities */
  1077. if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
  1078. spapr->max_compat_pvr)) {
  1079. env->gpr[4] |= H_GUEST_CAPABILITIES_P9_MODE;
  1080. }
  1081. return H_SUCCESS;
  1082. }
  1083. static target_ulong h_guest_set_capabilities(PowerPCCPU *cpu,
  1084. SpaprMachineState *spapr,
  1085. target_ulong opcode,
  1086. target_ulong *args)
  1087. {
  1088. CPUPPCState *env = &cpu->env;
  1089. target_ulong flags = args[0];
  1090. target_ulong capabilities = args[1];
  1091. env->gpr[4] = 0;
  1092. if (flags) { /* don't handle any flags capabilities for now */
  1093. return H_PARAMETER;
  1094. }
  1095. if (capabilities & H_GUEST_CAPABILITIES_COPY_MEM) {
  1096. env->gpr[4] = 1;
  1097. return H_P2; /* isn't supported */
  1098. }
  1099. /*
  1100. * If there are no capabilities configured, set the R5 to the index of
  1101. * the first supported Power Processor Mode
  1102. */
  1103. if (!capabilities) {
  1104. env->gpr[4] = 1;
  1105. /* set R5 to the first supported Power Processor Mode */
  1106. if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10_P11, 0,
  1107. spapr->max_compat_pvr)) {
  1108. env->gpr[5] = H_GUEST_CAP_P11_MODE_BMAP;
  1109. } else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
  1110. spapr->max_compat_pvr)) {
  1111. env->gpr[5] = H_GUEST_CAP_P10_MODE_BMAP;
  1112. } else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
  1113. spapr->max_compat_pvr)) {
  1114. env->gpr[5] = H_GUEST_CAP_P9_MODE_BMAP;
  1115. }
  1116. return H_P2;
  1117. }
  1118. /*
  1119. * If an invalid capability is set, R5 should contain the index of the
  1120. * invalid capability bit
  1121. */
  1122. if (capabilities & ~H_GUEST_CAP_VALID_MASK) {
  1123. env->gpr[4] = 1;
  1124. /* Set R5 to the index of the invalid capability */
  1125. env->gpr[5] = 63 - ctz64(capabilities);
  1126. return H_P2;
  1127. }
  1128. if (!spapr->nested.capabilities_set) {
  1129. spapr->nested.capabilities_set = true;
  1130. spapr->nested.pvr_base = env->spr[SPR_PVR];
  1131. return H_SUCCESS;
  1132. } else {
  1133. return H_STATE;
  1134. }
  1135. }
  1136. static void
  1137. destroy_guest_helper(gpointer value)
  1138. {
  1139. struct SpaprMachineStateNestedGuest *guest = value;
  1140. g_free(guest->vcpus);
  1141. g_free(guest);
  1142. }
  1143. static target_ulong h_guest_create(PowerPCCPU *cpu,
  1144. SpaprMachineState *spapr,
  1145. target_ulong opcode,
  1146. target_ulong *args)
  1147. {
  1148. CPUPPCState *env = &cpu->env;
  1149. target_ulong flags = args[0];
  1150. target_ulong continue_token = args[1];
  1151. uint64_t guestid;
  1152. int nguests = 0;
  1153. struct SpaprMachineStateNestedGuest *guest;
  1154. if (flags) { /* don't handle any flags for now */
  1155. return H_UNSUPPORTED_FLAG;
  1156. }
  1157. if (continue_token != -1) {
  1158. return H_P2;
  1159. }
  1160. if (!spapr->nested.capabilities_set) {
  1161. return H_STATE;
  1162. }
  1163. if (!spapr->nested.guests) {
  1164. spapr->nested.guests = g_hash_table_new_full(NULL,
  1165. NULL,
  1166. NULL,
  1167. destroy_guest_helper);
  1168. }
  1169. nguests = g_hash_table_size(spapr->nested.guests);
  1170. if (nguests == PAPR_NESTED_GUEST_MAX) {
  1171. return H_NO_MEM;
  1172. }
  1173. /* Lookup for available guestid */
  1174. for (guestid = 1; guestid < PAPR_NESTED_GUEST_MAX; guestid++) {
  1175. if (!(g_hash_table_lookup(spapr->nested.guests,
  1176. GINT_TO_POINTER(guestid)))) {
  1177. break;
  1178. }
  1179. }
  1180. if (guestid == PAPR_NESTED_GUEST_MAX) {
  1181. return H_NO_MEM;
  1182. }
  1183. guest = g_try_new0(struct SpaprMachineStateNestedGuest, 1);
  1184. if (!guest) {
  1185. return H_NO_MEM;
  1186. }
  1187. guest->pvr_logical = spapr->nested.pvr_base;
  1188. g_hash_table_insert(spapr->nested.guests, GINT_TO_POINTER(guestid), guest);
  1189. env->gpr[4] = guestid;
  1190. return H_SUCCESS;
  1191. }
  1192. static target_ulong h_guest_delete(PowerPCCPU *cpu,
  1193. SpaprMachineState *spapr,
  1194. target_ulong opcode,
  1195. target_ulong *args)
  1196. {
  1197. target_ulong flags = args[0];
  1198. target_ulong guestid = args[1];
  1199. struct SpaprMachineStateNestedGuest *guest;
  1200. /*
  1201. * handle flag deleteAllGuests, if set:
  1202. * guestid is ignored and all guests are deleted
  1203. *
  1204. */
  1205. if (flags & ~H_GUEST_DELETE_ALL_FLAG) {
  1206. return H_UNSUPPORTED_FLAG; /* other flag bits reserved */
  1207. } else if (flags & H_GUEST_DELETE_ALL_FLAG) {
  1208. g_hash_table_destroy(spapr->nested.guests);
  1209. return H_SUCCESS;
  1210. }
  1211. guest = g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(guestid));
  1212. if (!guest) {
  1213. return H_P2;
  1214. }
  1215. g_hash_table_remove(spapr->nested.guests, GINT_TO_POINTER(guestid));
  1216. return H_SUCCESS;
  1217. }
  1218. static target_ulong h_guest_create_vcpu(PowerPCCPU *cpu,
  1219. SpaprMachineState *spapr,
  1220. target_ulong opcode,
  1221. target_ulong *args)
  1222. {
  1223. target_ulong flags = args[0];
  1224. target_ulong guestid = args[1];
  1225. target_ulong vcpuid = args[2];
  1226. SpaprMachineStateNestedGuest *guest;
  1227. if (flags) { /* don't handle any flags for now */
  1228. return H_UNSUPPORTED_FLAG;
  1229. }
  1230. guest = spapr_get_nested_guest(spapr, guestid);
  1231. if (!guest) {
  1232. return H_P2;
  1233. }
  1234. if (vcpuid < guest->nr_vcpus) {
  1235. qemu_log_mask(LOG_UNIMP, "vcpuid " TARGET_FMT_ld " already in use.",
  1236. vcpuid);
  1237. return H_IN_USE;
  1238. }
  1239. /* linear vcpuid allocation only */
  1240. assert(vcpuid == guest->nr_vcpus);
  1241. if (guest->nr_vcpus >= PAPR_NESTED_GUEST_VCPU_MAX) {
  1242. return H_P3;
  1243. }
  1244. SpaprMachineStateNestedGuestVcpu *vcpus, *curr_vcpu;
  1245. vcpus = g_try_renew(struct SpaprMachineStateNestedGuestVcpu,
  1246. guest->vcpus,
  1247. guest->nr_vcpus + 1);
  1248. if (!vcpus) {
  1249. return H_NO_MEM;
  1250. }
  1251. guest->vcpus = vcpus;
  1252. curr_vcpu = &vcpus[guest->nr_vcpus];
  1253. memset(curr_vcpu, 0, sizeof(SpaprMachineStateNestedGuestVcpu));
  1254. curr_vcpu->enabled = true;
  1255. guest->nr_vcpus++;
  1256. return H_SUCCESS;
  1257. }
  1258. static target_ulong getset_state(SpaprMachineState *spapr,
  1259. SpaprMachineStateNestedGuest *guest,
  1260. uint64_t vcpuid,
  1261. struct guest_state_request *gsr)
  1262. {
  1263. void *ptr;
  1264. uint16_t id;
  1265. struct guest_state_element *element;
  1266. struct guest_state_element_type *type;
  1267. int64_t lenleft, num_elements;
  1268. lenleft = gsr->len;
  1269. if (!guest_state_request_check(gsr)) {
  1270. return H_P3;
  1271. }
  1272. num_elements = be32_to_cpu(gsr->gsb->num_elements);
  1273. element = gsr->gsb->elements;
  1274. /* Process the elements */
  1275. while (num_elements) {
  1276. type = NULL;
  1277. /* log_element(element, gsr); */
  1278. id = be16_to_cpu(element->id);
  1279. if (id == GSB_HV_VCPU_IGNORED_ID) {
  1280. goto next_element;
  1281. }
  1282. type = guest_state_element_type_find(id);
  1283. assert(type);
  1284. /* Get pointer to guest data to get/set */
  1285. if (type->location && type->copy) {
  1286. ptr = type->location(spapr, guest, vcpuid);
  1287. assert(ptr);
  1288. if (!~(type->mask) && is_gsr_invalid(gsr, element, type)) {
  1289. return H_INVALID_ELEMENT_VALUE;
  1290. }
  1291. type->copy(ptr + type->offset, element->value,
  1292. gsr->flags & GUEST_STATE_REQUEST_SET ? true : false);
  1293. }
  1294. next_element:
  1295. element = guest_state_element_next(element, &lenleft, &num_elements);
  1296. }
  1297. return H_SUCCESS;
  1298. }
  1299. static target_ulong map_and_getset_state(PowerPCCPU *cpu,
  1300. SpaprMachineState *spapr,
  1301. SpaprMachineStateNestedGuest *guest,
  1302. uint64_t vcpuid,
  1303. struct guest_state_request *gsr)
  1304. {
  1305. target_ulong rc;
  1306. int64_t len;
  1307. bool is_write;
  1308. len = gsr->len;
  1309. /* only get_state would require write access to the provided buffer */
  1310. is_write = (gsr->flags & GUEST_STATE_REQUEST_SET) ? false : true;
  1311. gsr->gsb = address_space_map(CPU(cpu)->as, gsr->buf, (uint64_t *)&len,
  1312. is_write, MEMTXATTRS_UNSPECIFIED);
  1313. if (!gsr->gsb) {
  1314. rc = H_P3;
  1315. goto out1;
  1316. }
  1317. if (len != gsr->len) {
  1318. rc = H_P3;
  1319. goto out1;
  1320. }
  1321. rc = getset_state(spapr, guest, vcpuid, gsr);
  1322. out1:
  1323. address_space_unmap(CPU(cpu)->as, gsr->gsb, len, is_write, len);
  1324. return rc;
  1325. }
  1326. static target_ulong h_guest_getset_state(PowerPCCPU *cpu,
  1327. SpaprMachineState *spapr,
  1328. target_ulong *args,
  1329. bool set)
  1330. {
  1331. target_ulong flags = args[0];
  1332. target_ulong lpid = args[1];
  1333. target_ulong vcpuid = args[2];
  1334. target_ulong buf = args[3];
  1335. target_ulong buflen = args[4];
  1336. struct guest_state_request gsr;
  1337. SpaprMachineStateNestedGuest *guest = NULL;
  1338. gsr.buf = buf;
  1339. assert(buflen <= GSB_MAX_BUF_SIZE);
  1340. gsr.len = buflen;
  1341. gsr.flags = 0;
  1342. /* Works for both get/set state */
  1343. if ((flags & H_GUEST_GET_STATE_FLAGS_GUEST_WIDE) ||
  1344. (flags & H_GUEST_SET_STATE_FLAGS_GUEST_WIDE)) {
  1345. gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE;
  1346. }
  1347. if (set) {
  1348. if (flags & ~H_GUEST_SET_STATE_FLAGS_MASK) {
  1349. return H_PARAMETER;
  1350. }
  1351. gsr.flags |= GUEST_STATE_REQUEST_SET;
  1352. } else {
  1353. /*
  1354. * No reserved fields to be set in flags nor both
  1355. * GUEST/HOST wide bits
  1356. */
  1357. if ((flags & ~H_GUEST_GET_STATE_FLAGS_MASK) ||
  1358. (flags == H_GUEST_GET_STATE_FLAGS_MASK)) {
  1359. return H_PARAMETER;
  1360. }
  1361. if (flags & H_GUEST_GET_STATE_FLAGS_HOST_WIDE) {
  1362. gsr.flags |= GUEST_STATE_REQUEST_HOST_WIDE;
  1363. }
  1364. }
  1365. if (!(gsr.flags & GUEST_STATE_REQUEST_HOST_WIDE)) {
  1366. guest = spapr_get_nested_guest(spapr, lpid);
  1367. if (!guest) {
  1368. return H_P2;
  1369. }
  1370. }
  1371. return map_and_getset_state(cpu, spapr, guest, vcpuid, &gsr);
  1372. }
  1373. static target_ulong h_guest_set_state(PowerPCCPU *cpu,
  1374. SpaprMachineState *spapr,
  1375. target_ulong opcode,
  1376. target_ulong *args)
  1377. {
  1378. return h_guest_getset_state(cpu, spapr, args, true);
  1379. }
  1380. static target_ulong h_guest_get_state(PowerPCCPU *cpu,
  1381. SpaprMachineState *spapr,
  1382. target_ulong opcode,
  1383. target_ulong *args)
  1384. {
  1385. return h_guest_getset_state(cpu, spapr, args, false);
  1386. }
  1387. static void exit_nested_store_l2(PowerPCCPU *cpu, int excp,
  1388. SpaprMachineStateNestedGuestVcpu *vcpu)
  1389. {
  1390. CPUPPCState *env = &cpu->env;
  1391. SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  1392. target_ulong now, hdar, hdsisr, asdr;
  1393. assert(sizeof(env->gpr) == sizeof(vcpu->state.gpr)); /* sanity check */
  1394. now = cpu_ppc_load_tbl(env); /* L2 timebase */
  1395. now -= vcpu->tb_offset; /* L1 timebase */
  1396. vcpu->state.dec_expiry_tb = now - cpu_ppc_load_decr(env);
  1397. cpu_ppc_store_decr(env, spapr_cpu->nested_host_state->dec_expiry_tb - now);
  1398. /* backup hdar, hdsisr, asdr if reqd later below */
  1399. hdar = vcpu->state.hdar;
  1400. hdsisr = vcpu->state.hdsisr;
  1401. asdr = vcpu->state.asdr;
  1402. nested_save_state(&vcpu->state, cpu);
  1403. if (excp == POWERPC_EXCP_MCHECK ||
  1404. excp == POWERPC_EXCP_RESET ||
  1405. excp == POWERPC_EXCP_SYSCALL) {
  1406. vcpu->state.nip = env->spr[SPR_SRR0];
  1407. vcpu->state.msr = env->spr[SPR_SRR1] & env->msr_mask;
  1408. } else {
  1409. vcpu->state.nip = env->spr[SPR_HSRR0];
  1410. vcpu->state.msr = env->spr[SPR_HSRR1] & env->msr_mask;
  1411. }
  1412. /* hdar, hdsisr, asdr should be retained unless certain exceptions */
  1413. if ((excp != POWERPC_EXCP_HDSI) && (excp != POWERPC_EXCP_HISI)) {
  1414. vcpu->state.asdr = asdr;
  1415. } else if (excp != POWERPC_EXCP_HDSI) {
  1416. vcpu->state.hdar = hdar;
  1417. vcpu->state.hdsisr = hdsisr;
  1418. }
  1419. }
  1420. static int get_exit_ids(uint64_t srr0, uint16_t ids[16])
  1421. {
  1422. int nr;
  1423. switch (srr0) {
  1424. case 0xc00:
  1425. nr = 10;
  1426. ids[0] = GSB_VCPU_GPR3;
  1427. ids[1] = GSB_VCPU_GPR4;
  1428. ids[2] = GSB_VCPU_GPR5;
  1429. ids[3] = GSB_VCPU_GPR6;
  1430. ids[4] = GSB_VCPU_GPR7;
  1431. ids[5] = GSB_VCPU_GPR8;
  1432. ids[6] = GSB_VCPU_GPR9;
  1433. ids[7] = GSB_VCPU_GPR10;
  1434. ids[8] = GSB_VCPU_GPR11;
  1435. ids[9] = GSB_VCPU_GPR12;
  1436. break;
  1437. case 0xe00:
  1438. nr = 5;
  1439. ids[0] = GSB_VCPU_SPR_HDAR;
  1440. ids[1] = GSB_VCPU_SPR_HDSISR;
  1441. ids[2] = GSB_VCPU_SPR_ASDR;
  1442. ids[3] = GSB_VCPU_SPR_NIA;
  1443. ids[4] = GSB_VCPU_SPR_MSR;
  1444. break;
  1445. case 0xe20:
  1446. nr = 4;
  1447. ids[0] = GSB_VCPU_SPR_HDAR;
  1448. ids[1] = GSB_VCPU_SPR_ASDR;
  1449. ids[2] = GSB_VCPU_SPR_NIA;
  1450. ids[3] = GSB_VCPU_SPR_MSR;
  1451. break;
  1452. case 0xe40:
  1453. nr = 3;
  1454. ids[0] = GSB_VCPU_SPR_HEIR;
  1455. ids[1] = GSB_VCPU_SPR_NIA;
  1456. ids[2] = GSB_VCPU_SPR_MSR;
  1457. break;
  1458. case 0xf80:
  1459. nr = 3;
  1460. ids[0] = GSB_VCPU_SPR_HFSCR;
  1461. ids[1] = GSB_VCPU_SPR_NIA;
  1462. ids[2] = GSB_VCPU_SPR_MSR;
  1463. break;
  1464. default:
  1465. nr = 0;
  1466. break;
  1467. }
  1468. return nr;
  1469. }
  1470. static void exit_process_output_buffer(SpaprMachineState *spapr,
  1471. PowerPCCPU *cpu,
  1472. SpaprMachineStateNestedGuest *guest,
  1473. target_ulong vcpuid,
  1474. target_ulong *r3)
  1475. {
  1476. SpaprMachineStateNestedGuestVcpu *vcpu = &guest->vcpus[vcpuid];
  1477. struct guest_state_request gsr;
  1478. struct guest_state_buffer *gsb;
  1479. struct guest_state_element *element;
  1480. struct guest_state_element_type *type;
  1481. int exit_id_count = 0;
  1482. uint16_t exit_cause_ids[16];
  1483. hwaddr len;
  1484. len = vcpu->runbufout.size;
  1485. gsb = address_space_map(CPU(cpu)->as, vcpu->runbufout.addr, &len, true,
  1486. MEMTXATTRS_UNSPECIFIED);
  1487. if (!gsb || len != vcpu->runbufout.size) {
  1488. address_space_unmap(CPU(cpu)->as, gsb, len, true, len);
  1489. *r3 = H_P2;
  1490. return;
  1491. }
  1492. exit_id_count = get_exit_ids(*r3, exit_cause_ids);
  1493. /* Create a buffer of elements to send back */
  1494. gsb->num_elements = cpu_to_be32(exit_id_count);
  1495. element = gsb->elements;
  1496. for (int i = 0; i < exit_id_count; i++) {
  1497. type = guest_state_element_type_find(exit_cause_ids[i]);
  1498. assert(type);
  1499. element->id = cpu_to_be16(exit_cause_ids[i]);
  1500. element->size = cpu_to_be16(type->size);
  1501. element = guest_state_element_next(element, NULL, NULL);
  1502. }
  1503. gsr.gsb = gsb;
  1504. gsr.len = VCPU_OUT_BUF_MIN_SZ;
  1505. gsr.flags = 0; /* get + never guest wide */
  1506. getset_state(spapr, guest, vcpuid, &gsr);
  1507. address_space_unmap(CPU(cpu)->as, gsb, len, true, len);
  1508. return;
  1509. }
  1510. static
  1511. void spapr_exit_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, int excp)
  1512. {
  1513. CPUPPCState *env = &cpu->env;
  1514. CPUState *cs = CPU(cpu);
  1515. SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  1516. target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */
  1517. target_ulong lpid = 0, vcpuid = 0;
  1518. struct SpaprMachineStateNestedGuestVcpu *vcpu = NULL;
  1519. struct SpaprMachineStateNestedGuest *guest = NULL;
  1520. lpid = spapr_cpu->nested_host_state->gpr[5];
  1521. vcpuid = spapr_cpu->nested_host_state->gpr[6];
  1522. guest = spapr_get_nested_guest(spapr, lpid);
  1523. assert(guest);
  1524. spapr_nested_vcpu_check(guest, vcpuid, false);
  1525. vcpu = &guest->vcpus[vcpuid];
  1526. exit_nested_store_l2(cpu, excp, vcpu);
  1527. /* do the output buffer for run_vcpu*/
  1528. exit_process_output_buffer(spapr, cpu, guest, vcpuid, &r3_return);
  1529. assert(env->spr[SPR_LPIDR] != 0);
  1530. nested_load_state(cpu, spapr_cpu->nested_host_state);
  1531. cpu_ppc_decrease_tb_by_offset(env, vcpu->tb_offset);
  1532. env->gpr[3] = H_SUCCESS;
  1533. env->gpr[4] = r3_return;
  1534. nested_post_load_state(env, cs);
  1535. cpu_ppc_hdecr_exit(env);
  1536. spapr_cpu->in_nested = false;
  1537. g_free(spapr_cpu->nested_host_state);
  1538. spapr_cpu->nested_host_state = NULL;
  1539. }
  1540. void spapr_exit_nested(PowerPCCPU *cpu, int excp)
  1541. {
  1542. SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  1543. SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  1544. assert(spapr_cpu->in_nested);
  1545. if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
  1546. spapr_exit_nested_hv(cpu, excp);
  1547. } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
  1548. spapr_exit_nested_papr(spapr, cpu, excp);
  1549. } else {
  1550. g_assert_not_reached();
  1551. }
  1552. }
  1553. static void nested_papr_load_l2(PowerPCCPU *cpu,
  1554. CPUPPCState *env,
  1555. SpaprMachineStateNestedGuestVcpu *vcpu,
  1556. target_ulong now)
  1557. {
  1558. PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  1559. target_ulong lpcr, lpcr_mask, hdec;
  1560. lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER;
  1561. assert(vcpu);
  1562. assert(sizeof(env->gpr) == sizeof(vcpu->state.gpr));
  1563. nested_load_state(cpu, &vcpu->state);
  1564. lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) |
  1565. (vcpu->state.lpcr & lpcr_mask);
  1566. lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE;
  1567. lpcr &= ~LPCR_LPES0;
  1568. env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask;
  1569. hdec = vcpu->hdecr_expiry_tb - now;
  1570. cpu_ppc_store_decr(env, vcpu->state.dec_expiry_tb - now);
  1571. cpu_ppc_hdecr_init(env);
  1572. cpu_ppc_store_hdecr(env, hdec);
  1573. cpu_ppc_increase_tb_by_offset(env, vcpu->tb_offset);
  1574. }
  1575. static void nested_papr_run_vcpu(PowerPCCPU *cpu,
  1576. uint64_t lpid,
  1577. SpaprMachineStateNestedGuestVcpu *vcpu)
  1578. {
  1579. SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  1580. CPUPPCState *env = &cpu->env;
  1581. CPUState *cs = CPU(cpu);
  1582. SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  1583. target_ulong now = cpu_ppc_load_tbl(env);
  1584. assert(env->spr[SPR_LPIDR] == 0);
  1585. assert(spapr->nested.api); /* ensure API version is initialized */
  1586. spapr_cpu->nested_host_state = g_try_new(struct nested_ppc_state, 1);
  1587. assert(spapr_cpu->nested_host_state);
  1588. nested_save_state(spapr_cpu->nested_host_state, cpu);
  1589. spapr_cpu->nested_host_state->dec_expiry_tb = now - cpu_ppc_load_decr(env);
  1590. nested_papr_load_l2(cpu, env, vcpu, now);
  1591. env->spr[SPR_LPIDR] = lpid; /* post load l2 */
  1592. spapr_cpu->in_nested = true;
  1593. nested_post_load_state(env, cs);
  1594. }
  1595. static target_ulong h_guest_run_vcpu(PowerPCCPU *cpu,
  1596. SpaprMachineState *spapr,
  1597. target_ulong opcode,
  1598. target_ulong *args)
  1599. {
  1600. CPUPPCState *env = &cpu->env;
  1601. target_ulong flags = args[0];
  1602. target_ulong lpid = args[1];
  1603. target_ulong vcpuid = args[2];
  1604. struct SpaprMachineStateNestedGuestVcpu *vcpu;
  1605. struct guest_state_request gsr;
  1606. SpaprMachineStateNestedGuest *guest;
  1607. target_ulong rc;
  1608. if (flags) /* don't handle any flags for now */
  1609. return H_PARAMETER;
  1610. guest = spapr_get_nested_guest(spapr, lpid);
  1611. if (!guest) {
  1612. return H_P2;
  1613. }
  1614. if (!spapr_nested_vcpu_check(guest, vcpuid, true)) {
  1615. return H_P3;
  1616. }
  1617. if (guest->parttbl[0] == 0) {
  1618. /* At least need a partition scoped radix tree */
  1619. return H_NOT_AVAILABLE;
  1620. }
  1621. vcpu = &guest->vcpus[vcpuid];
  1622. /* Read run_vcpu input buffer to update state */
  1623. gsr.buf = vcpu->runbufin.addr;
  1624. gsr.len = vcpu->runbufin.size;
  1625. gsr.flags = GUEST_STATE_REQUEST_SET; /* Thread wide + writing */
  1626. rc = map_and_getset_state(cpu, spapr, guest, vcpuid, &gsr);
  1627. if (rc == H_SUCCESS) {
  1628. nested_papr_run_vcpu(cpu, lpid, vcpu);
  1629. } else {
  1630. env->gpr[3] = rc;
  1631. }
  1632. return env->gpr[3];
  1633. }
  1634. void spapr_register_nested_hv(void)
  1635. {
  1636. spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
  1637. spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
  1638. spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
  1639. spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
  1640. }
  1641. void spapr_unregister_nested_hv(void)
  1642. {
  1643. spapr_unregister_hypercall(KVMPPC_H_SET_PARTITION_TABLE);
  1644. spapr_unregister_hypercall(KVMPPC_H_ENTER_NESTED);
  1645. spapr_unregister_hypercall(KVMPPC_H_TLB_INVALIDATE);
  1646. spapr_unregister_hypercall(KVMPPC_H_COPY_TOFROM_GUEST);
  1647. }
  1648. void spapr_register_nested_papr(void)
  1649. {
  1650. spapr_register_hypercall(H_GUEST_GET_CAPABILITIES,
  1651. h_guest_get_capabilities);
  1652. spapr_register_hypercall(H_GUEST_SET_CAPABILITIES,
  1653. h_guest_set_capabilities);
  1654. spapr_register_hypercall(H_GUEST_CREATE, h_guest_create);
  1655. spapr_register_hypercall(H_GUEST_DELETE, h_guest_delete);
  1656. spapr_register_hypercall(H_GUEST_CREATE_VCPU, h_guest_create_vcpu);
  1657. spapr_register_hypercall(H_GUEST_SET_STATE, h_guest_set_state);
  1658. spapr_register_hypercall(H_GUEST_GET_STATE, h_guest_get_state);
  1659. spapr_register_hypercall(H_GUEST_RUN_VCPU, h_guest_run_vcpu);
  1660. }
  1661. void spapr_unregister_nested_papr(void)
  1662. {
  1663. spapr_unregister_hypercall(H_GUEST_GET_CAPABILITIES);
  1664. spapr_unregister_hypercall(H_GUEST_SET_CAPABILITIES);
  1665. spapr_unregister_hypercall(H_GUEST_CREATE);
  1666. spapr_unregister_hypercall(H_GUEST_DELETE);
  1667. spapr_unregister_hypercall(H_GUEST_CREATE_VCPU);
  1668. spapr_unregister_hypercall(H_GUEST_SET_STATE);
  1669. spapr_unregister_hypercall(H_GUEST_GET_STATE);
  1670. spapr_unregister_hypercall(H_GUEST_RUN_VCPU);
  1671. }
  1672. #else
  1673. void spapr_exit_nested(PowerPCCPU *cpu, int excp)
  1674. {
  1675. g_assert_not_reached();
  1676. }
  1677. void spapr_register_nested_hv(void)
  1678. {
  1679. /* DO NOTHING */
  1680. }
  1681. void spapr_unregister_nested_hv(void)
  1682. {
  1683. /* DO NOTHING */
  1684. }
  1685. bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
  1686. target_ulong lpid, ppc_v3_pate_t *entry)
  1687. {
  1688. return false;
  1689. }
  1690. bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu,
  1691. target_ulong lpid, ppc_v3_pate_t *entry)
  1692. {
  1693. return false;
  1694. }
  1695. void spapr_register_nested_papr(void)
  1696. {
  1697. /* DO NOTHING */
  1698. }
  1699. void spapr_unregister_nested_papr(void)
  1700. {
  1701. /* DO NOTHING */
  1702. }
  1703. void spapr_nested_gsb_init(void)
  1704. {
  1705. /* DO NOTHING */
  1706. }
  1707. #endif