2
0

virt_ctrl.c 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150
  1. /*
  2. * SPDX-License-Identifier: GPL-2.0-or-later
  3. *
  4. * Virt system Controller
  5. */
  6. #include "qemu/osdep.h"
  7. #include "hw/qdev-properties.h"
  8. #include "hw/sysbus.h"
  9. #include "migration/vmstate.h"
  10. #include "qemu/log.h"
  11. #include "trace.h"
  12. #include "system/runstate.h"
  13. #include "hw/misc/virt_ctrl.h"
  14. enum {
  15. REG_FEATURES = 0x00,
  16. REG_CMD = 0x04,
  17. };
  18. #define FEAT_POWER_CTRL 0x00000001
  19. enum {
  20. CMD_NOOP,
  21. CMD_RESET,
  22. CMD_HALT,
  23. CMD_PANIC,
  24. };
  25. static uint64_t virt_ctrl_read(void *opaque, hwaddr addr, unsigned size)
  26. {
  27. VirtCtrlState *s = opaque;
  28. uint64_t value = 0;
  29. switch (addr) {
  30. case REG_FEATURES:
  31. value = FEAT_POWER_CTRL;
  32. break;
  33. default:
  34. qemu_log_mask(LOG_UNIMP,
  35. "%s: unimplemented register read 0x%02"HWADDR_PRIx"\n",
  36. __func__, addr);
  37. break;
  38. }
  39. trace_virt_ctrl_write(s, addr, size, value);
  40. return value;
  41. }
  42. static void virt_ctrl_write(void *opaque, hwaddr addr, uint64_t value,
  43. unsigned size)
  44. {
  45. VirtCtrlState *s = opaque;
  46. trace_virt_ctrl_write(s, addr, size, value);
  47. switch (addr) {
  48. case REG_CMD:
  49. switch (value) {
  50. case CMD_NOOP:
  51. break;
  52. case CMD_RESET:
  53. qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
  54. break;
  55. case CMD_HALT:
  56. qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  57. break;
  58. case CMD_PANIC:
  59. qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_PANIC);
  60. break;
  61. }
  62. break;
  63. default:
  64. qemu_log_mask(LOG_UNIMP,
  65. "%s: unimplemented register write 0x%02"HWADDR_PRIx"\n",
  66. __func__, addr);
  67. break;
  68. }
  69. }
  70. static const MemoryRegionOps virt_ctrl_ops = {
  71. .read = virt_ctrl_read,
  72. .write = virt_ctrl_write,
  73. .endianness = DEVICE_NATIVE_ENDIAN,
  74. .valid.max_access_size = 4,
  75. .impl.max_access_size = 4,
  76. };
  77. static void virt_ctrl_reset(DeviceState *dev)
  78. {
  79. VirtCtrlState *s = VIRT_CTRL(dev);
  80. trace_virt_ctrl_reset(s);
  81. }
  82. static void virt_ctrl_realize(DeviceState *dev, Error **errp)
  83. {
  84. VirtCtrlState *s = VIRT_CTRL(dev);
  85. trace_virt_ctrl_instance_init(s);
  86. memory_region_init_io(&s->iomem, OBJECT(s), &virt_ctrl_ops, s,
  87. "virt-ctrl", 0x100);
  88. }
  89. static const VMStateDescription vmstate_virt_ctrl = {
  90. .name = "virt-ctrl",
  91. .version_id = 1,
  92. .minimum_version_id = 1,
  93. .fields = (const VMStateField[]) {
  94. VMSTATE_UINT32(irq_enabled, VirtCtrlState),
  95. VMSTATE_END_OF_LIST()
  96. }
  97. };
  98. static void virt_ctrl_instance_init(Object *obj)
  99. {
  100. SysBusDevice *dev = SYS_BUS_DEVICE(obj);
  101. VirtCtrlState *s = VIRT_CTRL(obj);
  102. trace_virt_ctrl_instance_init(s);
  103. sysbus_init_mmio(dev, &s->iomem);
  104. sysbus_init_irq(dev, &s->irq);
  105. }
  106. static void virt_ctrl_class_init(ObjectClass *oc, void *data)
  107. {
  108. DeviceClass *dc = DEVICE_CLASS(oc);
  109. device_class_set_legacy_reset(dc, virt_ctrl_reset);
  110. dc->realize = virt_ctrl_realize;
  111. dc->vmsd = &vmstate_virt_ctrl;
  112. }
  113. static const TypeInfo virt_ctrl_info = {
  114. .name = TYPE_VIRT_CTRL,
  115. .parent = TYPE_SYS_BUS_DEVICE,
  116. .class_init = virt_ctrl_class_init,
  117. .instance_init = virt_ctrl_instance_init,
  118. .instance_size = sizeof(VirtCtrlState),
  119. };
  120. static void virt_ctrl_register_types(void)
  121. {
  122. type_register_static(&virt_ctrl_info);
  123. }
  124. type_init(virt_ctrl_register_types)