macio.c 17 KB

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  1. /*
  2. * PowerMac MacIO device emulation
  3. *
  4. * Copyright (c) 2005-2007 Fabrice Bellard
  5. * Copyright (c) 2007 Jocelyn Mayer
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy
  8. * of this software and associated documentation files (the "Software"), to deal
  9. * in the Software without restriction, including without limitation the rights
  10. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11. * copies of the Software, and to permit persons to whom the Software is
  12. * furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23. * THE SOFTWARE.
  24. */
  25. #include "qemu/osdep.h"
  26. #include "qapi/error.h"
  27. #include "qemu/module.h"
  28. #include "hw/misc/macio/cuda.h"
  29. #include "hw/pci/pci.h"
  30. #include "hw/ppc/mac_dbdma.h"
  31. #include "hw/qdev-properties.h"
  32. #include "migration/vmstate.h"
  33. #include "hw/char/escc.h"
  34. #include "hw/misc/macio/macio.h"
  35. #include "hw/intc/heathrow_pic.h"
  36. #include "trace.h"
  37. #define ESCC_CLOCK 3686400
  38. /* Note: this code is strongly inspired by the corresponding code in PearPC */
  39. /*
  40. * The mac-io has two interfaces to the ESCC. One is called "escc-legacy",
  41. * while the other one is the normal, current ESCC interface.
  42. *
  43. * The magic below creates memory aliases to spawn the escc-legacy device
  44. * purely by rerouting the respective registers to our escc region. This
  45. * works because the only difference between the two memory regions is the
  46. * register layout, not their semantics.
  47. *
  48. * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
  49. */
  50. static void macio_escc_legacy_setup(MacIOState *s)
  51. {
  52. SysBusDevice *sbd = SYS_BUS_DEVICE(&s->escc);
  53. MemoryRegion *escc_legacy = g_new(MemoryRegion, 1);
  54. int i;
  55. static const int maps[] = {
  56. 0x00, 0x00, /* Command B */
  57. 0x02, 0x20, /* Command A */
  58. 0x04, 0x10, /* Data B */
  59. 0x06, 0x30, /* Data A */
  60. 0x08, 0x40, /* Enhancement B */
  61. 0x0A, 0x50, /* Enhancement A */
  62. 0x80, 0x80, /* Recovery count */
  63. 0x90, 0x90, /* Start A */
  64. 0xa0, 0xa0, /* Start B */
  65. 0xb0, 0xb0, /* Detect AB */
  66. };
  67. memory_region_init(escc_legacy, OBJECT(s), "escc-legacy", 256);
  68. for (i = 0; i < ARRAY_SIZE(maps); i += 2) {
  69. MemoryRegion *port = g_new(MemoryRegion, 1);
  70. memory_region_init_alias(port, OBJECT(s), "escc-legacy-port",
  71. sysbus_mmio_get_region(sbd, 0),
  72. maps[i + 1], 0x2);
  73. memory_region_add_subregion(escc_legacy, maps[i], port);
  74. }
  75. memory_region_add_subregion(&s->bar, 0x12000, escc_legacy);
  76. }
  77. static void macio_bar_setup(MacIOState *s)
  78. {
  79. SysBusDevice *sbd = SYS_BUS_DEVICE(&s->escc);
  80. MemoryRegion *bar = sysbus_mmio_get_region(sbd, 0);
  81. memory_region_add_subregion(&s->bar, 0x13000, bar);
  82. macio_escc_legacy_setup(s);
  83. }
  84. static bool macio_common_realize(PCIDevice *d, Error **errp)
  85. {
  86. MacIOState *s = MACIO(d);
  87. SysBusDevice *sbd;
  88. if (!qdev_realize(DEVICE(&s->dbdma), BUS(&s->macio_bus), errp)) {
  89. return false;
  90. }
  91. sbd = SYS_BUS_DEVICE(&s->dbdma);
  92. memory_region_add_subregion(&s->bar, 0x08000,
  93. sysbus_mmio_get_region(sbd, 0));
  94. if (!qdev_realize(DEVICE(&s->screamer), BUS(&s->macio_bus), errp)) {
  95. return false;
  96. }
  97. sbd = SYS_BUS_DEVICE(&s->screamer);
  98. memory_region_add_subregion(&s->bar, 0x14000,
  99. sysbus_mmio_get_region(sbd, 0));
  100. qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0);
  101. qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK);
  102. qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4);
  103. qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial);
  104. qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial);
  105. if (!qdev_realize(DEVICE(&s->escc), BUS(&s->macio_bus), errp)) {
  106. return false;
  107. }
  108. macio_bar_setup(s);
  109. pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
  110. return true;
  111. }
  112. static bool macio_realize_ide(MacIOState *s, MACIOIDEState *ide,
  113. qemu_irq irq0, qemu_irq irq1, int dmaid,
  114. Error **errp)
  115. {
  116. SysBusDevice *sbd = SYS_BUS_DEVICE(ide);
  117. qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid);
  118. object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma),
  119. &error_abort);
  120. macio_ide_register_dma(ide);
  121. if (!qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp)) {
  122. return false;
  123. }
  124. sysbus_connect_irq(sbd, 0, irq0);
  125. sysbus_connect_irq(sbd, 1, irq1);
  126. return true;
  127. }
  128. static void macio_oldworld_realize(PCIDevice *d, Error **errp)
  129. {
  130. MacIOState *s = MACIO(d);
  131. OldWorldMacIOState *os = OLDWORLD_MACIO(d);
  132. DeviceState *pic_dev = DEVICE(&os->pic);
  133. SysBusDevice *sbd;
  134. if (!macio_common_realize(d, errp)) {
  135. return;
  136. }
  137. /* Heathrow PIC */
  138. if (!qdev_realize(DEVICE(&os->pic), BUS(&s->macio_bus), errp)) {
  139. return;
  140. }
  141. sbd = SYS_BUS_DEVICE(&os->pic);
  142. memory_region_add_subregion(&s->bar, 0x0,
  143. sysbus_mmio_get_region(sbd, 0));
  144. qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
  145. s->frequency);
  146. if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) {
  147. return;
  148. }
  149. sbd = SYS_BUS_DEVICE(&s->cuda);
  150. memory_region_add_subregion(&s->bar, 0x16000,
  151. sysbus_mmio_get_region(sbd, 0));
  152. sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, OLDWORLD_CUDA_IRQ));
  153. sbd = SYS_BUS_DEVICE(&s->escc);
  154. sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCB_IRQ));
  155. sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCA_IRQ));
  156. if (!qdev_realize(DEVICE(&os->nvram), BUS(&s->macio_bus), errp)) {
  157. return;
  158. }
  159. sbd = SYS_BUS_DEVICE(&os->nvram);
  160. memory_region_add_subregion(&s->bar, 0x60000,
  161. sysbus_mmio_get_region(sbd, 0));
  162. pmac_format_nvram_partition(&os->nvram, os->nvram.size);
  163. /* IDE buses */
  164. if (!macio_realize_ide(s, &os->ide[0],
  165. qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ),
  166. qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ),
  167. 0x16, errp)) {
  168. return;
  169. }
  170. if (!macio_realize_ide(s, &os->ide[1],
  171. qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ),
  172. qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ),
  173. 0x1a, errp)) {
  174. return;
  175. }
  176. /* Screamer */
  177. sbd = SYS_BUS_DEVICE(&s->screamer);
  178. sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, OLDWORLD_SCREAMER_TX_IRQ));
  179. sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(pic_dev, OLDWORLD_SCREAMER_TX_DMA_IRQ));
  180. sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(pic_dev, OLDWORLD_SCREAMER_RX_IRQ));
  181. macio_screamer_register_dma(SCREAMER(sbd), &s->dbdma, 0x10, 0x12);
  182. }
  183. static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, int index)
  184. {
  185. gchar *name = g_strdup_printf("ide[%i]", index);
  186. uint32_t addr = 0x1f000 + ((index + 1) * 0x1000);
  187. object_initialize_child(OBJECT(s), name, ide, TYPE_MACIO_IDE);
  188. qdev_prop_set_uint32(DEVICE(ide), "addr", addr);
  189. memory_region_add_subregion(&s->bar, addr, &ide->mem);
  190. g_free(name);
  191. }
  192. static void macio_oldworld_init(Object *obj)
  193. {
  194. MacIOState *s = MACIO(obj);
  195. OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
  196. DeviceState *dev;
  197. int i;
  198. object_initialize_child(obj, "pic", &os->pic, TYPE_HEATHROW);
  199. object_initialize_child(obj, "cuda", &s->cuda, TYPE_CUDA);
  200. object_initialize_child(obj, "nvram", &os->nvram, TYPE_MACIO_NVRAM);
  201. dev = DEVICE(&os->nvram);
  202. qdev_prop_set_uint32(dev, "size", MACIO_NVRAM_SIZE);
  203. qdev_prop_set_uint32(dev, "it_shift", 4);
  204. for (i = 0; i < 2; i++) {
  205. macio_init_ide(s, &os->ide[i], i);
  206. }
  207. }
  208. static void timer_write(void *opaque, hwaddr addr, uint64_t value,
  209. unsigned size)
  210. {
  211. trace_macio_timer_write(addr, size, value);
  212. }
  213. static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
  214. {
  215. uint32_t value = 0;
  216. uint64_t systime = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  217. uint64_t kltime;
  218. kltime = muldiv64(systime, 4194300, NANOSECONDS_PER_SECOND * 4);
  219. kltime = muldiv64(kltime, 18432000, 1048575);
  220. switch (addr) {
  221. case 0x38:
  222. value = kltime;
  223. break;
  224. case 0x3c:
  225. value = kltime >> 32;
  226. break;
  227. }
  228. trace_macio_timer_read(addr, size, value);
  229. return value;
  230. }
  231. static const MemoryRegionOps timer_ops = {
  232. .read = timer_read,
  233. .write = timer_write,
  234. .endianness = DEVICE_LITTLE_ENDIAN,
  235. };
  236. static void macio_newworld_realize(PCIDevice *d, Error **errp)
  237. {
  238. MacIOState *s = MACIO(d);
  239. NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
  240. DeviceState *pic_dev = DEVICE(&ns->pic);
  241. SysBusDevice *sbd;
  242. MemoryRegion *timer_memory = NULL;
  243. if (!macio_common_realize(d, errp)) {
  244. return;
  245. }
  246. /* OpenPIC */
  247. qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
  248. sbd = SYS_BUS_DEVICE(&ns->pic);
  249. sysbus_realize_and_unref(sbd, &error_fatal);
  250. memory_region_add_subregion(&s->bar, 0x40000,
  251. sysbus_mmio_get_region(sbd, 0));
  252. sbd = SYS_BUS_DEVICE(&s->escc);
  253. sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, NEWWORLD_ESCCB_IRQ));
  254. sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(pic_dev, NEWWORLD_ESCCA_IRQ));
  255. /* IDE buses */
  256. if (!macio_realize_ide(s, &ns->ide[0],
  257. qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_IRQ),
  258. qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_DMA_IRQ),
  259. 0x16, errp)) {
  260. return;
  261. }
  262. if (!macio_realize_ide(s, &ns->ide[1],
  263. qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_IRQ),
  264. qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_DMA_IRQ),
  265. 0x1a, errp)) {
  266. return;
  267. }
  268. /* Timer */
  269. timer_memory = g_new(MemoryRegion, 1);
  270. memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer",
  271. 0x1000);
  272. memory_region_add_subregion(&s->bar, 0x15000, timer_memory);
  273. if (ns->has_pmu) {
  274. /* GPIOs */
  275. if (!qdev_realize(DEVICE(&ns->gpio), BUS(&s->macio_bus), errp)) {
  276. return;
  277. }
  278. sbd = SYS_BUS_DEVICE(&ns->gpio);
  279. sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(pic_dev,
  280. NEWWORLD_EXTING_GPIO1));
  281. sysbus_connect_irq(sbd, 9, qdev_get_gpio_in(pic_dev,
  282. NEWWORLD_EXTING_GPIO9));
  283. memory_region_add_subregion(&s->bar, 0x50,
  284. sysbus_mmio_get_region(sbd, 0));
  285. /* PMU */
  286. object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU);
  287. object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sbd),
  288. &error_abort);
  289. qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb);
  290. if (!qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), errp)) {
  291. return;
  292. }
  293. sbd = SYS_BUS_DEVICE(&s->pmu);
  294. sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, NEWWORLD_PMU_IRQ));
  295. memory_region_add_subregion(&s->bar, 0x16000,
  296. sysbus_mmio_get_region(sbd, 0));
  297. } else {
  298. object_unparent(OBJECT(&ns->gpio));
  299. /* CUDA */
  300. object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA);
  301. qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
  302. s->frequency);
  303. if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) {
  304. return;
  305. }
  306. sbd = SYS_BUS_DEVICE(&s->cuda);
  307. sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, NEWWORLD_CUDA_IRQ));
  308. memory_region_add_subregion(&s->bar, 0x16000,
  309. sysbus_mmio_get_region(sbd, 0));
  310. }
  311. /* Screamer */
  312. sbd = SYS_BUS_DEVICE(&s->screamer);
  313. sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, NEWWORLD_SCREAMER_IRQ));
  314. sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(pic_dev, NEWWORLD_SCREAMER_DMA_IRQ));
  315. sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(pic_dev, NEWWORLD_SCREAMER_RX_IRQ));
  316. macio_screamer_register_dma(SCREAMER(sbd), &s->dbdma, 0x10, 0x12);
  317. }
  318. static void macio_newworld_init(Object *obj)
  319. {
  320. MacIOState *s = MACIO(obj);
  321. NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
  322. int i;
  323. object_initialize_child(obj, "pic", &ns->pic, TYPE_OPENPIC);
  324. object_initialize_child(obj, "gpio", &ns->gpio, TYPE_MACIO_GPIO);
  325. for (i = 0; i < 2; i++) {
  326. macio_init_ide(s, &ns->ide[i], i);
  327. }
  328. }
  329. static void macio_instance_init(Object *obj)
  330. {
  331. MacIOState *s = MACIO(obj);
  332. memory_region_init(&s->bar, obj, "macio", 0x80000);
  333. qbus_init(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
  334. DEVICE(obj), "macio.0");
  335. object_initialize_child(obj, "dbdma", &s->dbdma, TYPE_MAC_DBDMA);
  336. object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC);
  337. object_initialize_child(obj, "screamer", &s->screamer, TYPE_SCREAMER);
  338. }
  339. static const VMStateDescription vmstate_macio_oldworld = {
  340. .name = "macio-oldworld",
  341. .version_id = 0,
  342. .minimum_version_id = 0,
  343. .fields = (const VMStateField[]) {
  344. VMSTATE_PCI_DEVICE(parent_obj.parent, OldWorldMacIOState),
  345. VMSTATE_END_OF_LIST()
  346. }
  347. };
  348. static void macio_oldworld_class_init(ObjectClass *oc, void *data)
  349. {
  350. PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
  351. DeviceClass *dc = DEVICE_CLASS(oc);
  352. pdc->realize = macio_oldworld_realize;
  353. pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201;
  354. dc->vmsd = &vmstate_macio_oldworld;
  355. }
  356. static const VMStateDescription vmstate_macio_newworld = {
  357. .name = "macio-newworld",
  358. .version_id = 0,
  359. .minimum_version_id = 0,
  360. .fields = (const VMStateField[]) {
  361. VMSTATE_PCI_DEVICE(parent_obj.parent, NewWorldMacIOState),
  362. VMSTATE_END_OF_LIST()
  363. }
  364. };
  365. static const Property macio_newworld_properties[] = {
  366. DEFINE_PROP_BOOL("has-pmu", NewWorldMacIOState, has_pmu, false),
  367. DEFINE_PROP_BOOL("has-adb", NewWorldMacIOState, has_adb, false),
  368. };
  369. static void macio_newworld_class_init(ObjectClass *oc, void *data)
  370. {
  371. PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
  372. DeviceClass *dc = DEVICE_CLASS(oc);
  373. pdc->realize = macio_newworld_realize;
  374. pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL;
  375. dc->vmsd = &vmstate_macio_newworld;
  376. device_class_set_props(dc, macio_newworld_properties);
  377. }
  378. static const Property macio_properties[] = {
  379. DEFINE_PROP_UINT64("frequency", MacIOState, frequency, 0),
  380. };
  381. static void macio_class_init(ObjectClass *klass, void *data)
  382. {
  383. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  384. DeviceClass *dc = DEVICE_CLASS(klass);
  385. k->vendor_id = PCI_VENDOR_ID_APPLE;
  386. k->class_id = PCI_CLASS_OTHERS << 8;
  387. device_class_set_props(dc, macio_properties);
  388. set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
  389. }
  390. static const TypeInfo macio_bus_info = {
  391. .name = TYPE_MACIO_BUS,
  392. .parent = TYPE_SYSTEM_BUS,
  393. .instance_size = sizeof(MacIOBusState),
  394. };
  395. static const TypeInfo macio_oldworld_type_info = {
  396. .name = TYPE_OLDWORLD_MACIO,
  397. .parent = TYPE_MACIO,
  398. .instance_size = sizeof(OldWorldMacIOState),
  399. .instance_init = macio_oldworld_init,
  400. .class_init = macio_oldworld_class_init,
  401. };
  402. static const TypeInfo macio_newworld_type_info = {
  403. .name = TYPE_NEWWORLD_MACIO,
  404. .parent = TYPE_MACIO,
  405. .instance_size = sizeof(NewWorldMacIOState),
  406. .instance_init = macio_newworld_init,
  407. .class_init = macio_newworld_class_init,
  408. };
  409. static const TypeInfo macio_type_info = {
  410. .name = TYPE_MACIO,
  411. .parent = TYPE_PCI_DEVICE,
  412. .instance_size = sizeof(MacIOState),
  413. .instance_init = macio_instance_init,
  414. .abstract = true,
  415. .class_init = macio_class_init,
  416. .interfaces = (InterfaceInfo[]) {
  417. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  418. { },
  419. },
  420. };
  421. static void macio_register_types(void)
  422. {
  423. type_register_static(&macio_bus_info);
  424. type_register_static(&macio_type_info);
  425. type_register_static(&macio_oldworld_type_info);
  426. type_register_static(&macio_newworld_type_info);
  427. }
  428. type_init(macio_register_types)