imx8mp_ccm.c 4.6 KB

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  1. /*
  2. * Copyright (c) 2025 Bernhard Beschow <shentey@gmail.com>
  3. *
  4. * i.MX 8M Plus CCM IP block emulation code
  5. *
  6. * Based on hw/misc/imx7_ccm.c
  7. *
  8. * SPDX-License-Identifier: GPL-2.0-or-later
  9. */
  10. #include "qemu/osdep.h"
  11. #include "qemu/log.h"
  12. #include "hw/misc/imx8mp_ccm.h"
  13. #include "migration/vmstate.h"
  14. #include "trace.h"
  15. #define CKIH_FREQ 16000000 /* 16MHz crystal input */
  16. static void imx8mp_ccm_reset(DeviceState *dev)
  17. {
  18. IMX8MPCCMState *s = IMX8MP_CCM(dev);
  19. memset(s->ccm, 0, sizeof(s->ccm));
  20. }
  21. #define CCM_INDEX(offset) (((offset) & ~(hwaddr)0xF) / sizeof(uint32_t))
  22. #define CCM_BITOP(offset) ((offset) & (hwaddr)0xF)
  23. enum {
  24. CCM_BITOP_NONE = 0x00,
  25. CCM_BITOP_SET = 0x04,
  26. CCM_BITOP_CLR = 0x08,
  27. CCM_BITOP_TOG = 0x0C,
  28. };
  29. static uint64_t imx8mp_set_clr_tog_read(void *opaque, hwaddr offset,
  30. unsigned size)
  31. {
  32. const uint32_t *mmio = opaque;
  33. return mmio[CCM_INDEX(offset)];
  34. }
  35. static void imx8mp_set_clr_tog_write(void *opaque, hwaddr offset,
  36. uint64_t value, unsigned size)
  37. {
  38. const uint8_t bitop = CCM_BITOP(offset);
  39. const uint32_t index = CCM_INDEX(offset);
  40. uint32_t *mmio = opaque;
  41. switch (bitop) {
  42. case CCM_BITOP_NONE:
  43. mmio[index] = value;
  44. break;
  45. case CCM_BITOP_SET:
  46. mmio[index] |= value;
  47. break;
  48. case CCM_BITOP_CLR:
  49. mmio[index] &= ~value;
  50. break;
  51. case CCM_BITOP_TOG:
  52. mmio[index] ^= value;
  53. break;
  54. };
  55. }
  56. static const struct MemoryRegionOps imx8mp_set_clr_tog_ops = {
  57. .read = imx8mp_set_clr_tog_read,
  58. .write = imx8mp_set_clr_tog_write,
  59. .endianness = DEVICE_NATIVE_ENDIAN,
  60. .impl = {
  61. /*
  62. * Our device would not work correctly if the guest was doing
  63. * unaligned access. This might not be a limitation on the real
  64. * device but in practice there is no reason for a guest to access
  65. * this device unaligned.
  66. */
  67. .min_access_size = 4,
  68. .max_access_size = 4,
  69. .unaligned = false,
  70. },
  71. };
  72. static void imx8mp_ccm_init(Object *obj)
  73. {
  74. SysBusDevice *sd = SYS_BUS_DEVICE(obj);
  75. IMX8MPCCMState *s = IMX8MP_CCM(obj);
  76. memory_region_init_io(&s->iomem,
  77. obj,
  78. &imx8mp_set_clr_tog_ops,
  79. s->ccm,
  80. TYPE_IMX8MP_CCM ".ccm",
  81. sizeof(s->ccm));
  82. sysbus_init_mmio(sd, &s->iomem);
  83. }
  84. static const VMStateDescription imx8mp_ccm_vmstate = {
  85. .name = TYPE_IMX8MP_CCM,
  86. .version_id = 1,
  87. .minimum_version_id = 1,
  88. .fields = (const VMStateField[]) {
  89. VMSTATE_UINT32_ARRAY(ccm, IMX8MPCCMState, CCM_MAX),
  90. VMSTATE_END_OF_LIST()
  91. },
  92. };
  93. static uint32_t imx8mp_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
  94. {
  95. /*
  96. * This function is "consumed" by GPT emulation code. Some clocks
  97. * have fixed frequencies and we can provide requested frequency
  98. * easily. However for CCM provided clocks (like IPG) each GPT
  99. * timer can have its own clock root.
  100. * This means we need additional information when calling this
  101. * function to know the requester's identity.
  102. */
  103. uint32_t freq = 0;
  104. switch (clock) {
  105. case CLK_NONE:
  106. break;
  107. case CLK_32k:
  108. freq = CKIL_FREQ;
  109. break;
  110. case CLK_HIGH:
  111. freq = CKIH_FREQ;
  112. break;
  113. case CLK_IPG:
  114. case CLK_IPG_HIGH:
  115. /*
  116. * For now we don't have a way to figure out the device this
  117. * function is called for. Until then the IPG derived clocks
  118. * are left unimplemented.
  119. */
  120. qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Clock %d Not implemented\n",
  121. TYPE_IMX8MP_CCM, __func__, clock);
  122. break;
  123. default:
  124. qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
  125. TYPE_IMX8MP_CCM, __func__, clock);
  126. break;
  127. }
  128. trace_ccm_clock_freq(clock, freq);
  129. return freq;
  130. }
  131. static void imx8mp_ccm_class_init(ObjectClass *klass, void *data)
  132. {
  133. DeviceClass *dc = DEVICE_CLASS(klass);
  134. IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
  135. device_class_set_legacy_reset(dc, imx8mp_ccm_reset);
  136. dc->vmsd = &imx8mp_ccm_vmstate;
  137. dc->desc = "i.MX 8M Plus Clock Control Module";
  138. ccm->get_clock_frequency = imx8mp_ccm_get_clock_frequency;
  139. }
  140. static const TypeInfo imx8mp_ccm_types[] = {
  141. {
  142. .name = TYPE_IMX8MP_CCM,
  143. .parent = TYPE_IMX_CCM,
  144. .instance_size = sizeof(IMX8MPCCMState),
  145. .instance_init = imx8mp_ccm_init,
  146. .class_init = imx8mp_ccm_class_init,
  147. },
  148. };
  149. DEFINE_TYPES(imx8mp_ccm_types);