2
0

imx7_snvs.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167
  1. /*
  2. * IMX7 Secure Non-Volatile Storage
  3. *
  4. * Copyright (c) 2018, Impinj, Inc.
  5. *
  6. * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
  7. *
  8. * This work is licensed under the terms of the GNU GPL, version 2 or later.
  9. * See the COPYING file in the top-level directory.
  10. *
  11. * Bare minimum emulation code needed to support being able to shut
  12. * down linux guest gracefully.
  13. */
  14. #include "qemu/osdep.h"
  15. #include "qemu/bitops.h"
  16. #include "qemu/timer.h"
  17. #include "migration/vmstate.h"
  18. #include "hw/misc/imx7_snvs.h"
  19. #include "qemu/cutils.h"
  20. #include "qemu/module.h"
  21. #include "system/system.h"
  22. #include "system/rtc.h"
  23. #include "system/runstate.h"
  24. #include "trace.h"
  25. #define RTC_FREQ 32768ULL
  26. static const VMStateDescription vmstate_imx7_snvs = {
  27. .name = TYPE_IMX7_SNVS,
  28. .version_id = 1,
  29. .minimum_version_id = 1,
  30. .fields = (const VMStateField[]) {
  31. VMSTATE_UINT64(tick_offset, IMX7SNVSState),
  32. VMSTATE_UINT64(lpcr, IMX7SNVSState),
  33. VMSTATE_END_OF_LIST()
  34. }
  35. };
  36. static uint64_t imx7_snvs_get_count(IMX7SNVSState *s)
  37. {
  38. uint64_t ticks = muldiv64(qemu_clock_get_ns(rtc_clock), RTC_FREQ,
  39. NANOSECONDS_PER_SECOND);
  40. return s->tick_offset + ticks;
  41. }
  42. static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size)
  43. {
  44. IMX7SNVSState *s = IMX7_SNVS(opaque);
  45. uint64_t ret = 0;
  46. switch (offset) {
  47. case SNVS_LPSRTCMR:
  48. ret = extract64(imx7_snvs_get_count(s), 32, 15);
  49. break;
  50. case SNVS_LPSRTCLR:
  51. ret = extract64(imx7_snvs_get_count(s), 0, 32);
  52. break;
  53. case SNVS_LPCR:
  54. ret = s->lpcr;
  55. break;
  56. }
  57. trace_imx7_snvs_read(offset, ret, size);
  58. return ret;
  59. }
  60. static void imx7_snvs_reset(DeviceState *dev)
  61. {
  62. IMX7SNVSState *s = IMX7_SNVS(dev);
  63. s->lpcr = 0;
  64. }
  65. static void imx7_snvs_write(void *opaque, hwaddr offset,
  66. uint64_t v, unsigned size)
  67. {
  68. trace_imx7_snvs_write(offset, v, size);
  69. IMX7SNVSState *s = IMX7_SNVS(opaque);
  70. uint64_t new_value = 0, snvs_count = 0;
  71. if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) {
  72. snvs_count = imx7_snvs_get_count(s);
  73. }
  74. switch (offset) {
  75. case SNVS_LPSRTCMR:
  76. new_value = deposit64(snvs_count, 32, 32, v);
  77. break;
  78. case SNVS_LPSRTCLR:
  79. new_value = deposit64(snvs_count, 0, 32, v);
  80. break;
  81. case SNVS_LPCR: {
  82. s->lpcr = v;
  83. const uint32_t mask = SNVS_LPCR_TOP | SNVS_LPCR_DP_EN;
  84. if ((v & mask) == mask) {
  85. qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  86. }
  87. break;
  88. }
  89. }
  90. if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) {
  91. s->tick_offset += new_value - snvs_count;
  92. }
  93. }
  94. static const struct MemoryRegionOps imx7_snvs_ops = {
  95. .read = imx7_snvs_read,
  96. .write = imx7_snvs_write,
  97. .endianness = DEVICE_NATIVE_ENDIAN,
  98. .impl = {
  99. /*
  100. * Our device would not work correctly if the guest was doing
  101. * unaligned access. This might not be a limitation on the real
  102. * device but in practice there is no reason for a guest to access
  103. * this device unaligned.
  104. */
  105. .min_access_size = 4,
  106. .max_access_size = 4,
  107. .unaligned = false,
  108. },
  109. };
  110. static void imx7_snvs_init(Object *obj)
  111. {
  112. SysBusDevice *sd = SYS_BUS_DEVICE(obj);
  113. IMX7SNVSState *s = IMX7_SNVS(obj);
  114. struct tm tm;
  115. memory_region_init_io(&s->mmio, obj, &imx7_snvs_ops, s,
  116. TYPE_IMX7_SNVS, 0x1000);
  117. sysbus_init_mmio(sd, &s->mmio);
  118. qemu_get_timedate(&tm, 0);
  119. s->tick_offset = mktimegm(&tm) -
  120. qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
  121. }
  122. static void imx7_snvs_class_init(ObjectClass *klass, void *data)
  123. {
  124. DeviceClass *dc = DEVICE_CLASS(klass);
  125. device_class_set_legacy_reset(dc, imx7_snvs_reset);
  126. dc->vmsd = &vmstate_imx7_snvs;
  127. dc->desc = "i.MX7 Secure Non-Volatile Storage Module";
  128. }
  129. static const TypeInfo imx7_snvs_info = {
  130. .name = TYPE_IMX7_SNVS,
  131. .parent = TYPE_SYS_BUS_DEVICE,
  132. .instance_size = sizeof(IMX7SNVSState),
  133. .instance_init = imx7_snvs_init,
  134. .class_init = imx7_snvs_class_init,
  135. };
  136. static void imx7_snvs_register_type(void)
  137. {
  138. type_register_static(&imx7_snvs_info);
  139. }
  140. type_init(imx7_snvs_register_type)