vt82c686.c 27 KB

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  1. /*
  2. * VT82C686B south bridge support
  3. *
  4. * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
  5. * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
  6. * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
  7. * This code is licensed under the GNU GPL v2.
  8. *
  9. * Contributions after 2012-01-13 are licensed under the terms of the
  10. * GNU GPL, version 2 or (at your option) any later version.
  11. *
  12. * VT8231 south bridge support and general clean up to allow it
  13. * Copyright (c) 2018-2020 BALATON Zoltan
  14. */
  15. #include "qemu/osdep.h"
  16. #include "hw/isa/vt82c686.h"
  17. #include "hw/block/fdc.h"
  18. #include "hw/char/parallel-isa.h"
  19. #include "hw/char/serial-isa.h"
  20. #include "hw/pci/pci.h"
  21. #include "hw/qdev-properties.h"
  22. #include "hw/ide/pci.h"
  23. #include "hw/isa/isa.h"
  24. #include "hw/isa/superio.h"
  25. #include "hw/intc/i8259.h"
  26. #include "hw/irq.h"
  27. #include "hw/dma/i8257.h"
  28. #include "hw/usb/hcd-uhci.h"
  29. #include "hw/timer/i8254.h"
  30. #include "hw/rtc/mc146818rtc.h"
  31. #include "migration/vmstate.h"
  32. #include "hw/isa/apm.h"
  33. #include "hw/acpi/acpi.h"
  34. #include "hw/i2c/pm_smbus.h"
  35. #include "qapi/error.h"
  36. #include "qemu/log.h"
  37. #include "qemu/module.h"
  38. #include "qemu/range.h"
  39. #include "qemu/timer.h"
  40. #include "trace.h"
  41. #define TYPE_VIA_PM "via-pm"
  42. OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM)
  43. struct ViaPMState {
  44. PCIDevice dev;
  45. MemoryRegion io;
  46. ACPIREGS ar;
  47. APMState apm;
  48. PMSMBus smb;
  49. };
  50. static void pm_io_space_update(ViaPMState *s)
  51. {
  52. uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL;
  53. memory_region_transaction_begin();
  54. memory_region_set_address(&s->io, pmbase);
  55. memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7));
  56. memory_region_transaction_commit();
  57. }
  58. static void smb_io_space_update(ViaPMState *s)
  59. {
  60. uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL;
  61. memory_region_transaction_begin();
  62. memory_region_set_address(&s->smb.io, smbase);
  63. memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0));
  64. memory_region_transaction_commit();
  65. }
  66. static int vmstate_acpi_post_load(void *opaque, int version_id)
  67. {
  68. ViaPMState *s = opaque;
  69. pm_io_space_update(s);
  70. smb_io_space_update(s);
  71. return 0;
  72. }
  73. static const VMStateDescription vmstate_acpi = {
  74. .name = "vt82c686b_pm",
  75. .version_id = 1,
  76. .minimum_version_id = 1,
  77. .post_load = vmstate_acpi_post_load,
  78. .fields = (const VMStateField[]) {
  79. VMSTATE_PCI_DEVICE(dev, ViaPMState),
  80. VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState),
  81. VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState),
  82. VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState),
  83. VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState),
  84. VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState),
  85. VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState),
  86. VMSTATE_END_OF_LIST()
  87. }
  88. };
  89. static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
  90. {
  91. ViaPMState *s = VIA_PM(d);
  92. trace_via_pm_write(addr, val, len);
  93. pci_default_write_config(d, addr, val, len);
  94. if (ranges_overlap(addr, len, 0x48, 4)) {
  95. uint32_t v = pci_get_long(s->dev.config + 0x48);
  96. pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1);
  97. }
  98. if (range_covers_byte(addr, len, 0x41)) {
  99. pm_io_space_update(s);
  100. }
  101. if (ranges_overlap(addr, len, 0x90, 4)) {
  102. uint32_t v = pci_get_long(s->dev.config + 0x90);
  103. pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1);
  104. }
  105. if (range_covers_byte(addr, len, 0xd2)) {
  106. s->dev.config[0xd2] &= 0xf;
  107. smb_io_space_update(s);
  108. }
  109. }
  110. static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size)
  111. {
  112. trace_via_pm_io_write(addr, data, size);
  113. }
  114. static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size)
  115. {
  116. trace_via_pm_io_read(addr, 0, size);
  117. return 0;
  118. }
  119. static const MemoryRegionOps pm_io_ops = {
  120. .read = pm_io_read,
  121. .write = pm_io_write,
  122. .endianness = DEVICE_NATIVE_ENDIAN,
  123. .impl = {
  124. .min_access_size = 1,
  125. .max_access_size = 1,
  126. },
  127. };
  128. static void pm_update_sci(ViaPMState *s)
  129. {
  130. int sci_level, pmsts;
  131. pmsts = acpi_pm1_evt_get_sts(&s->ar);
  132. sci_level = (((pmsts & s->ar.pm1.evt.en) &
  133. (ACPI_BITMASK_RT_CLOCK_ENABLE |
  134. ACPI_BITMASK_POWER_BUTTON_ENABLE |
  135. ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  136. ACPI_BITMASK_TIMER_ENABLE)) != 0);
  137. if (pci_get_byte(s->dev.config + PCI_INTERRUPT_PIN)) {
  138. /*
  139. * FIXME:
  140. * Fix device model that realizes this PM device and remove
  141. * this work around.
  142. * The device model should wire SCI and setup
  143. * PCI_INTERRUPT_PIN properly.
  144. * If PIN# = 0(interrupt pin isn't used), don't raise SCI as
  145. * work around.
  146. */
  147. pci_set_irq(&s->dev, sci_level);
  148. }
  149. /* schedule a timer interruption if needed */
  150. acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
  151. !(pmsts & ACPI_BITMASK_TIMER_STATUS));
  152. }
  153. static void pm_tmr_timer(ACPIREGS *ar)
  154. {
  155. ViaPMState *s = container_of(ar, ViaPMState, ar);
  156. pm_update_sci(s);
  157. }
  158. static void via_pm_reset(DeviceState *d)
  159. {
  160. ViaPMState *s = VIA_PM(d);
  161. memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0,
  162. PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE);
  163. /* Power Management IO base */
  164. pci_set_long(s->dev.config + 0x48, 1);
  165. /* SMBus IO base */
  166. pci_set_long(s->dev.config + 0x90, 1);
  167. acpi_pm1_evt_reset(&s->ar);
  168. acpi_pm1_cnt_reset(&s->ar);
  169. acpi_pm_tmr_reset(&s->ar);
  170. pm_update_sci(s);
  171. pm_io_space_update(s);
  172. smb_io_space_update(s);
  173. }
  174. static void via_pm_realize(PCIDevice *dev, Error **errp)
  175. {
  176. ViaPMState *s = VIA_PM(dev);
  177. pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK |
  178. PCI_STATUS_DEVSEL_MEDIUM);
  179. pm_smbus_init(DEVICE(s), &s->smb, false);
  180. memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io);
  181. memory_region_set_enabled(&s->smb.io, false);
  182. apm_init(dev, &s->apm, NULL, s);
  183. memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128);
  184. memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io);
  185. memory_region_set_enabled(&s->io, false);
  186. acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
  187. acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
  188. acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false);
  189. }
  190. typedef struct via_pm_init_info {
  191. uint16_t device_id;
  192. } ViaPMInitInfo;
  193. static void via_pm_class_init(ObjectClass *klass, void *data)
  194. {
  195. DeviceClass *dc = DEVICE_CLASS(klass);
  196. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  197. const ViaPMInitInfo *info = data;
  198. k->realize = via_pm_realize;
  199. k->config_write = pm_write_config;
  200. k->vendor_id = PCI_VENDOR_ID_VIA;
  201. k->device_id = info->device_id;
  202. k->class_id = PCI_CLASS_BRIDGE_OTHER;
  203. k->revision = 0x40;
  204. device_class_set_legacy_reset(dc, via_pm_reset);
  205. /* Reason: part of VIA south bridge, does not exist stand alone */
  206. dc->user_creatable = false;
  207. dc->vmsd = &vmstate_acpi;
  208. }
  209. static const TypeInfo via_pm_info = {
  210. .name = TYPE_VIA_PM,
  211. .parent = TYPE_PCI_DEVICE,
  212. .instance_size = sizeof(ViaPMState),
  213. .abstract = true,
  214. .interfaces = (InterfaceInfo[]) {
  215. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  216. { },
  217. },
  218. };
  219. static const ViaPMInitInfo vt82c686b_pm_init_info = {
  220. .device_id = PCI_DEVICE_ID_VIA_82C686B_PM,
  221. };
  222. #define TYPE_VT82C686B_PM "vt82c686b-pm"
  223. static const TypeInfo vt82c686b_pm_info = {
  224. .name = TYPE_VT82C686B_PM,
  225. .parent = TYPE_VIA_PM,
  226. .class_init = via_pm_class_init,
  227. .class_data = (void *)&vt82c686b_pm_init_info,
  228. };
  229. static const ViaPMInitInfo vt8231_pm_init_info = {
  230. .device_id = PCI_DEVICE_ID_VIA_8231_PM,
  231. };
  232. #define TYPE_VT8231_PM "vt8231-pm"
  233. static const TypeInfo vt8231_pm_info = {
  234. .name = TYPE_VT8231_PM,
  235. .parent = TYPE_VIA_PM,
  236. .class_init = via_pm_class_init,
  237. .class_data = (void *)&vt8231_pm_init_info,
  238. };
  239. #define TYPE_VIA_SUPERIO "via-superio"
  240. OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO)
  241. struct ViaSuperIOState {
  242. ISASuperIODevice superio;
  243. uint8_t regs[0x100];
  244. const MemoryRegionOps *io_ops;
  245. MemoryRegion io;
  246. };
  247. static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable)
  248. {
  249. memory_region_set_enabled(&s->io, enable);
  250. }
  251. static void via_superio_realize(DeviceState *d, Error **errp)
  252. {
  253. ViaSuperIOState *s = VIA_SUPERIO(d);
  254. ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s);
  255. Error *local_err = NULL;
  256. assert(s->io_ops);
  257. ic->parent_realize(d, &local_err);
  258. if (local_err) {
  259. error_propagate(errp, local_err);
  260. return;
  261. }
  262. memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2);
  263. memory_region_set_enabled(&s->io, false);
  264. /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */
  265. memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0,
  266. &s->io);
  267. }
  268. static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
  269. {
  270. ViaSuperIOState *sc = opaque;
  271. uint8_t idx = sc->regs[0];
  272. uint8_t val = sc->regs[idx];
  273. if (addr == 0) {
  274. return idx;
  275. }
  276. if (addr == 1 && idx == 0) {
  277. val = 0; /* reading reg 0 where we store index value */
  278. }
  279. trace_via_superio_read(idx, val);
  280. return val;
  281. }
  282. static void via_superio_devices_enable(ViaSuperIOState *s, uint8_t data)
  283. {
  284. ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s);
  285. isa_parallel_set_enabled(s->superio.parallel[0], (data & 0x3) != 3);
  286. for (int i = 0; i < ic->serial.count; i++) {
  287. isa_serial_set_enabled(s->superio.serial[i], data & BIT(i + 2));
  288. }
  289. isa_fdc_set_enabled(s->superio.floppy, data & BIT(4));
  290. }
  291. static void via_superio_class_init(ObjectClass *klass, void *data)
  292. {
  293. DeviceClass *dc = DEVICE_CLASS(klass);
  294. ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
  295. device_class_set_parent_realize(dc, via_superio_realize,
  296. &sc->parent_realize);
  297. }
  298. static const TypeInfo via_superio_info = {
  299. .name = TYPE_VIA_SUPERIO,
  300. .parent = TYPE_ISA_SUPERIO,
  301. .instance_size = sizeof(ViaSuperIOState),
  302. .class_size = sizeof(ISASuperIOClass),
  303. .class_init = via_superio_class_init,
  304. .abstract = true,
  305. };
  306. #define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
  307. static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr,
  308. uint64_t data, unsigned size)
  309. {
  310. ViaSuperIOState *sc = opaque;
  311. uint8_t idx = sc->regs[0];
  312. if (addr == 0) { /* config index register */
  313. sc->regs[0] = data;
  314. return;
  315. }
  316. /* config data register */
  317. trace_via_superio_write(idx, data);
  318. switch (idx) {
  319. case 0x00 ... 0xdf:
  320. case 0xe4:
  321. case 0xe5:
  322. case 0xe9 ... 0xed:
  323. case 0xf3:
  324. case 0xf5:
  325. case 0xf7:
  326. case 0xf9 ... 0xfb:
  327. case 0xfd ... 0xff:
  328. /* ignore write to read only registers */
  329. return;
  330. case 0xe2:
  331. data &= 0x1f;
  332. via_superio_devices_enable(sc, data);
  333. break;
  334. case 0xe3:
  335. data &= 0xfc;
  336. isa_fdc_set_iobase(sc->superio.floppy, data << 2);
  337. break;
  338. case 0xe6:
  339. isa_parallel_set_iobase(sc->superio.parallel[0], data << 2);
  340. break;
  341. case 0xe7:
  342. data &= 0xfe;
  343. isa_serial_set_iobase(sc->superio.serial[0], data << 2);
  344. break;
  345. case 0xe8:
  346. data &= 0xfe;
  347. isa_serial_set_iobase(sc->superio.serial[1], data << 2);
  348. break;
  349. default:
  350. qemu_log_mask(LOG_UNIMP,
  351. "via_superio_cfg: unimplemented register 0x%x\n", idx);
  352. break;
  353. }
  354. sc->regs[idx] = data;
  355. }
  356. static const MemoryRegionOps vt82c686b_superio_cfg_ops = {
  357. .read = via_superio_cfg_read,
  358. .write = vt82c686b_superio_cfg_write,
  359. .endianness = DEVICE_NATIVE_ENDIAN,
  360. .impl = {
  361. .min_access_size = 1,
  362. .max_access_size = 1,
  363. },
  364. };
  365. static void vt82c686b_superio_reset(DeviceState *dev)
  366. {
  367. ViaSuperIOState *s = VIA_SUPERIO(dev);
  368. memset(s->regs, 0, sizeof(s->regs));
  369. /* Device ID */
  370. vt82c686b_superio_cfg_write(s, 0, 0xe0, 1);
  371. vt82c686b_superio_cfg_write(s, 1, 0x3c, 1);
  372. /*
  373. * Function select - only serial enabled
  374. * Fuloong 2e's rescue-yl prints to the serial console w/o enabling it. This
  375. * suggests that the serial ports are enabled by default, so override the
  376. * datasheet.
  377. */
  378. vt82c686b_superio_cfg_write(s, 0, 0xe2, 1);
  379. vt82c686b_superio_cfg_write(s, 1, 0x0f, 1);
  380. /* Floppy ctrl base addr 0x3f0-7 */
  381. vt82c686b_superio_cfg_write(s, 0, 0xe3, 1);
  382. vt82c686b_superio_cfg_write(s, 1, 0xfc, 1);
  383. /* Parallel port base addr 0x378-f */
  384. vt82c686b_superio_cfg_write(s, 0, 0xe6, 1);
  385. vt82c686b_superio_cfg_write(s, 1, 0xde, 1);
  386. /* Serial port 1 base addr 0x3f8-f */
  387. vt82c686b_superio_cfg_write(s, 0, 0xe7, 1);
  388. vt82c686b_superio_cfg_write(s, 1, 0xfe, 1);
  389. /* Serial port 2 base addr 0x2f8-f */
  390. vt82c686b_superio_cfg_write(s, 0, 0xe8, 1);
  391. vt82c686b_superio_cfg_write(s, 1, 0xbe, 1);
  392. vt82c686b_superio_cfg_write(s, 0, 0, 1);
  393. }
  394. static void vt82c686b_superio_init(Object *obj)
  395. {
  396. VIA_SUPERIO(obj)->io_ops = &vt82c686b_superio_cfg_ops;
  397. }
  398. static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
  399. {
  400. DeviceClass *dc = DEVICE_CLASS(klass);
  401. ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
  402. device_class_set_legacy_reset(dc, vt82c686b_superio_reset);
  403. sc->serial.count = 2;
  404. sc->parallel.count = 1;
  405. sc->ide.count = 0; /* emulated by via-ide */
  406. sc->floppy.count = 1;
  407. }
  408. static const TypeInfo vt82c686b_superio_info = {
  409. .name = TYPE_VT82C686B_SUPERIO,
  410. .parent = TYPE_VIA_SUPERIO,
  411. .instance_size = sizeof(ViaSuperIOState),
  412. .instance_init = vt82c686b_superio_init,
  413. .class_size = sizeof(ISASuperIOClass),
  414. .class_init = vt82c686b_superio_class_init,
  415. };
  416. #define TYPE_VT8231_SUPERIO "vt8231-superio"
  417. static void vt8231_superio_cfg_write(void *opaque, hwaddr addr,
  418. uint64_t data, unsigned size)
  419. {
  420. ViaSuperIOState *sc = opaque;
  421. uint8_t idx = sc->regs[0];
  422. if (addr == 0) { /* config index register */
  423. sc->regs[0] = data;
  424. return;
  425. }
  426. /* config data register */
  427. trace_via_superio_write(idx, data);
  428. switch (idx) {
  429. case 0x00 ... 0xdf:
  430. case 0xe7 ... 0xef:
  431. case 0xf0 ... 0xf1:
  432. case 0xf5:
  433. case 0xf8:
  434. case 0xfd:
  435. /* ignore write to read only registers */
  436. return;
  437. case 0xf2:
  438. data &= 0x17;
  439. via_superio_devices_enable(sc, data);
  440. break;
  441. case 0xf4:
  442. data &= 0xfe;
  443. isa_serial_set_iobase(sc->superio.serial[0], data << 2);
  444. break;
  445. case 0xf6:
  446. isa_parallel_set_iobase(sc->superio.parallel[0], data << 2);
  447. break;
  448. case 0xf7:
  449. data &= 0xfc;
  450. isa_fdc_set_iobase(sc->superio.floppy, data << 2);
  451. break;
  452. default:
  453. qemu_log_mask(LOG_UNIMP,
  454. "via_superio_cfg: unimplemented register 0x%x\n", idx);
  455. break;
  456. }
  457. sc->regs[idx] = data;
  458. }
  459. static const MemoryRegionOps vt8231_superio_cfg_ops = {
  460. .read = via_superio_cfg_read,
  461. .write = vt8231_superio_cfg_write,
  462. .endianness = DEVICE_NATIVE_ENDIAN,
  463. .impl = {
  464. .min_access_size = 1,
  465. .max_access_size = 1,
  466. },
  467. };
  468. static void vt8231_superio_reset(DeviceState *dev)
  469. {
  470. ViaSuperIOState *s = VIA_SUPERIO(dev);
  471. memset(s->regs, 0, sizeof(s->regs));
  472. /* Device ID */
  473. s->regs[0xf0] = 0x3c;
  474. /* Device revision */
  475. s->regs[0xf1] = 0x01;
  476. /* Function select - all disabled */
  477. vt8231_superio_cfg_write(s, 0, 0xf2, 1);
  478. vt8231_superio_cfg_write(s, 1, 0x03, 1);
  479. /* Serial port base addr */
  480. vt8231_superio_cfg_write(s, 0, 0xf4, 1);
  481. vt8231_superio_cfg_write(s, 1, 0xfe, 1);
  482. /* Parallel port base addr */
  483. vt8231_superio_cfg_write(s, 0, 0xf6, 1);
  484. vt8231_superio_cfg_write(s, 1, 0xde, 1);
  485. /* Floppy ctrl base addr */
  486. vt8231_superio_cfg_write(s, 0, 0xf7, 1);
  487. vt8231_superio_cfg_write(s, 1, 0xfc, 1);
  488. vt8231_superio_cfg_write(s, 0, 0, 1);
  489. }
  490. static void vt8231_superio_init(Object *obj)
  491. {
  492. VIA_SUPERIO(obj)->io_ops = &vt8231_superio_cfg_ops;
  493. }
  494. static void vt8231_superio_class_init(ObjectClass *klass, void *data)
  495. {
  496. DeviceClass *dc = DEVICE_CLASS(klass);
  497. ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
  498. device_class_set_legacy_reset(dc, vt8231_superio_reset);
  499. sc->serial.count = 1;
  500. sc->parallel.count = 1;
  501. sc->ide.count = 0; /* emulated by via-ide */
  502. sc->floppy.count = 1;
  503. }
  504. static const TypeInfo vt8231_superio_info = {
  505. .name = TYPE_VT8231_SUPERIO,
  506. .parent = TYPE_VIA_SUPERIO,
  507. .instance_size = sizeof(ViaSuperIOState),
  508. .instance_init = vt8231_superio_init,
  509. .class_size = sizeof(ISASuperIOClass),
  510. .class_init = vt8231_superio_class_init,
  511. };
  512. #define TYPE_VIA_ISA "via-isa"
  513. OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA)
  514. struct ViaISAState {
  515. PCIDevice dev;
  516. IRQState i8259_irq;
  517. qemu_irq cpu_intr;
  518. qemu_irq *isa_irqs_in;
  519. uint16_t irq_state[ISA_NUM_IRQS];
  520. ViaSuperIOState via_sio;
  521. MC146818RtcState rtc;
  522. PCIIDEState ide;
  523. UHCIState uhci[2];
  524. ViaPMState pm;
  525. ViaAC97State ac97;
  526. PCIDevice mc97;
  527. };
  528. static const VMStateDescription vmstate_via = {
  529. .name = "via-isa",
  530. .version_id = 1,
  531. .minimum_version_id = 1,
  532. .fields = (const VMStateField[]) {
  533. VMSTATE_PCI_DEVICE(dev, ViaISAState),
  534. VMSTATE_END_OF_LIST()
  535. }
  536. };
  537. static void via_isa_init(Object *obj)
  538. {
  539. ViaISAState *s = VIA_ISA(obj);
  540. object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
  541. object_initialize_child(obj, "ide", &s->ide, TYPE_VIA_IDE);
  542. object_initialize_child(obj, "uhci1", &s->uhci[0], TYPE_VT82C686B_USB_UHCI);
  543. object_initialize_child(obj, "uhci2", &s->uhci[1], TYPE_VT82C686B_USB_UHCI);
  544. object_initialize_child(obj, "ac97", &s->ac97, TYPE_VIA_AC97);
  545. object_initialize_child(obj, "mc97", &s->mc97, TYPE_VIA_MC97);
  546. }
  547. static const TypeInfo via_isa_info = {
  548. .name = TYPE_VIA_ISA,
  549. .parent = TYPE_PCI_DEVICE,
  550. .instance_size = sizeof(ViaISAState),
  551. .instance_init = via_isa_init,
  552. .abstract = true,
  553. .interfaces = (InterfaceInfo[]) {
  554. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  555. { },
  556. },
  557. };
  558. static int via_isa_get_pci_irq(const ViaISAState *s, int pin)
  559. {
  560. switch (pin) {
  561. case 0:
  562. return s->dev.config[0x55] >> 4;
  563. case 1:
  564. return s->dev.config[0x56] & 0xf;
  565. case 2:
  566. return s->dev.config[0x56] >> 4;
  567. case 3:
  568. return s->dev.config[0x57] >> 4;
  569. }
  570. return 0;
  571. }
  572. void via_isa_set_irq(PCIDevice *d, int pin, int level)
  573. {
  574. ViaISAState *s = VIA_ISA(pci_get_function_0(d));
  575. uint8_t irq = d->config[PCI_INTERRUPT_LINE], max_irq = 15;
  576. int f = PCI_FUNC(d->devfn);
  577. uint16_t mask;
  578. switch (f) {
  579. case 0: /* PIRQ/PINT inputs */
  580. irq = via_isa_get_pci_irq(s, pin);
  581. f = 8 + pin; /* Use function 8-11 for PCI interrupt inputs */
  582. break;
  583. case 2: /* USB ports 0-1 */
  584. case 3: /* USB ports 2-3 */
  585. case 5: /* AC97 audio */
  586. max_irq = 14;
  587. break;
  588. }
  589. /* Keep track of the state of all sources */
  590. mask = BIT(f);
  591. if (level) {
  592. s->irq_state[0] |= mask;
  593. } else {
  594. s->irq_state[0] &= ~mask;
  595. }
  596. if (irq == 0 || irq == 0xff) {
  597. return; /* disabled */
  598. }
  599. if (unlikely(irq > max_irq || irq == 2)) {
  600. qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing %d for %d",
  601. irq, f);
  602. return;
  603. }
  604. /* Record source state at mapped IRQ */
  605. if (level) {
  606. s->irq_state[irq] |= mask;
  607. } else {
  608. s->irq_state[irq] &= ~mask;
  609. }
  610. /* Make sure there are no stuck bits if mapping has changed */
  611. s->irq_state[irq] &= s->irq_state[0];
  612. /* ISA IRQ level is the OR of all sources routed to it */
  613. qemu_set_irq(s->isa_irqs_in[irq], !!s->irq_state[irq]);
  614. }
  615. static void via_isa_pirq(void *opaque, int pin, int level)
  616. {
  617. via_isa_set_irq(opaque, pin, level);
  618. }
  619. static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
  620. {
  621. ViaISAState *s = opaque;
  622. qemu_set_irq(s->cpu_intr, level);
  623. }
  624. static void via_isa_realize(PCIDevice *d, Error **errp)
  625. {
  626. ViaISAState *s = VIA_ISA(d);
  627. DeviceState *dev = DEVICE(d);
  628. PCIBus *pci_bus = pci_get_bus(d);
  629. ISABus *isa_bus;
  630. int i;
  631. qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1);
  632. qdev_init_gpio_in_named(dev, via_isa_pirq, "pirq", PCI_NUM_PINS);
  633. qemu_init_irq(&s->i8259_irq, via_isa_request_i8259_irq, s, 0);
  634. isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d),
  635. errp);
  636. if (!isa_bus) {
  637. return;
  638. }
  639. s->isa_irqs_in = i8259_init(isa_bus, &s->i8259_irq);
  640. isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
  641. i8254_pit_init(isa_bus, 0x40, 0, NULL);
  642. i8257_dma_init(OBJECT(d), isa_bus, 0);
  643. /* RTC */
  644. qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
  645. if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
  646. return;
  647. }
  648. isa_connect_gpio_out(ISA_DEVICE(&s->rtc), 0, s->rtc.isairq);
  649. for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
  650. if (i < PCI_COMMAND || i >= PCI_REVISION_ID) {
  651. d->wmask[i] = 0;
  652. }
  653. }
  654. /* Super I/O */
  655. if (!qdev_realize(DEVICE(&s->via_sio), BUS(isa_bus), errp)) {
  656. return;
  657. }
  658. /* Function 1: IDE */
  659. qdev_prop_set_int32(DEVICE(&s->ide), "addr", d->devfn + 1);
  660. if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
  661. return;
  662. }
  663. for (i = 0; i < 2; i++) {
  664. qdev_connect_gpio_out_named(DEVICE(&s->ide), "isa-irq", i,
  665. s->isa_irqs_in[14 + i]);
  666. }
  667. /* Functions 2-3: USB Ports */
  668. for (i = 0; i < ARRAY_SIZE(s->uhci); i++) {
  669. qdev_prop_set_int32(DEVICE(&s->uhci[i]), "addr", d->devfn + 2 + i);
  670. if (!qdev_realize(DEVICE(&s->uhci[i]), BUS(pci_bus), errp)) {
  671. return;
  672. }
  673. }
  674. /* Function 4: Power Management */
  675. qdev_prop_set_int32(DEVICE(&s->pm), "addr", d->devfn + 4);
  676. if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
  677. return;
  678. }
  679. /* Function 5: AC97 Audio */
  680. qdev_prop_set_int32(DEVICE(&s->ac97), "addr", d->devfn + 5);
  681. if (!qdev_realize(DEVICE(&s->ac97), BUS(pci_bus), errp)) {
  682. return;
  683. }
  684. /* Function 6: MC97 Modem */
  685. qdev_prop_set_int32(DEVICE(&s->mc97), "addr", d->devfn + 6);
  686. if (!qdev_realize(DEVICE(&s->mc97), BUS(pci_bus), errp)) {
  687. return;
  688. }
  689. }
  690. /* TYPE_VT82C686B_ISA */
  691. static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
  692. uint32_t val, int len)
  693. {
  694. ViaISAState *s = VIA_ISA(d);
  695. trace_via_isa_write(addr, val, len);
  696. pci_default_write_config(d, addr, val, len);
  697. if (addr == 0x85) {
  698. /* BIT(1): enable or disable superio config io ports */
  699. via_superio_io_enable(&s->via_sio, val & BIT(1));
  700. }
  701. }
  702. static void vt82c686b_isa_reset(DeviceState *dev)
  703. {
  704. ViaISAState *s = VIA_ISA(dev);
  705. uint8_t *pci_conf = s->dev.config;
  706. pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
  707. pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  708. PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
  709. pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
  710. pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
  711. pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
  712. pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
  713. pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
  714. pci_conf[0x59] = 0x04;
  715. pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
  716. pci_conf[0x5f] = 0x04;
  717. pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
  718. }
  719. static void vt82c686b_init(Object *obj)
  720. {
  721. ViaISAState *s = VIA_ISA(obj);
  722. object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT82C686B_SUPERIO);
  723. object_initialize_child(obj, "pm", &s->pm, TYPE_VT82C686B_PM);
  724. }
  725. static void vt82c686b_class_init(ObjectClass *klass, void *data)
  726. {
  727. DeviceClass *dc = DEVICE_CLASS(klass);
  728. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  729. k->realize = via_isa_realize;
  730. k->config_write = vt82c686b_write_config;
  731. k->vendor_id = PCI_VENDOR_ID_VIA;
  732. k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA;
  733. k->class_id = PCI_CLASS_BRIDGE_ISA;
  734. k->revision = 0x40;
  735. device_class_set_legacy_reset(dc, vt82c686b_isa_reset);
  736. dc->desc = "ISA bridge";
  737. dc->vmsd = &vmstate_via;
  738. /* Reason: part of VIA VT82C686 southbridge, needs to be wired up */
  739. dc->user_creatable = false;
  740. }
  741. static const TypeInfo vt82c686b_isa_info = {
  742. .name = TYPE_VT82C686B_ISA,
  743. .parent = TYPE_VIA_ISA,
  744. .instance_size = sizeof(ViaISAState),
  745. .instance_init = vt82c686b_init,
  746. .class_init = vt82c686b_class_init,
  747. };
  748. /* TYPE_VT8231_ISA */
  749. static void vt8231_write_config(PCIDevice *d, uint32_t addr,
  750. uint32_t val, int len)
  751. {
  752. ViaISAState *s = VIA_ISA(d);
  753. trace_via_isa_write(addr, val, len);
  754. pci_default_write_config(d, addr, val, len);
  755. if (addr == 0x50) {
  756. /* BIT(2): enable or disable superio config io ports */
  757. via_superio_io_enable(&s->via_sio, val & BIT(2));
  758. }
  759. }
  760. static void vt8231_isa_reset(DeviceState *dev)
  761. {
  762. ViaISAState *s = VIA_ISA(dev);
  763. uint8_t *pci_conf = s->dev.config;
  764. pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
  765. pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  766. PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
  767. pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
  768. pci_conf[0x4c] = 0x04; /* IDE interrupt Routing */
  769. pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */
  770. pci_conf[0x67] = 0x08; /* Fast IR Config */
  771. pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */
  772. }
  773. static void vt8231_init(Object *obj)
  774. {
  775. ViaISAState *s = VIA_ISA(obj);
  776. object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT8231_SUPERIO);
  777. object_initialize_child(obj, "pm", &s->pm, TYPE_VT8231_PM);
  778. }
  779. static void vt8231_class_init(ObjectClass *klass, void *data)
  780. {
  781. DeviceClass *dc = DEVICE_CLASS(klass);
  782. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  783. k->realize = via_isa_realize;
  784. k->config_write = vt8231_write_config;
  785. k->vendor_id = PCI_VENDOR_ID_VIA;
  786. k->device_id = PCI_DEVICE_ID_VIA_8231_ISA;
  787. k->class_id = PCI_CLASS_BRIDGE_ISA;
  788. k->revision = 0x10;
  789. device_class_set_legacy_reset(dc, vt8231_isa_reset);
  790. dc->desc = "ISA bridge";
  791. dc->vmsd = &vmstate_via;
  792. /* Reason: part of VIA VT8231 southbridge, needs to be wired up */
  793. dc->user_creatable = false;
  794. }
  795. static const TypeInfo vt8231_isa_info = {
  796. .name = TYPE_VT8231_ISA,
  797. .parent = TYPE_VIA_ISA,
  798. .instance_size = sizeof(ViaISAState),
  799. .instance_init = vt8231_init,
  800. .class_init = vt8231_class_init,
  801. };
  802. static void vt82c686b_register_types(void)
  803. {
  804. type_register_static(&via_pm_info);
  805. type_register_static(&vt82c686b_pm_info);
  806. type_register_static(&vt8231_pm_info);
  807. type_register_static(&via_superio_info);
  808. type_register_static(&vt82c686b_superio_info);
  809. type_register_static(&vt8231_superio_info);
  810. type_register_static(&via_isa_info);
  811. type_register_static(&vt82c686b_isa_info);
  812. type_register_static(&vt8231_isa_info);
  813. }
  814. type_init(vt82c686b_register_types)