allwinner-a10-pic.c 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212
  1. /*
  2. * Allwinner A10 interrupt controller device emulation
  3. *
  4. * Copyright (C) 2013 Li Guang
  5. * Written by Li Guang <lig.fnst@cn.fujitsu.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15. * for more details.
  16. */
  17. #include "qemu/osdep.h"
  18. #include "hw/sysbus.h"
  19. #include "migration/vmstate.h"
  20. #include "hw/intc/allwinner-a10-pic.h"
  21. #include "hw/irq.h"
  22. #include "qemu/log.h"
  23. #include "qemu/module.h"
  24. static void aw_a10_pic_update(AwA10PICState *s)
  25. {
  26. uint8_t i;
  27. int irq = 0, fiq = 0, zeroes;
  28. s->vector = 0;
  29. for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
  30. irq |= s->irq_pending[i] & ~s->mask[i];
  31. fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
  32. if (!s->vector) {
  33. zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]);
  34. if (zeroes != 32) {
  35. s->vector = (i * 32 + zeroes) * 4;
  36. }
  37. }
  38. }
  39. qemu_set_irq(s->parent_irq, !!irq);
  40. qemu_set_irq(s->parent_fiq, !!fiq);
  41. }
  42. static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
  43. {
  44. AwA10PICState *s = opaque;
  45. uint32_t *pending_reg = &s->irq_pending[irq / 32];
  46. *pending_reg = deposit32(*pending_reg, irq % 32, 1, !!level);
  47. aw_a10_pic_update(s);
  48. }
  49. static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size)
  50. {
  51. AwA10PICState *s = opaque;
  52. uint8_t index = (offset & 0xc) / 4;
  53. switch (offset) {
  54. case AW_A10_PIC_VECTOR:
  55. return s->vector;
  56. case AW_A10_PIC_BASE_ADDR:
  57. return s->base_addr;
  58. case AW_A10_PIC_PROTECT:
  59. return s->protect;
  60. case AW_A10_PIC_NMI:
  61. return s->nmi;
  62. case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
  63. return s->irq_pending[index];
  64. case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
  65. return s->fiq_pending[index];
  66. case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
  67. return s->select[index];
  68. case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
  69. return s->enable[index];
  70. case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
  71. return s->mask[index];
  72. default:
  73. qemu_log_mask(LOG_GUEST_ERROR,
  74. "%s: Bad offset 0x%x\n", __func__, (int)offset);
  75. break;
  76. }
  77. return 0;
  78. }
  79. static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
  80. unsigned size)
  81. {
  82. AwA10PICState *s = opaque;
  83. uint8_t index = (offset & 0xc) / 4;
  84. switch (offset) {
  85. case AW_A10_PIC_BASE_ADDR:
  86. s->base_addr = value & ~0x3;
  87. break;
  88. case AW_A10_PIC_PROTECT:
  89. s->protect = value;
  90. break;
  91. case AW_A10_PIC_NMI:
  92. s->nmi = value;
  93. break;
  94. case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
  95. /*
  96. * The register is read-only; nevertheless, Linux (including
  97. * the version originally shipped by Allwinner) pretends to
  98. * write to the register. Just ignore it.
  99. */
  100. break;
  101. case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
  102. s->fiq_pending[index] &= ~value;
  103. break;
  104. case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
  105. s->select[index] = value;
  106. break;
  107. case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
  108. s->enable[index] = value;
  109. break;
  110. case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
  111. s->mask[index] = value;
  112. break;
  113. default:
  114. qemu_log_mask(LOG_GUEST_ERROR,
  115. "%s: Bad offset 0x%x\n", __func__, (int)offset);
  116. break;
  117. }
  118. aw_a10_pic_update(s);
  119. }
  120. static const MemoryRegionOps aw_a10_pic_ops = {
  121. .read = aw_a10_pic_read,
  122. .write = aw_a10_pic_write,
  123. .endianness = DEVICE_LITTLE_ENDIAN,
  124. };
  125. static const VMStateDescription vmstate_aw_a10_pic = {
  126. .name = "a10.pic",
  127. .version_id = 1,
  128. .minimum_version_id = 1,
  129. .fields = (const VMStateField[]) {
  130. VMSTATE_UINT32(vector, AwA10PICState),
  131. VMSTATE_UINT32(base_addr, AwA10PICState),
  132. VMSTATE_UINT32(protect, AwA10PICState),
  133. VMSTATE_UINT32(nmi, AwA10PICState),
  134. VMSTATE_UINT32_ARRAY(irq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
  135. VMSTATE_UINT32_ARRAY(fiq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
  136. VMSTATE_UINT32_ARRAY(enable, AwA10PICState, AW_A10_PIC_REG_NUM),
  137. VMSTATE_UINT32_ARRAY(select, AwA10PICState, AW_A10_PIC_REG_NUM),
  138. VMSTATE_UINT32_ARRAY(mask, AwA10PICState, AW_A10_PIC_REG_NUM),
  139. VMSTATE_END_OF_LIST()
  140. }
  141. };
  142. static void aw_a10_pic_init(Object *obj)
  143. {
  144. AwA10PICState *s = AW_A10_PIC(obj);
  145. SysBusDevice *dev = SYS_BUS_DEVICE(obj);
  146. qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR);
  147. sysbus_init_irq(dev, &s->parent_irq);
  148. sysbus_init_irq(dev, &s->parent_fiq);
  149. memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s,
  150. TYPE_AW_A10_PIC, 0x400);
  151. sysbus_init_mmio(dev, &s->iomem);
  152. }
  153. static void aw_a10_pic_reset(DeviceState *d)
  154. {
  155. AwA10PICState *s = AW_A10_PIC(d);
  156. uint8_t i;
  157. s->base_addr = 0;
  158. s->protect = 0;
  159. s->nmi = 0;
  160. s->vector = 0;
  161. for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
  162. s->irq_pending[i] = 0;
  163. s->fiq_pending[i] = 0;
  164. s->select[i] = 0;
  165. s->enable[i] = 0;
  166. s->mask[i] = 0;
  167. }
  168. }
  169. static void aw_a10_pic_class_init(ObjectClass *klass, void *data)
  170. {
  171. DeviceClass *dc = DEVICE_CLASS(klass);
  172. device_class_set_legacy_reset(dc, aw_a10_pic_reset);
  173. dc->desc = "allwinner a10 pic";
  174. dc->vmsd = &vmstate_aw_a10_pic;
  175. }
  176. static const TypeInfo aw_a10_pic_info = {
  177. .name = TYPE_AW_A10_PIC,
  178. .parent = TYPE_SYS_BUS_DEVICE,
  179. .instance_size = sizeof(AwA10PICState),
  180. .instance_init = aw_a10_pic_init,
  181. .class_init = aw_a10_pic_class_init,
  182. };
  183. static void aw_a10_register_types(void)
  184. {
  185. type_register_static(&aw_a10_pic_info);
  186. }
  187. type_init(aw_a10_register_types);