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core.c 11 KB

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  1. /*
  2. * QEMU I2C bus interface.
  3. *
  4. * Copyright (c) 2007 CodeSourcery.
  5. * Written by Paul Brook
  6. *
  7. * This code is licensed under the LGPL.
  8. */
  9. #include "qemu/osdep.h"
  10. #include "hw/i2c/i2c.h"
  11. #include "hw/qdev-properties.h"
  12. #include "migration/vmstate.h"
  13. #include "qapi/error.h"
  14. #include "qemu/module.h"
  15. #include "qemu/main-loop.h"
  16. #include "trace.h"
  17. #define I2C_BROADCAST 0x00
  18. static const Property i2c_props[] = {
  19. DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
  20. };
  21. static const TypeInfo i2c_bus_info = {
  22. .name = TYPE_I2C_BUS,
  23. .parent = TYPE_BUS,
  24. .instance_size = sizeof(I2CBus),
  25. };
  26. static int i2c_bus_pre_save(void *opaque)
  27. {
  28. I2CBus *bus = opaque;
  29. bus->saved_address = -1;
  30. if (!QLIST_EMPTY(&bus->current_devs)) {
  31. if (!bus->broadcast) {
  32. bus->saved_address = QLIST_FIRST(&bus->current_devs)->elt->address;
  33. } else {
  34. bus->saved_address = I2C_BROADCAST;
  35. }
  36. }
  37. return 0;
  38. }
  39. static const VMStateDescription vmstate_i2c_bus = {
  40. .name = "i2c_bus",
  41. .version_id = 1,
  42. .minimum_version_id = 1,
  43. .pre_save = i2c_bus_pre_save,
  44. .fields = (const VMStateField[]) {
  45. VMSTATE_UINT8(saved_address, I2CBus),
  46. VMSTATE_END_OF_LIST()
  47. }
  48. };
  49. /* Create a new I2C bus. */
  50. I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
  51. {
  52. I2CBus *bus;
  53. bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
  54. QLIST_INIT(&bus->current_devs);
  55. QSIMPLEQ_INIT(&bus->pending_masters);
  56. vmstate_register_any(NULL, &vmstate_i2c_bus, bus);
  57. return bus;
  58. }
  59. void i2c_slave_set_address(I2CSlave *dev, uint8_t address)
  60. {
  61. dev->address = address;
  62. }
  63. /* Return nonzero if bus is busy. */
  64. int i2c_bus_busy(I2CBus *bus)
  65. {
  66. return !QLIST_EMPTY(&bus->current_devs) || bus->bh;
  67. }
  68. bool i2c_scan_bus(I2CBus *bus, uint8_t address, bool broadcast,
  69. I2CNodeList *current_devs)
  70. {
  71. BusChild *kid;
  72. QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
  73. DeviceState *qdev = kid->child;
  74. I2CSlave *candidate = I2C_SLAVE(qdev);
  75. I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(candidate);
  76. if (sc->match_and_add(candidate, address, broadcast, current_devs)) {
  77. if (!broadcast) {
  78. return true;
  79. }
  80. }
  81. }
  82. /*
  83. * If broadcast was true, and the list was full or empty, return true. If
  84. * broadcast was false, return false.
  85. */
  86. return broadcast;
  87. }
  88. /* TODO: Make this handle multiple masters. */
  89. /*
  90. * Start or continue an i2c transaction. When this is called for the
  91. * first time or after an i2c_end_transfer(), if it returns an error
  92. * the bus transaction is terminated (or really never started). If
  93. * this is called after another i2c_start_transfer() without an
  94. * intervening i2c_end_transfer(), and it returns an error, the
  95. * transaction will not be terminated. The caller must do it.
  96. *
  97. * This corresponds with the way real hardware works. The SMBus
  98. * protocol uses a start transfer to switch from write to read mode
  99. * without releasing the bus. If that fails, the bus is still
  100. * in a transaction.
  101. *
  102. * @event must be I2C_START_RECV or I2C_START_SEND.
  103. */
  104. static int i2c_do_start_transfer(I2CBus *bus, uint8_t address,
  105. enum i2c_event event)
  106. {
  107. I2CSlaveClass *sc;
  108. I2CNode *node;
  109. bool bus_scanned = false;
  110. if (address == I2C_BROADCAST) {
  111. /*
  112. * This is a broadcast, the current_devs will be all the devices of the
  113. * bus.
  114. */
  115. bus->broadcast = true;
  116. }
  117. /*
  118. * If there are already devices in the list, that means we are in
  119. * the middle of a transaction and we shouldn't rescan the bus.
  120. *
  121. * This happens with any SMBus transaction, even on a pure I2C
  122. * device. The interface does a transaction start without
  123. * terminating the previous transaction.
  124. */
  125. if (QLIST_EMPTY(&bus->current_devs)) {
  126. /* Disregard whether devices were found. */
  127. (void)i2c_scan_bus(bus, address, bus->broadcast, &bus->current_devs);
  128. bus_scanned = true;
  129. }
  130. if (QLIST_EMPTY(&bus->current_devs)) {
  131. return 1;
  132. }
  133. QLIST_FOREACH(node, &bus->current_devs, next) {
  134. I2CSlave *s = node->elt;
  135. int rv;
  136. sc = I2C_SLAVE_GET_CLASS(s);
  137. /* If the bus is already busy, assume this is a repeated
  138. start condition. */
  139. if (sc->event) {
  140. trace_i2c_event(event == I2C_START_SEND ? "start" : "start_async",
  141. s->address);
  142. rv = sc->event(s, event);
  143. if (rv && !bus->broadcast) {
  144. if (bus_scanned) {
  145. /* First call, terminate the transfer. */
  146. i2c_end_transfer(bus);
  147. }
  148. return rv;
  149. }
  150. }
  151. }
  152. return 0;
  153. }
  154. int i2c_start_transfer(I2CBus *bus, uint8_t address, bool is_recv)
  155. {
  156. return i2c_do_start_transfer(bus, address, is_recv
  157. ? I2C_START_RECV
  158. : I2C_START_SEND);
  159. }
  160. void i2c_bus_master(I2CBus *bus, QEMUBH *bh)
  161. {
  162. I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);
  163. node->bh = bh;
  164. QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);
  165. }
  166. void i2c_schedule_pending_master(I2CBus *bus)
  167. {
  168. I2CPendingMaster *node;
  169. if (i2c_bus_busy(bus)) {
  170. /* someone is already controlling the bus; wait for it to release it */
  171. return;
  172. }
  173. if (QSIMPLEQ_EMPTY(&bus->pending_masters)) {
  174. return;
  175. }
  176. node = QSIMPLEQ_FIRST(&bus->pending_masters);
  177. bus->bh = node->bh;
  178. QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);
  179. g_free(node);
  180. qemu_bh_schedule(bus->bh);
  181. }
  182. void i2c_bus_release(I2CBus *bus)
  183. {
  184. bus->bh = NULL;
  185. i2c_schedule_pending_master(bus);
  186. }
  187. int i2c_start_recv(I2CBus *bus, uint8_t address)
  188. {
  189. return i2c_do_start_transfer(bus, address, I2C_START_RECV);
  190. }
  191. int i2c_start_send(I2CBus *bus, uint8_t address)
  192. {
  193. return i2c_do_start_transfer(bus, address, I2C_START_SEND);
  194. }
  195. int i2c_start_send_async(I2CBus *bus, uint8_t address)
  196. {
  197. return i2c_do_start_transfer(bus, address, I2C_START_SEND_ASYNC);
  198. }
  199. void i2c_end_transfer(I2CBus *bus)
  200. {
  201. I2CSlaveClass *sc;
  202. I2CNode *node, *next;
  203. QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
  204. I2CSlave *s = node->elt;
  205. sc = I2C_SLAVE_GET_CLASS(s);
  206. if (sc->event) {
  207. trace_i2c_event("finish", s->address);
  208. sc->event(s, I2C_FINISH);
  209. }
  210. QLIST_REMOVE(node, next);
  211. g_free(node);
  212. }
  213. bus->broadcast = false;
  214. }
  215. int i2c_send(I2CBus *bus, uint8_t data)
  216. {
  217. I2CSlaveClass *sc;
  218. I2CSlave *s;
  219. I2CNode *node;
  220. int ret = 0;
  221. QLIST_FOREACH(node, &bus->current_devs, next) {
  222. s = node->elt;
  223. sc = I2C_SLAVE_GET_CLASS(s);
  224. if (sc->send) {
  225. trace_i2c_send(s->address, data);
  226. ret = ret || sc->send(s, data);
  227. } else {
  228. ret = -1;
  229. }
  230. }
  231. return ret ? -1 : 0;
  232. }
  233. int i2c_send_async(I2CBus *bus, uint8_t data)
  234. {
  235. I2CNode *node = QLIST_FIRST(&bus->current_devs);
  236. I2CSlave *slave = node->elt;
  237. I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(slave);
  238. if (!sc->send_async) {
  239. return -1;
  240. }
  241. trace_i2c_send_async(slave->address, data);
  242. sc->send_async(slave, data);
  243. return 0;
  244. }
  245. uint8_t i2c_recv(I2CBus *bus)
  246. {
  247. uint8_t data = 0xff;
  248. I2CSlaveClass *sc;
  249. I2CSlave *s;
  250. if (!QLIST_EMPTY(&bus->current_devs) && !bus->broadcast) {
  251. sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt);
  252. if (sc->recv) {
  253. s = QLIST_FIRST(&bus->current_devs)->elt;
  254. data = sc->recv(s);
  255. trace_i2c_recv(s->address, data);
  256. }
  257. }
  258. return data;
  259. }
  260. void i2c_nack(I2CBus *bus)
  261. {
  262. I2CSlaveClass *sc;
  263. I2CNode *node;
  264. if (QLIST_EMPTY(&bus->current_devs)) {
  265. return;
  266. }
  267. QLIST_FOREACH(node, &bus->current_devs, next) {
  268. sc = I2C_SLAVE_GET_CLASS(node->elt);
  269. if (sc->event) {
  270. trace_i2c_event("nack", node->elt->address);
  271. sc->event(node->elt, I2C_NACK);
  272. }
  273. }
  274. }
  275. void i2c_ack(I2CBus *bus)
  276. {
  277. if (!bus->bh) {
  278. return;
  279. }
  280. trace_i2c_ack();
  281. qemu_bh_schedule(bus->bh);
  282. }
  283. static int i2c_slave_post_load(void *opaque, int version_id)
  284. {
  285. I2CSlave *dev = opaque;
  286. I2CBus *bus;
  287. I2CNode *node;
  288. bus = I2C_BUS(qdev_get_parent_bus(DEVICE(dev)));
  289. if ((bus->saved_address == dev->address) ||
  290. (bus->saved_address == I2C_BROADCAST)) {
  291. node = g_new(struct I2CNode, 1);
  292. node->elt = dev;
  293. QLIST_INSERT_HEAD(&bus->current_devs, node, next);
  294. }
  295. return 0;
  296. }
  297. const VMStateDescription vmstate_i2c_slave = {
  298. .name = "I2CSlave",
  299. .version_id = 1,
  300. .minimum_version_id = 1,
  301. .post_load = i2c_slave_post_load,
  302. .fields = (const VMStateField[]) {
  303. VMSTATE_UINT8(address, I2CSlave),
  304. VMSTATE_END_OF_LIST()
  305. }
  306. };
  307. I2CSlave *i2c_slave_new(const char *name, uint8_t addr)
  308. {
  309. DeviceState *dev;
  310. dev = qdev_new(name);
  311. qdev_prop_set_uint8(dev, "address", addr);
  312. return I2C_SLAVE(dev);
  313. }
  314. bool i2c_slave_realize_and_unref(I2CSlave *dev, I2CBus *bus, Error **errp)
  315. {
  316. return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
  317. }
  318. I2CSlave *i2c_slave_create_simple(I2CBus *bus, const char *name, uint8_t addr)
  319. {
  320. I2CSlave *dev = i2c_slave_new(name, addr);
  321. i2c_slave_realize_and_unref(dev, bus, &error_abort);
  322. return dev;
  323. }
  324. static bool i2c_slave_match(I2CSlave *candidate, uint8_t address,
  325. bool broadcast, I2CNodeList *current_devs)
  326. {
  327. if ((candidate->address == address) || (broadcast)) {
  328. I2CNode *node = g_new(struct I2CNode, 1);
  329. node->elt = candidate;
  330. QLIST_INSERT_HEAD(current_devs, node, next);
  331. return true;
  332. }
  333. /* Not found and not broadcast. */
  334. return false;
  335. }
  336. static void i2c_slave_class_init(ObjectClass *klass, void *data)
  337. {
  338. DeviceClass *k = DEVICE_CLASS(klass);
  339. I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
  340. set_bit(DEVICE_CATEGORY_MISC, k->categories);
  341. k->bus_type = TYPE_I2C_BUS;
  342. device_class_set_props(k, i2c_props);
  343. sc->match_and_add = i2c_slave_match;
  344. }
  345. static const TypeInfo i2c_slave_type_info = {
  346. .name = TYPE_I2C_SLAVE,
  347. .parent = TYPE_DEVICE,
  348. .instance_size = sizeof(I2CSlave),
  349. .abstract = true,
  350. .class_size = sizeof(I2CSlaveClass),
  351. .class_init = i2c_slave_class_init,
  352. };
  353. static void i2c_slave_register_types(void)
  354. {
  355. type_register_static(&i2c_bus_info);
  356. type_register_static(&i2c_slave_type_info);
  357. }
  358. type_init(i2c_slave_register_types)