vmware_vga.c 39 KB

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  1. /*
  2. * QEMU VMware-SVGA "chipset".
  3. *
  4. * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "qemu/osdep.h"
  25. #include "qemu/module.h"
  26. #include "qemu/units.h"
  27. #include "qapi/error.h"
  28. #include "qemu/log.h"
  29. #include "hw/loader.h"
  30. #include "trace.h"
  31. #include "hw/pci/pci_device.h"
  32. #include "hw/qdev-properties.h"
  33. #include "migration/vmstate.h"
  34. #include "qom/object.h"
  35. #include "ui/console.h"
  36. #undef VERBOSE
  37. #define HW_RECT_ACCEL
  38. #define HW_FILL_ACCEL
  39. #define HW_MOUSE_ACCEL
  40. #include "vga_int.h"
  41. /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
  42. struct vmsvga_state_s {
  43. VGACommonState vga;
  44. int invalidated;
  45. int enable;
  46. int config;
  47. struct {
  48. int id;
  49. int x;
  50. int y;
  51. int on;
  52. } cursor;
  53. int index;
  54. int scratch_size;
  55. uint32_t *scratch;
  56. int new_width;
  57. int new_height;
  58. int new_depth;
  59. uint32_t guest;
  60. uint32_t svgaid;
  61. int syncing;
  62. MemoryRegion fifo_ram;
  63. uint8_t *fifo_ptr;
  64. unsigned int fifo_size;
  65. uint32_t *fifo;
  66. uint32_t fifo_min;
  67. uint32_t fifo_max;
  68. uint32_t fifo_next;
  69. uint32_t fifo_stop;
  70. #define REDRAW_FIFO_LEN 512
  71. struct vmsvga_rect_s {
  72. int x, y, w, h;
  73. } redraw_fifo[REDRAW_FIFO_LEN];
  74. int redraw_fifo_last;
  75. };
  76. #define TYPE_VMWARE_SVGA "vmware-svga"
  77. DECLARE_INSTANCE_CHECKER(struct pci_vmsvga_state_s, VMWARE_SVGA,
  78. TYPE_VMWARE_SVGA)
  79. struct pci_vmsvga_state_s {
  80. /*< private >*/
  81. PCIDevice parent_obj;
  82. /*< public >*/
  83. struct vmsvga_state_s chip;
  84. MemoryRegion io_bar;
  85. };
  86. #define SVGA_MAGIC 0x900000UL
  87. #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
  88. #define SVGA_ID_0 SVGA_MAKE_ID(0)
  89. #define SVGA_ID_1 SVGA_MAKE_ID(1)
  90. #define SVGA_ID_2 SVGA_MAKE_ID(2)
  91. #define SVGA_LEGACY_BASE_PORT 0x4560
  92. #define SVGA_INDEX_PORT 0x0
  93. #define SVGA_VALUE_PORT 0x1
  94. #define SVGA_BIOS_PORT 0x2
  95. #define SVGA_VERSION_2
  96. #ifdef SVGA_VERSION_2
  97. # define SVGA_ID SVGA_ID_2
  98. # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
  99. # define SVGA_IO_MUL 1
  100. # define SVGA_FIFO_SIZE 0x10000
  101. # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
  102. #else
  103. # define SVGA_ID SVGA_ID_1
  104. # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
  105. # define SVGA_IO_MUL 4
  106. # define SVGA_FIFO_SIZE 0x10000
  107. # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
  108. #endif
  109. enum {
  110. /* ID 0, 1 and 2 registers */
  111. SVGA_REG_ID = 0,
  112. SVGA_REG_ENABLE = 1,
  113. SVGA_REG_WIDTH = 2,
  114. SVGA_REG_HEIGHT = 3,
  115. SVGA_REG_MAX_WIDTH = 4,
  116. SVGA_REG_MAX_HEIGHT = 5,
  117. SVGA_REG_DEPTH = 6,
  118. SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
  119. SVGA_REG_PSEUDOCOLOR = 8,
  120. SVGA_REG_RED_MASK = 9,
  121. SVGA_REG_GREEN_MASK = 10,
  122. SVGA_REG_BLUE_MASK = 11,
  123. SVGA_REG_BYTES_PER_LINE = 12,
  124. SVGA_REG_FB_START = 13,
  125. SVGA_REG_FB_OFFSET = 14,
  126. SVGA_REG_VRAM_SIZE = 15,
  127. SVGA_REG_FB_SIZE = 16,
  128. /* ID 1 and 2 registers */
  129. SVGA_REG_CAPABILITIES = 17,
  130. SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
  131. SVGA_REG_MEM_SIZE = 19,
  132. SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
  133. SVGA_REG_SYNC = 21, /* Write to force synchronization */
  134. SVGA_REG_BUSY = 22, /* Read to check if sync is done */
  135. SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
  136. SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
  137. SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
  138. SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
  139. SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
  140. SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
  141. SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
  142. SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
  143. SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
  144. SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
  145. SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
  146. SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
  147. SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
  148. };
  149. #define SVGA_CAP_NONE 0
  150. #define SVGA_CAP_RECT_FILL (1 << 0)
  151. #define SVGA_CAP_RECT_COPY (1 << 1)
  152. #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
  153. #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
  154. #define SVGA_CAP_RASTER_OP (1 << 4)
  155. #define SVGA_CAP_CURSOR (1 << 5)
  156. #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
  157. #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
  158. #define SVGA_CAP_8BIT_EMULATION (1 << 8)
  159. #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
  160. #define SVGA_CAP_GLYPH (1 << 10)
  161. #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
  162. #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
  163. #define SVGA_CAP_ALPHA_BLEND (1 << 13)
  164. #define SVGA_CAP_3D (1 << 14)
  165. #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
  166. #define SVGA_CAP_MULTIMON (1 << 16)
  167. #define SVGA_CAP_PITCHLOCK (1 << 17)
  168. /*
  169. * FIFO offsets (seen as an array of 32-bit words)
  170. */
  171. enum {
  172. /*
  173. * The original defined FIFO offsets
  174. */
  175. SVGA_FIFO_MIN = 0,
  176. SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
  177. SVGA_FIFO_NEXT,
  178. SVGA_FIFO_STOP,
  179. /*
  180. * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
  181. */
  182. SVGA_FIFO_CAPABILITIES = 4,
  183. SVGA_FIFO_FLAGS,
  184. SVGA_FIFO_FENCE,
  185. SVGA_FIFO_3D_HWVERSION,
  186. SVGA_FIFO_PITCHLOCK,
  187. };
  188. #define SVGA_FIFO_CAP_NONE 0
  189. #define SVGA_FIFO_CAP_FENCE (1 << 0)
  190. #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
  191. #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
  192. #define SVGA_FIFO_FLAG_NONE 0
  193. #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
  194. /* These values can probably be changed arbitrarily. */
  195. #define SVGA_SCRATCH_SIZE 0x8000
  196. #define SVGA_MAX_WIDTH 2368
  197. #define SVGA_MAX_HEIGHT 1770
  198. #ifdef VERBOSE
  199. # define GUEST_OS_BASE 0x5001
  200. static const char *vmsvga_guest_id[] = {
  201. [0x00] = "Dos",
  202. [0x01] = "Windows 3.1",
  203. [0x02] = "Windows 95",
  204. [0x03] = "Windows 98",
  205. [0x04] = "Windows ME",
  206. [0x05] = "Windows NT",
  207. [0x06] = "Windows 2000",
  208. [0x07] = "Linux",
  209. [0x08] = "OS/2",
  210. [0x09] = "an unknown OS",
  211. [0x0a] = "BSD",
  212. [0x0b] = "Whistler",
  213. [0x0c] = "an unknown OS",
  214. [0x0d] = "an unknown OS",
  215. [0x0e] = "an unknown OS",
  216. [0x0f] = "an unknown OS",
  217. [0x10] = "an unknown OS",
  218. [0x11] = "an unknown OS",
  219. [0x12] = "an unknown OS",
  220. [0x13] = "an unknown OS",
  221. [0x14] = "an unknown OS",
  222. [0x15] = "Windows 2003",
  223. };
  224. #endif
  225. enum {
  226. SVGA_CMD_INVALID_CMD = 0,
  227. SVGA_CMD_UPDATE = 1,
  228. SVGA_CMD_RECT_FILL = 2,
  229. SVGA_CMD_RECT_COPY = 3,
  230. SVGA_CMD_DEFINE_BITMAP = 4,
  231. SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
  232. SVGA_CMD_DEFINE_PIXMAP = 6,
  233. SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
  234. SVGA_CMD_RECT_BITMAP_FILL = 8,
  235. SVGA_CMD_RECT_PIXMAP_FILL = 9,
  236. SVGA_CMD_RECT_BITMAP_COPY = 10,
  237. SVGA_CMD_RECT_PIXMAP_COPY = 11,
  238. SVGA_CMD_FREE_OBJECT = 12,
  239. SVGA_CMD_RECT_ROP_FILL = 13,
  240. SVGA_CMD_RECT_ROP_COPY = 14,
  241. SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
  242. SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
  243. SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
  244. SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
  245. SVGA_CMD_DEFINE_CURSOR = 19,
  246. SVGA_CMD_DISPLAY_CURSOR = 20,
  247. SVGA_CMD_MOVE_CURSOR = 21,
  248. SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
  249. SVGA_CMD_DRAW_GLYPH = 23,
  250. SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
  251. SVGA_CMD_UPDATE_VERBOSE = 25,
  252. SVGA_CMD_SURFACE_FILL = 26,
  253. SVGA_CMD_SURFACE_COPY = 27,
  254. SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
  255. SVGA_CMD_FRONT_ROP_FILL = 29,
  256. SVGA_CMD_FENCE = 30,
  257. };
  258. /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
  259. enum {
  260. SVGA_CURSOR_ON_HIDE = 0,
  261. SVGA_CURSOR_ON_SHOW = 1,
  262. SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
  263. SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
  264. };
  265. static inline bool vmsvga_verify_rect(DisplaySurface *surface,
  266. const char *name,
  267. int x, int y, int w, int h)
  268. {
  269. if (x < 0) {
  270. trace_vmware_verify_rect_less_than_zero(name, "x", x);
  271. return false;
  272. }
  273. if (x > SVGA_MAX_WIDTH) {
  274. trace_vmware_verify_rect_greater_than_bound(name, "x", SVGA_MAX_WIDTH,
  275. x);
  276. return false;
  277. }
  278. if (w < 0) {
  279. trace_vmware_verify_rect_less_than_zero(name, "w", w);
  280. return false;
  281. }
  282. if (w > SVGA_MAX_WIDTH) {
  283. trace_vmware_verify_rect_greater_than_bound(name, "w", SVGA_MAX_WIDTH,
  284. w);
  285. return false;
  286. }
  287. if (x + w > surface_width(surface)) {
  288. trace_vmware_verify_rect_surface_bound_exceeded(name, "width",
  289. surface_width(surface),
  290. "x", x, "w", w);
  291. return false;
  292. }
  293. if (y < 0) {
  294. trace_vmware_verify_rect_less_than_zero(name, "y", y);
  295. return false;
  296. }
  297. if (y > SVGA_MAX_HEIGHT) {
  298. trace_vmware_verify_rect_greater_than_bound(name, "y", SVGA_MAX_HEIGHT,
  299. y);
  300. return false;
  301. }
  302. if (h < 0) {
  303. trace_vmware_verify_rect_less_than_zero(name, "h", h);
  304. return false;
  305. }
  306. if (h > SVGA_MAX_HEIGHT) {
  307. trace_vmware_verify_rect_greater_than_bound(name, "h", SVGA_MAX_HEIGHT,
  308. h);
  309. return false;
  310. }
  311. if (y + h > surface_height(surface)) {
  312. trace_vmware_verify_rect_surface_bound_exceeded(name, "height",
  313. surface_height(surface),
  314. "y", y, "h", h);
  315. return false;
  316. }
  317. return true;
  318. }
  319. static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
  320. int x, int y, int w, int h)
  321. {
  322. DisplaySurface *surface = qemu_console_surface(s->vga.con);
  323. int line;
  324. int bypl;
  325. int width;
  326. int start;
  327. uint8_t *src;
  328. uint8_t *dst;
  329. if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
  330. /* go for a fullscreen update as fallback */
  331. x = 0;
  332. y = 0;
  333. w = surface_width(surface);
  334. h = surface_height(surface);
  335. }
  336. bypl = surface_stride(surface);
  337. width = surface_bytes_per_pixel(surface) * w;
  338. start = surface_bytes_per_pixel(surface) * x + bypl * y;
  339. src = s->vga.vram_ptr + start;
  340. dst = surface_data(surface) + start;
  341. for (line = h; line > 0; line--, src += bypl, dst += bypl) {
  342. memcpy(dst, src, width);
  343. }
  344. dpy_gfx_update(s->vga.con, x, y, w, h);
  345. }
  346. static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
  347. {
  348. struct vmsvga_rect_s *rect;
  349. if (s->invalidated) {
  350. s->redraw_fifo_last = 0;
  351. return;
  352. }
  353. /* Overlapping region updates can be optimised out here - if someone
  354. * knows a smart algorithm to do that, please share. */
  355. for (int i = 0; i < s->redraw_fifo_last; i++) {
  356. rect = &s->redraw_fifo[i];
  357. vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
  358. }
  359. s->redraw_fifo_last = 0;
  360. }
  361. static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
  362. int x, int y, int w, int h)
  363. {
  364. if (s->redraw_fifo_last >= REDRAW_FIFO_LEN) {
  365. trace_vmware_update_rect_delayed_flush();
  366. vmsvga_update_rect_flush(s);
  367. }
  368. struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
  369. rect->x = x;
  370. rect->y = y;
  371. rect->w = w;
  372. rect->h = h;
  373. }
  374. #ifdef HW_RECT_ACCEL
  375. static inline int vmsvga_copy_rect(struct vmsvga_state_s *s,
  376. int x0, int y0, int x1, int y1, int w, int h)
  377. {
  378. DisplaySurface *surface = qemu_console_surface(s->vga.con);
  379. uint8_t *vram = s->vga.vram_ptr;
  380. int bypl = surface_stride(surface);
  381. int bypp = surface_bytes_per_pixel(surface);
  382. int width = bypp * w;
  383. int line = h;
  384. uint8_t *ptr[2];
  385. if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) {
  386. return -1;
  387. }
  388. if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) {
  389. return -1;
  390. }
  391. if (y1 > y0) {
  392. ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1);
  393. ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1);
  394. for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
  395. memmove(ptr[1], ptr[0], width);
  396. }
  397. } else {
  398. ptr[0] = vram + bypp * x0 + bypl * y0;
  399. ptr[1] = vram + bypp * x1 + bypl * y1;
  400. for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
  401. memmove(ptr[1], ptr[0], width);
  402. }
  403. }
  404. vmsvga_update_rect_delayed(s, x1, y1, w, h);
  405. return 0;
  406. }
  407. #endif
  408. #ifdef HW_FILL_ACCEL
  409. static inline int vmsvga_fill_rect(struct vmsvga_state_s *s,
  410. uint32_t c, int x, int y, int w, int h)
  411. {
  412. DisplaySurface *surface = qemu_console_surface(s->vga.con);
  413. int bypl = surface_stride(surface);
  414. int width = surface_bytes_per_pixel(surface) * w;
  415. int line = h;
  416. int column;
  417. uint8_t *fst;
  418. uint8_t *dst;
  419. uint8_t *src;
  420. uint8_t col[4];
  421. if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
  422. return -1;
  423. }
  424. col[0] = c;
  425. col[1] = c >> 8;
  426. col[2] = c >> 16;
  427. col[3] = c >> 24;
  428. fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y;
  429. if (line--) {
  430. dst = fst;
  431. src = col;
  432. for (column = width; column > 0; column--) {
  433. *(dst++) = *(src++);
  434. if (src - col == surface_bytes_per_pixel(surface)) {
  435. src = col;
  436. }
  437. }
  438. dst = fst;
  439. for (; line > 0; line--) {
  440. dst += bypl;
  441. memcpy(dst, fst, width);
  442. }
  443. }
  444. vmsvga_update_rect_delayed(s, x, y, w, h);
  445. return 0;
  446. }
  447. #endif
  448. struct vmsvga_cursor_definition_s {
  449. uint32_t width;
  450. uint32_t height;
  451. int id;
  452. uint32_t bpp;
  453. int hot_x;
  454. int hot_y;
  455. uint32_t mask[1024];
  456. uint32_t image[4096];
  457. };
  458. #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
  459. #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
  460. #ifdef HW_MOUSE_ACCEL
  461. static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
  462. struct vmsvga_cursor_definition_s *c)
  463. {
  464. QEMUCursor *qc;
  465. int i, pixels;
  466. qc = cursor_alloc(c->width, c->height);
  467. assert(qc != NULL);
  468. qc->hot_x = c->hot_x;
  469. qc->hot_y = c->hot_y;
  470. switch (c->bpp) {
  471. case 1:
  472. cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
  473. 1, (void *)c->mask);
  474. #ifdef DEBUG
  475. cursor_print_ascii_art(qc, "vmware/mono");
  476. #endif
  477. break;
  478. case 32:
  479. /* fill alpha channel from mask, set color to zero */
  480. cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
  481. 1, (void *)c->mask);
  482. /* add in rgb values */
  483. pixels = c->width * c->height;
  484. for (i = 0; i < pixels; i++) {
  485. qc->data[i] |= c->image[i] & 0xffffff;
  486. }
  487. #ifdef DEBUG
  488. cursor_print_ascii_art(qc, "vmware/32bit");
  489. #endif
  490. break;
  491. default:
  492. fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
  493. __func__, c->bpp);
  494. cursor_unref(qc);
  495. qc = cursor_builtin_left_ptr();
  496. }
  497. dpy_cursor_define(s->vga.con, qc);
  498. cursor_unref(qc);
  499. }
  500. #endif
  501. static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
  502. {
  503. int num;
  504. if (!s->config || !s->enable) {
  505. return 0;
  506. }
  507. s->fifo_min = le32_to_cpu(s->fifo[SVGA_FIFO_MIN]);
  508. s->fifo_max = le32_to_cpu(s->fifo[SVGA_FIFO_MAX]);
  509. s->fifo_next = le32_to_cpu(s->fifo[SVGA_FIFO_NEXT]);
  510. s->fifo_stop = le32_to_cpu(s->fifo[SVGA_FIFO_STOP]);
  511. /* Check range and alignment. */
  512. if ((s->fifo_min | s->fifo_max | s->fifo_next | s->fifo_stop) & 3) {
  513. return 0;
  514. }
  515. if (s->fifo_min < sizeof(uint32_t) * 4) {
  516. return 0;
  517. }
  518. if (s->fifo_max > SVGA_FIFO_SIZE ||
  519. s->fifo_min >= SVGA_FIFO_SIZE ||
  520. s->fifo_stop >= SVGA_FIFO_SIZE ||
  521. s->fifo_next >= SVGA_FIFO_SIZE) {
  522. return 0;
  523. }
  524. if (s->fifo_max < s->fifo_min + 10 * KiB) {
  525. return 0;
  526. }
  527. num = s->fifo_next - s->fifo_stop;
  528. if (num < 0) {
  529. num += s->fifo_max - s->fifo_min;
  530. }
  531. return num >> 2;
  532. }
  533. static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
  534. {
  535. uint32_t cmd = s->fifo[s->fifo_stop >> 2];
  536. s->fifo_stop += 4;
  537. if (s->fifo_stop >= s->fifo_max) {
  538. s->fifo_stop = s->fifo_min;
  539. }
  540. s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop);
  541. return cmd;
  542. }
  543. static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
  544. {
  545. return le32_to_cpu(vmsvga_fifo_read_raw(s));
  546. }
  547. static void vmsvga_fifo_run(struct vmsvga_state_s *s)
  548. {
  549. uint32_t cmd, colour;
  550. int args, len, maxloop = 1024;
  551. int x, y, dx, dy, width, height;
  552. struct vmsvga_cursor_definition_s cursor;
  553. uint32_t cmd_start;
  554. len = vmsvga_fifo_length(s);
  555. while (len > 0 && --maxloop > 0) {
  556. /* May need to go back to the start of the command if incomplete */
  557. cmd_start = s->fifo_stop;
  558. switch (cmd = vmsvga_fifo_read(s)) {
  559. case SVGA_CMD_UPDATE:
  560. case SVGA_CMD_UPDATE_VERBOSE:
  561. len -= 5;
  562. if (len < 0) {
  563. goto rewind;
  564. }
  565. x = vmsvga_fifo_read(s);
  566. y = vmsvga_fifo_read(s);
  567. width = vmsvga_fifo_read(s);
  568. height = vmsvga_fifo_read(s);
  569. vmsvga_update_rect_delayed(s, x, y, width, height);
  570. break;
  571. case SVGA_CMD_RECT_FILL:
  572. len -= 6;
  573. if (len < 0) {
  574. goto rewind;
  575. }
  576. colour = vmsvga_fifo_read(s);
  577. x = vmsvga_fifo_read(s);
  578. y = vmsvga_fifo_read(s);
  579. width = vmsvga_fifo_read(s);
  580. height = vmsvga_fifo_read(s);
  581. #ifdef HW_FILL_ACCEL
  582. if (vmsvga_fill_rect(s, colour, x, y, width, height) == 0) {
  583. break;
  584. }
  585. #endif
  586. args = 0;
  587. goto badcmd;
  588. case SVGA_CMD_RECT_COPY:
  589. len -= 7;
  590. if (len < 0) {
  591. goto rewind;
  592. }
  593. x = vmsvga_fifo_read(s);
  594. y = vmsvga_fifo_read(s);
  595. dx = vmsvga_fifo_read(s);
  596. dy = vmsvga_fifo_read(s);
  597. width = vmsvga_fifo_read(s);
  598. height = vmsvga_fifo_read(s);
  599. #ifdef HW_RECT_ACCEL
  600. if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) {
  601. break;
  602. }
  603. #endif
  604. args = 0;
  605. goto badcmd;
  606. case SVGA_CMD_DEFINE_CURSOR:
  607. len -= 8;
  608. if (len < 0) {
  609. goto rewind;
  610. }
  611. cursor.id = vmsvga_fifo_read(s);
  612. cursor.hot_x = vmsvga_fifo_read(s);
  613. cursor.hot_y = vmsvga_fifo_read(s);
  614. cursor.width = x = vmsvga_fifo_read(s);
  615. cursor.height = y = vmsvga_fifo_read(s);
  616. vmsvga_fifo_read(s);
  617. cursor.bpp = vmsvga_fifo_read(s);
  618. args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
  619. if (cursor.width > 256
  620. || cursor.height > 256
  621. || cursor.bpp > 32
  622. || SVGA_BITMAP_SIZE(x, y) > ARRAY_SIZE(cursor.mask)
  623. || SVGA_PIXMAP_SIZE(x, y, cursor.bpp)
  624. > ARRAY_SIZE(cursor.image)) {
  625. goto badcmd;
  626. }
  627. len -= args;
  628. if (len < 0) {
  629. goto rewind;
  630. }
  631. for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
  632. cursor.mask[args] = vmsvga_fifo_read_raw(s);
  633. }
  634. for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
  635. cursor.image[args] = vmsvga_fifo_read_raw(s);
  636. }
  637. #ifdef HW_MOUSE_ACCEL
  638. vmsvga_cursor_define(s, &cursor);
  639. break;
  640. #else
  641. args = 0;
  642. goto badcmd;
  643. #endif
  644. /*
  645. * Other commands that we at least know the number of arguments
  646. * for so we can avoid FIFO desync if driver uses them illegally.
  647. */
  648. case SVGA_CMD_DEFINE_ALPHA_CURSOR:
  649. len -= 6;
  650. if (len < 0) {
  651. goto rewind;
  652. }
  653. vmsvga_fifo_read(s);
  654. vmsvga_fifo_read(s);
  655. vmsvga_fifo_read(s);
  656. x = vmsvga_fifo_read(s);
  657. y = vmsvga_fifo_read(s);
  658. args = x * y;
  659. goto badcmd;
  660. case SVGA_CMD_RECT_ROP_FILL:
  661. args = 6;
  662. goto badcmd;
  663. case SVGA_CMD_RECT_ROP_COPY:
  664. args = 7;
  665. goto badcmd;
  666. case SVGA_CMD_DRAW_GLYPH_CLIPPED:
  667. len -= 4;
  668. if (len < 0) {
  669. goto rewind;
  670. }
  671. vmsvga_fifo_read(s);
  672. vmsvga_fifo_read(s);
  673. args = 7 + (vmsvga_fifo_read(s) >> 2);
  674. goto badcmd;
  675. case SVGA_CMD_SURFACE_ALPHA_BLEND:
  676. args = 12;
  677. goto badcmd;
  678. /*
  679. * Other commands that are not listed as depending on any
  680. * CAPABILITIES bits, but are not described in the README either.
  681. */
  682. case SVGA_CMD_SURFACE_FILL:
  683. case SVGA_CMD_SURFACE_COPY:
  684. case SVGA_CMD_FRONT_ROP_FILL:
  685. case SVGA_CMD_FENCE:
  686. case SVGA_CMD_INVALID_CMD:
  687. break; /* Nop */
  688. default:
  689. args = 0;
  690. badcmd:
  691. len -= args;
  692. if (len < 0) {
  693. goto rewind;
  694. }
  695. while (args--) {
  696. vmsvga_fifo_read(s);
  697. }
  698. printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
  699. __func__, cmd);
  700. break;
  701. rewind:
  702. s->fifo_stop = cmd_start;
  703. s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop);
  704. break;
  705. }
  706. }
  707. s->syncing = 0;
  708. }
  709. static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
  710. {
  711. struct vmsvga_state_s *s = opaque;
  712. return s->index;
  713. }
  714. static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
  715. {
  716. struct vmsvga_state_s *s = opaque;
  717. s->index = index;
  718. }
  719. static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
  720. {
  721. uint32_t caps;
  722. struct vmsvga_state_s *s = opaque;
  723. DisplaySurface *surface = qemu_console_surface(s->vga.con);
  724. PixelFormat pf;
  725. uint32_t ret;
  726. switch (s->index) {
  727. case SVGA_REG_ID:
  728. ret = s->svgaid;
  729. break;
  730. case SVGA_REG_ENABLE:
  731. ret = s->enable;
  732. break;
  733. case SVGA_REG_WIDTH:
  734. ret = s->new_width ? s->new_width : surface_width(surface);
  735. break;
  736. case SVGA_REG_HEIGHT:
  737. ret = s->new_height ? s->new_height : surface_height(surface);
  738. break;
  739. case SVGA_REG_MAX_WIDTH:
  740. ret = SVGA_MAX_WIDTH;
  741. break;
  742. case SVGA_REG_MAX_HEIGHT:
  743. ret = SVGA_MAX_HEIGHT;
  744. break;
  745. case SVGA_REG_DEPTH:
  746. ret = (s->new_depth == 32) ? 24 : s->new_depth;
  747. break;
  748. case SVGA_REG_BITS_PER_PIXEL:
  749. case SVGA_REG_HOST_BITS_PER_PIXEL:
  750. ret = s->new_depth;
  751. break;
  752. case SVGA_REG_PSEUDOCOLOR:
  753. ret = 0x0;
  754. break;
  755. case SVGA_REG_RED_MASK:
  756. pf = qemu_default_pixelformat(s->new_depth);
  757. ret = pf.rmask;
  758. break;
  759. case SVGA_REG_GREEN_MASK:
  760. pf = qemu_default_pixelformat(s->new_depth);
  761. ret = pf.gmask;
  762. break;
  763. case SVGA_REG_BLUE_MASK:
  764. pf = qemu_default_pixelformat(s->new_depth);
  765. ret = pf.bmask;
  766. break;
  767. case SVGA_REG_BYTES_PER_LINE:
  768. if (s->new_width) {
  769. ret = (s->new_depth * s->new_width) / 8;
  770. } else {
  771. ret = surface_stride(surface);
  772. }
  773. break;
  774. case SVGA_REG_FB_START: {
  775. struct pci_vmsvga_state_s *pci_vmsvga
  776. = container_of(s, struct pci_vmsvga_state_s, chip);
  777. ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1);
  778. break;
  779. }
  780. case SVGA_REG_FB_OFFSET:
  781. ret = 0x0;
  782. break;
  783. case SVGA_REG_VRAM_SIZE:
  784. ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */
  785. break;
  786. case SVGA_REG_FB_SIZE:
  787. ret = s->vga.vram_size;
  788. break;
  789. case SVGA_REG_CAPABILITIES:
  790. caps = SVGA_CAP_NONE;
  791. #ifdef HW_RECT_ACCEL
  792. caps |= SVGA_CAP_RECT_COPY;
  793. #endif
  794. #ifdef HW_FILL_ACCEL
  795. caps |= SVGA_CAP_RECT_FILL;
  796. #endif
  797. #ifdef HW_MOUSE_ACCEL
  798. caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
  799. SVGA_CAP_CURSOR_BYPASS;
  800. #endif
  801. ret = caps;
  802. break;
  803. case SVGA_REG_MEM_START: {
  804. struct pci_vmsvga_state_s *pci_vmsvga
  805. = container_of(s, struct pci_vmsvga_state_s, chip);
  806. ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2);
  807. break;
  808. }
  809. case SVGA_REG_MEM_SIZE:
  810. ret = s->fifo_size;
  811. break;
  812. case SVGA_REG_CONFIG_DONE:
  813. ret = s->config;
  814. break;
  815. case SVGA_REG_SYNC:
  816. case SVGA_REG_BUSY:
  817. ret = s->syncing;
  818. break;
  819. case SVGA_REG_GUEST_ID:
  820. ret = s->guest;
  821. break;
  822. case SVGA_REG_CURSOR_ID:
  823. ret = s->cursor.id;
  824. break;
  825. case SVGA_REG_CURSOR_X:
  826. ret = s->cursor.x;
  827. break;
  828. case SVGA_REG_CURSOR_Y:
  829. ret = s->cursor.y;
  830. break;
  831. case SVGA_REG_CURSOR_ON:
  832. ret = s->cursor.on;
  833. break;
  834. case SVGA_REG_SCRATCH_SIZE:
  835. ret = s->scratch_size;
  836. break;
  837. case SVGA_REG_MEM_REGS:
  838. case SVGA_REG_NUM_DISPLAYS:
  839. case SVGA_REG_PITCHLOCK:
  840. case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
  841. ret = 0;
  842. break;
  843. default:
  844. if (s->index >= SVGA_SCRATCH_BASE &&
  845. s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
  846. ret = s->scratch[s->index - SVGA_SCRATCH_BASE];
  847. break;
  848. }
  849. qemu_log_mask(LOG_GUEST_ERROR,
  850. "%s: Bad register %02x\n", __func__, s->index);
  851. ret = 0;
  852. break;
  853. }
  854. if (s->index >= SVGA_SCRATCH_BASE) {
  855. trace_vmware_scratch_read(s->index, ret);
  856. } else if (s->index >= SVGA_PALETTE_BASE) {
  857. trace_vmware_palette_read(s->index, ret);
  858. } else {
  859. trace_vmware_value_read(s->index, ret);
  860. }
  861. return ret;
  862. }
  863. static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
  864. {
  865. struct vmsvga_state_s *s = opaque;
  866. if (s->index >= SVGA_SCRATCH_BASE) {
  867. trace_vmware_scratch_write(s->index, value);
  868. } else if (s->index >= SVGA_PALETTE_BASE) {
  869. trace_vmware_palette_write(s->index, value);
  870. } else {
  871. trace_vmware_value_write(s->index, value);
  872. }
  873. switch (s->index) {
  874. case SVGA_REG_ID:
  875. if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
  876. s->svgaid = value;
  877. }
  878. break;
  879. case SVGA_REG_ENABLE:
  880. s->enable = !!value;
  881. s->invalidated = 1;
  882. s->vga.hw_ops->invalidate(&s->vga);
  883. if (s->enable && s->config) {
  884. vga_dirty_log_stop(&s->vga);
  885. } else {
  886. vga_dirty_log_start(&s->vga);
  887. }
  888. break;
  889. case SVGA_REG_WIDTH:
  890. if (value <= SVGA_MAX_WIDTH) {
  891. s->new_width = value;
  892. s->invalidated = 1;
  893. } else {
  894. qemu_log_mask(LOG_GUEST_ERROR,
  895. "%s: Bad width: %i\n", __func__, value);
  896. }
  897. break;
  898. case SVGA_REG_HEIGHT:
  899. if (value <= SVGA_MAX_HEIGHT) {
  900. s->new_height = value;
  901. s->invalidated = 1;
  902. } else {
  903. qemu_log_mask(LOG_GUEST_ERROR,
  904. "%s: Bad height: %i\n", __func__, value);
  905. }
  906. break;
  907. case SVGA_REG_BITS_PER_PIXEL:
  908. if (value != 32) {
  909. qemu_log_mask(LOG_GUEST_ERROR,
  910. "%s: Bad bits per pixel: %i bits\n", __func__, value);
  911. s->config = 0;
  912. s->invalidated = 1;
  913. }
  914. break;
  915. case SVGA_REG_CONFIG_DONE:
  916. if (value) {
  917. s->fifo = (uint32_t *) s->fifo_ptr;
  918. vga_dirty_log_stop(&s->vga);
  919. }
  920. s->config = !!value;
  921. break;
  922. case SVGA_REG_SYNC:
  923. s->syncing = 1;
  924. vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
  925. break;
  926. case SVGA_REG_GUEST_ID:
  927. s->guest = value;
  928. #ifdef VERBOSE
  929. if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
  930. ARRAY_SIZE(vmsvga_guest_id)) {
  931. printf("%s: guest runs %s.\n", __func__,
  932. vmsvga_guest_id[value - GUEST_OS_BASE]);
  933. }
  934. #endif
  935. break;
  936. case SVGA_REG_CURSOR_ID:
  937. s->cursor.id = value;
  938. break;
  939. case SVGA_REG_CURSOR_X:
  940. s->cursor.x = value;
  941. break;
  942. case SVGA_REG_CURSOR_Y:
  943. s->cursor.y = value;
  944. break;
  945. case SVGA_REG_CURSOR_ON:
  946. s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
  947. s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
  948. #ifdef HW_MOUSE_ACCEL
  949. if (value <= SVGA_CURSOR_ON_SHOW) {
  950. dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on);
  951. }
  952. #endif
  953. break;
  954. case SVGA_REG_DEPTH:
  955. case SVGA_REG_MEM_REGS:
  956. case SVGA_REG_NUM_DISPLAYS:
  957. case SVGA_REG_PITCHLOCK:
  958. case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
  959. break;
  960. default:
  961. if (s->index >= SVGA_SCRATCH_BASE &&
  962. s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
  963. s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
  964. break;
  965. }
  966. qemu_log_mask(LOG_GUEST_ERROR,
  967. "%s: Bad register %02x\n", __func__, s->index);
  968. }
  969. }
  970. static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
  971. {
  972. printf("%s: what are we supposed to return?\n", __func__);
  973. return 0xcafe;
  974. }
  975. static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
  976. {
  977. printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
  978. }
  979. static inline void vmsvga_check_size(struct vmsvga_state_s *s)
  980. {
  981. DisplaySurface *surface = qemu_console_surface(s->vga.con);
  982. if (s->new_width != surface_width(surface) ||
  983. s->new_height != surface_height(surface) ||
  984. s->new_depth != surface_bits_per_pixel(surface)) {
  985. int stride = (s->new_depth * s->new_width) / 8;
  986. pixman_format_code_t format =
  987. qemu_default_pixman_format(s->new_depth, true);
  988. trace_vmware_setmode(s->new_width, s->new_height, s->new_depth);
  989. surface = qemu_create_displaysurface_from(s->new_width, s->new_height,
  990. format, stride,
  991. s->vga.vram_ptr);
  992. dpy_gfx_replace_surface(s->vga.con, surface);
  993. s->invalidated = 1;
  994. }
  995. }
  996. static void vmsvga_update_display(void *opaque)
  997. {
  998. struct vmsvga_state_s *s = opaque;
  999. if (!s->enable || !s->config) {
  1000. /* in standard vga mode */
  1001. s->vga.hw_ops->gfx_update(&s->vga);
  1002. return;
  1003. }
  1004. vmsvga_check_size(s);
  1005. vmsvga_fifo_run(s);
  1006. vmsvga_update_rect_flush(s);
  1007. if (s->invalidated) {
  1008. s->invalidated = 0;
  1009. dpy_gfx_update_full(s->vga.con);
  1010. }
  1011. }
  1012. static void vmsvga_reset(DeviceState *dev)
  1013. {
  1014. struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev);
  1015. struct vmsvga_state_s *s = &pci->chip;
  1016. s->index = 0;
  1017. s->enable = 0;
  1018. s->config = 0;
  1019. s->svgaid = SVGA_ID;
  1020. s->cursor.on = false;
  1021. s->redraw_fifo_last = 0;
  1022. s->syncing = 0;
  1023. vga_dirty_log_start(&s->vga);
  1024. }
  1025. static void vmsvga_invalidate_display(void *opaque)
  1026. {
  1027. struct vmsvga_state_s *s = opaque;
  1028. if (!s->enable) {
  1029. s->vga.hw_ops->invalidate(&s->vga);
  1030. return;
  1031. }
  1032. s->invalidated = 1;
  1033. }
  1034. static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
  1035. {
  1036. struct vmsvga_state_s *s = opaque;
  1037. if (s->vga.hw_ops->text_update) {
  1038. s->vga.hw_ops->text_update(&s->vga, chardata);
  1039. }
  1040. }
  1041. static int vmsvga_post_load(void *opaque, int version_id)
  1042. {
  1043. struct vmsvga_state_s *s = opaque;
  1044. s->invalidated = 1;
  1045. if (s->config) {
  1046. s->fifo = (uint32_t *) s->fifo_ptr;
  1047. }
  1048. return 0;
  1049. }
  1050. static const VMStateDescription vmstate_vmware_vga_internal = {
  1051. .name = "vmware_vga_internal",
  1052. .version_id = 0,
  1053. .minimum_version_id = 0,
  1054. .post_load = vmsvga_post_load,
  1055. .fields = (const VMStateField[]) {
  1056. VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s, NULL),
  1057. VMSTATE_INT32(enable, struct vmsvga_state_s),
  1058. VMSTATE_INT32(config, struct vmsvga_state_s),
  1059. VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
  1060. VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
  1061. VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
  1062. VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
  1063. VMSTATE_INT32(index, struct vmsvga_state_s),
  1064. VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
  1065. scratch_size, 0, vmstate_info_uint32, uint32_t),
  1066. VMSTATE_INT32(new_width, struct vmsvga_state_s),
  1067. VMSTATE_INT32(new_height, struct vmsvga_state_s),
  1068. VMSTATE_UINT32(guest, struct vmsvga_state_s),
  1069. VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
  1070. VMSTATE_INT32(syncing, struct vmsvga_state_s),
  1071. VMSTATE_UNUSED(4), /* was fb_size */
  1072. VMSTATE_END_OF_LIST()
  1073. }
  1074. };
  1075. static const VMStateDescription vmstate_vmware_vga = {
  1076. .name = "vmware_vga",
  1077. .version_id = 0,
  1078. .minimum_version_id = 0,
  1079. .fields = (const VMStateField[]) {
  1080. VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s),
  1081. VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
  1082. vmstate_vmware_vga_internal, struct vmsvga_state_s),
  1083. VMSTATE_END_OF_LIST()
  1084. }
  1085. };
  1086. static const GraphicHwOps vmsvga_ops = {
  1087. .invalidate = vmsvga_invalidate_display,
  1088. .gfx_update = vmsvga_update_display,
  1089. .text_update = vmsvga_text_update,
  1090. };
  1091. static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s,
  1092. MemoryRegion *address_space, MemoryRegion *io)
  1093. {
  1094. s->scratch_size = SVGA_SCRATCH_SIZE;
  1095. s->scratch = g_malloc(s->scratch_size * 4);
  1096. s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s);
  1097. s->fifo_size = SVGA_FIFO_SIZE;
  1098. memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size,
  1099. &error_fatal);
  1100. s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
  1101. vga_common_init(&s->vga, OBJECT(dev), &error_fatal);
  1102. vga_init(&s->vga, OBJECT(dev), address_space, io, true);
  1103. vmstate_register_any(NULL, &vmstate_vga_common, &s->vga);
  1104. s->new_depth = 32;
  1105. }
  1106. static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
  1107. {
  1108. struct vmsvga_state_s *s = opaque;
  1109. switch (addr) {
  1110. case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
  1111. case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
  1112. case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
  1113. default: return -1u;
  1114. }
  1115. }
  1116. static void vmsvga_io_write(void *opaque, hwaddr addr,
  1117. uint64_t data, unsigned size)
  1118. {
  1119. struct vmsvga_state_s *s = opaque;
  1120. switch (addr) {
  1121. case SVGA_IO_MUL * SVGA_INDEX_PORT:
  1122. vmsvga_index_write(s, addr, data);
  1123. break;
  1124. case SVGA_IO_MUL * SVGA_VALUE_PORT:
  1125. vmsvga_value_write(s, addr, data);
  1126. break;
  1127. case SVGA_IO_MUL * SVGA_BIOS_PORT:
  1128. vmsvga_bios_write(s, addr, data);
  1129. break;
  1130. }
  1131. }
  1132. static const MemoryRegionOps vmsvga_io_ops = {
  1133. .read = vmsvga_io_read,
  1134. .write = vmsvga_io_write,
  1135. .endianness = DEVICE_LITTLE_ENDIAN,
  1136. .valid = {
  1137. .min_access_size = 4,
  1138. .max_access_size = 4,
  1139. .unaligned = true,
  1140. },
  1141. .impl = {
  1142. .unaligned = true,
  1143. },
  1144. };
  1145. static void pci_vmsvga_realize(PCIDevice *dev, Error **errp)
  1146. {
  1147. struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
  1148. dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
  1149. dev->config[PCI_LATENCY_TIMER] = 0x40;
  1150. dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */
  1151. memory_region_init_io(&s->io_bar, OBJECT(dev), &vmsvga_io_ops, &s->chip,
  1152. "vmsvga-io", 0x10);
  1153. memory_region_set_flush_coalesced(&s->io_bar);
  1154. pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
  1155. vmsvga_init(DEVICE(dev), &s->chip,
  1156. pci_address_space(dev), pci_address_space_io(dev));
  1157. pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
  1158. &s->chip.vga.vram);
  1159. pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
  1160. &s->chip.fifo_ram);
  1161. }
  1162. static const Property vga_vmware_properties[] = {
  1163. DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
  1164. chip.vga.vram_size_mb, 16),
  1165. DEFINE_PROP_BOOL("global-vmstate", struct pci_vmsvga_state_s,
  1166. chip.vga.global_vmstate, false),
  1167. };
  1168. static void vmsvga_class_init(ObjectClass *klass, void *data)
  1169. {
  1170. DeviceClass *dc = DEVICE_CLASS(klass);
  1171. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  1172. k->realize = pci_vmsvga_realize;
  1173. k->romfile = "vgabios-vmware.bin";
  1174. k->vendor_id = PCI_VENDOR_ID_VMWARE;
  1175. k->device_id = SVGA_PCI_DEVICE_ID;
  1176. k->class_id = PCI_CLASS_DISPLAY_VGA;
  1177. k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
  1178. k->subsystem_id = SVGA_PCI_DEVICE_ID;
  1179. device_class_set_legacy_reset(dc, vmsvga_reset);
  1180. dc->vmsd = &vmstate_vmware_vga;
  1181. device_class_set_props(dc, vga_vmware_properties);
  1182. dc->hotpluggable = false;
  1183. set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
  1184. }
  1185. static const TypeInfo vmsvga_info = {
  1186. .name = TYPE_VMWARE_SVGA,
  1187. .parent = TYPE_PCI_DEVICE,
  1188. .instance_size = sizeof(struct pci_vmsvga_state_s),
  1189. .class_init = vmsvga_class_init,
  1190. .interfaces = (InterfaceInfo[]) {
  1191. { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  1192. { },
  1193. },
  1194. };
  1195. static void vmsvga_register_types(void)
  1196. {
  1197. type_register_static(&vmsvga_info);
  1198. }
  1199. type_init(vmsvga_register_types)