2
0

vga.c 71 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352
  1. /*
  2. * QEMU VGA Emulator.
  3. *
  4. * Copyright (c) 2003 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "qemu/osdep.h"
  25. #include "qemu/units.h"
  26. #include "system/reset.h"
  27. #include "qapi/error.h"
  28. #include "exec/tswap.h"
  29. #include "hw/display/vga.h"
  30. #include "hw/i386/x86.h"
  31. #include "hw/pci/pci.h"
  32. #include "vga_int.h"
  33. #include "vga_regs.h"
  34. #include "ui/pixel_ops.h"
  35. #include "ui/console.h"
  36. #include "qemu/timer.h"
  37. #include "hw/xen/xen.h"
  38. #include "migration/vmstate.h"
  39. #include "trace.h"
  40. //#define DEBUG_VGA_MEM
  41. //#define DEBUG_VGA_REG
  42. bool have_vga = true;
  43. /* 16 state changes per vertical frame @60 Hz */
  44. #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
  45. /* Address mask for non-VESA modes. */
  46. #define VGA_VRAM_SIZE (256 * KiB)
  47. /* This value corresponds to a shift of zero pixels
  48. * in 9-dot text mode. In other modes, bit 3 is undefined;
  49. * we just ignore it, so that 8 corresponds to zero pixels
  50. * in all modes.
  51. */
  52. #define VGA_HPEL_NEUTRAL 8
  53. /*
  54. * Video Graphics Array (VGA)
  55. *
  56. * Chipset docs for original IBM VGA:
  57. * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
  58. *
  59. * FreeVGA site:
  60. * http://www.osdever.net/FreeVGA/home.htm
  61. *
  62. * Standard VGA features and Bochs VBE extensions are implemented.
  63. */
  64. /* force some bits to zero */
  65. const uint8_t sr_mask[8] = {
  66. 0x03,
  67. 0x3d,
  68. 0x0f,
  69. 0x3f,
  70. 0x0e,
  71. 0x00,
  72. 0x00,
  73. 0xff,
  74. };
  75. const uint8_t gr_mask[16] = {
  76. 0x0f, /* 0x00 */
  77. 0x0f, /* 0x01 */
  78. 0x0f, /* 0x02 */
  79. 0x1f, /* 0x03 */
  80. 0x03, /* 0x04 */
  81. 0x7b, /* 0x05 */
  82. 0x0f, /* 0x06 */
  83. 0x0f, /* 0x07 */
  84. 0xff, /* 0x08 */
  85. 0x00, /* 0x09 */
  86. 0x00, /* 0x0a */
  87. 0x00, /* 0x0b */
  88. 0x00, /* 0x0c */
  89. 0x00, /* 0x0d */
  90. 0x00, /* 0x0e */
  91. 0x00, /* 0x0f */
  92. };
  93. #define GET_PLANE(data, p) ((cpu_to_le32(data) >> ((p) * 8)) & 0xff)
  94. static const uint32_t mask16[16] = {
  95. const_le32(0x00000000),
  96. const_le32(0x000000ff),
  97. const_le32(0x0000ff00),
  98. const_le32(0x0000ffff),
  99. const_le32(0x00ff0000),
  100. const_le32(0x00ff00ff),
  101. const_le32(0x00ffff00),
  102. const_le32(0x00ffffff),
  103. const_le32(0xff000000),
  104. const_le32(0xff0000ff),
  105. const_le32(0xff00ff00),
  106. const_le32(0xff00ffff),
  107. const_le32(0xffff0000),
  108. const_le32(0xffff00ff),
  109. const_le32(0xffffff00),
  110. const_le32(0xffffffff),
  111. };
  112. static uint32_t expand4[256];
  113. static uint16_t expand2[256];
  114. static uint8_t expand4to8[16];
  115. static void vbe_update_vgaregs(VGACommonState *s);
  116. static inline bool vbe_enabled(VGACommonState *s)
  117. {
  118. return s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED;
  119. }
  120. static inline uint8_t sr(VGACommonState *s, int idx)
  121. {
  122. return vbe_enabled(s) ? s->sr_vbe[idx] : s->sr[idx];
  123. }
  124. static void vga_update_memory_access(VGACommonState *s)
  125. {
  126. hwaddr base, offset, size;
  127. if (s->legacy_address_space == NULL) {
  128. return;
  129. }
  130. if (s->has_chain4_alias) {
  131. memory_region_del_subregion(s->legacy_address_space, &s->chain4_alias);
  132. object_unparent(OBJECT(&s->chain4_alias));
  133. s->has_chain4_alias = false;
  134. s->plane_updated = 0xf;
  135. }
  136. if ((sr(s, VGA_SEQ_PLANE_WRITE) & VGA_SR02_ALL_PLANES) ==
  137. VGA_SR02_ALL_PLANES && sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
  138. offset = 0;
  139. switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
  140. case 0:
  141. base = 0xa0000;
  142. size = 0x20000;
  143. break;
  144. case 1:
  145. base = 0xa0000;
  146. size = 0x10000;
  147. offset = s->bank_offset;
  148. break;
  149. case 2:
  150. base = 0xb0000;
  151. size = 0x8000;
  152. break;
  153. case 3:
  154. default:
  155. base = 0xb8000;
  156. size = 0x8000;
  157. break;
  158. }
  159. assert(offset + size <= s->vram_size);
  160. memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram),
  161. "vga.chain4", &s->vram, offset, size);
  162. memory_region_add_subregion_overlap(s->legacy_address_space, base,
  163. &s->chain4_alias, 2);
  164. s->has_chain4_alias = true;
  165. }
  166. }
  167. static void vga_dumb_update_retrace_info(VGACommonState *s)
  168. {
  169. (void) s;
  170. }
  171. static void vga_precise_update_retrace_info(VGACommonState *s)
  172. {
  173. int htotal_chars;
  174. int hretr_start_char;
  175. int hretr_skew_chars;
  176. int hretr_end_char;
  177. int vtotal_lines;
  178. int vretr_start_line;
  179. int vretr_end_line;
  180. int dots;
  181. #if 0
  182. int div2, sldiv2;
  183. #endif
  184. int clocking_mode;
  185. int clock_sel;
  186. const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
  187. int64_t chars_per_sec;
  188. struct vga_precise_retrace *r = &s->retrace_info.precise;
  189. htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
  190. hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
  191. hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
  192. hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
  193. vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
  194. (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
  195. ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
  196. vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
  197. ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
  198. ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
  199. vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
  200. clocking_mode = (sr(s, VGA_SEQ_CLOCK_MODE) >> 3) & 1;
  201. clock_sel = (s->msr >> 2) & 3;
  202. dots = (s->msr & 1) ? 8 : 9;
  203. chars_per_sec = clk_hz[clock_sel] / dots;
  204. htotal_chars <<= clocking_mode;
  205. r->total_chars = vtotal_lines * htotal_chars;
  206. if (r->freq) {
  207. r->ticks_per_char = NANOSECONDS_PER_SECOND / (r->total_chars * r->freq);
  208. } else {
  209. r->ticks_per_char = NANOSECONDS_PER_SECOND / chars_per_sec;
  210. }
  211. r->vstart = vretr_start_line;
  212. r->vend = r->vstart + vretr_end_line + 1;
  213. r->hstart = hretr_start_char + hretr_skew_chars;
  214. r->hend = r->hstart + hretr_end_char + 1;
  215. r->htotal = htotal_chars;
  216. #if 0
  217. div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
  218. sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
  219. printf (
  220. "hz=%f\n"
  221. "htotal = %d\n"
  222. "hretr_start = %d\n"
  223. "hretr_skew = %d\n"
  224. "hretr_end = %d\n"
  225. "vtotal = %d\n"
  226. "vretr_start = %d\n"
  227. "vretr_end = %d\n"
  228. "div2 = %d sldiv2 = %d\n"
  229. "clocking_mode = %d\n"
  230. "clock_sel = %d %d\n"
  231. "dots = %d\n"
  232. "ticks/char = %" PRId64 "\n"
  233. "\n",
  234. (double) NANOSECONDS_PER_SECOND / (r->ticks_per_char * r->total_chars),
  235. htotal_chars,
  236. hretr_start_char,
  237. hretr_skew_chars,
  238. hretr_end_char,
  239. vtotal_lines,
  240. vretr_start_line,
  241. vretr_end_line,
  242. div2, sldiv2,
  243. clocking_mode,
  244. clock_sel,
  245. clk_hz[clock_sel],
  246. dots,
  247. r->ticks_per_char
  248. );
  249. #endif
  250. }
  251. static uint8_t vga_precise_retrace(VGACommonState *s)
  252. {
  253. struct vga_precise_retrace *r = &s->retrace_info.precise;
  254. uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
  255. if (r->total_chars) {
  256. int cur_line, cur_line_char, cur_char;
  257. int64_t cur_tick;
  258. cur_tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  259. cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
  260. cur_line = cur_char / r->htotal;
  261. if (cur_line >= r->vstart && cur_line <= r->vend) {
  262. val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
  263. } else {
  264. cur_line_char = cur_char % r->htotal;
  265. if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
  266. val |= ST01_DISP_ENABLE;
  267. }
  268. }
  269. return val;
  270. } else {
  271. return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
  272. }
  273. }
  274. static uint8_t vga_dumb_retrace(VGACommonState *s)
  275. {
  276. return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
  277. }
  278. int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
  279. {
  280. if (s->msr & VGA_MIS_COLOR) {
  281. /* Color */
  282. return (addr >= 0x3b0 && addr <= 0x3bf);
  283. } else {
  284. /* Monochrome */
  285. return (addr >= 0x3d0 && addr <= 0x3df);
  286. }
  287. }
  288. uint32_t vga_ioport_read(void *opaque, uint32_t addr)
  289. {
  290. VGACommonState *s = opaque;
  291. int val, index;
  292. if (vga_ioport_invalid(s, addr)) {
  293. val = 0xff;
  294. } else {
  295. switch(addr) {
  296. case VGA_ATT_W:
  297. if (s->ar_flip_flop == 0) {
  298. val = s->ar_index;
  299. } else {
  300. val = 0;
  301. }
  302. break;
  303. case VGA_ATT_R:
  304. index = s->ar_index & 0x1f;
  305. if (index < VGA_ATT_C) {
  306. val = s->ar[index];
  307. } else {
  308. val = 0;
  309. }
  310. break;
  311. case VGA_MIS_W:
  312. val = s->st00;
  313. break;
  314. case VGA_SEQ_I:
  315. val = s->sr_index;
  316. break;
  317. case VGA_SEQ_D:
  318. val = s->sr[s->sr_index];
  319. #ifdef DEBUG_VGA_REG
  320. printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
  321. #endif
  322. break;
  323. case VGA_PEL_IR:
  324. val = s->dac_state;
  325. break;
  326. case VGA_PEL_IW:
  327. val = s->dac_write_index;
  328. break;
  329. case VGA_PEL_D:
  330. val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
  331. if (++s->dac_sub_index == 3) {
  332. s->dac_sub_index = 0;
  333. s->dac_read_index++;
  334. }
  335. break;
  336. case VGA_FTC_R:
  337. val = s->fcr;
  338. break;
  339. case VGA_MIS_R:
  340. val = s->msr;
  341. break;
  342. case VGA_GFX_I:
  343. val = s->gr_index;
  344. break;
  345. case VGA_GFX_D:
  346. val = s->gr[s->gr_index];
  347. #ifdef DEBUG_VGA_REG
  348. printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
  349. #endif
  350. break;
  351. case VGA_CRT_IM:
  352. case VGA_CRT_IC:
  353. val = s->cr_index;
  354. break;
  355. case VGA_CRT_DM:
  356. case VGA_CRT_DC:
  357. val = s->cr[s->cr_index];
  358. #ifdef DEBUG_VGA_REG
  359. printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
  360. #endif
  361. break;
  362. case VGA_IS1_RM:
  363. case VGA_IS1_RC:
  364. /* just toggle to fool polling */
  365. val = s->st01 = s->retrace(s);
  366. s->ar_flip_flop = 0;
  367. break;
  368. default:
  369. val = 0x00;
  370. break;
  371. }
  372. }
  373. trace_vga_std_read_io(addr, val);
  374. return val;
  375. }
  376. void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
  377. {
  378. VGACommonState *s = opaque;
  379. int index;
  380. /* check port range access depending on color/monochrome mode */
  381. if (vga_ioport_invalid(s, addr)) {
  382. return;
  383. }
  384. trace_vga_std_write_io(addr, val);
  385. switch(addr) {
  386. case VGA_ATT_W:
  387. if (s->ar_flip_flop == 0) {
  388. val &= 0x3f;
  389. s->ar_index = val;
  390. } else {
  391. index = s->ar_index & 0x1f;
  392. switch(index) {
  393. case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
  394. s->ar[index] = val & 0x3f;
  395. break;
  396. case VGA_ATC_MODE:
  397. s->ar[index] = val & ~0x10;
  398. break;
  399. case VGA_ATC_OVERSCAN:
  400. s->ar[index] = val;
  401. break;
  402. case VGA_ATC_PLANE_ENABLE:
  403. s->ar[index] = val & ~0xc0;
  404. break;
  405. case VGA_ATC_PEL:
  406. s->ar[index] = val & ~0xf0;
  407. break;
  408. case VGA_ATC_COLOR_PAGE:
  409. s->ar[index] = val & ~0xf0;
  410. break;
  411. default:
  412. break;
  413. }
  414. }
  415. s->ar_flip_flop ^= 1;
  416. break;
  417. case VGA_MIS_W:
  418. s->msr = val & ~0x10;
  419. s->update_retrace_info(s);
  420. break;
  421. case VGA_SEQ_I:
  422. s->sr_index = val & 7;
  423. break;
  424. case VGA_SEQ_D:
  425. #ifdef DEBUG_VGA_REG
  426. printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
  427. #endif
  428. s->sr[s->sr_index] = val & sr_mask[s->sr_index];
  429. if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
  430. s->update_retrace_info(s);
  431. }
  432. vga_update_memory_access(s);
  433. break;
  434. case VGA_PEL_IR:
  435. s->dac_read_index = val;
  436. s->dac_sub_index = 0;
  437. s->dac_state = 3;
  438. break;
  439. case VGA_PEL_IW:
  440. s->dac_write_index = val;
  441. s->dac_sub_index = 0;
  442. s->dac_state = 0;
  443. break;
  444. case VGA_PEL_D:
  445. s->dac_cache[s->dac_sub_index] = val;
  446. if (++s->dac_sub_index == 3) {
  447. memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
  448. s->dac_sub_index = 0;
  449. s->dac_write_index++;
  450. }
  451. break;
  452. case VGA_GFX_I:
  453. s->gr_index = val & 0x0f;
  454. break;
  455. case VGA_GFX_D:
  456. #ifdef DEBUG_VGA_REG
  457. printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
  458. #endif
  459. s->gr[s->gr_index] = val & gr_mask[s->gr_index];
  460. vbe_update_vgaregs(s);
  461. vga_update_memory_access(s);
  462. break;
  463. case VGA_CRT_IM:
  464. case VGA_CRT_IC:
  465. s->cr_index = val;
  466. break;
  467. case VGA_CRT_DM:
  468. case VGA_CRT_DC:
  469. #ifdef DEBUG_VGA_REG
  470. printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
  471. #endif
  472. /* handle CR0-7 protection */
  473. if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
  474. s->cr_index <= VGA_CRTC_OVERFLOW) {
  475. /* can always write bit 4 of CR7 */
  476. if (s->cr_index == VGA_CRTC_OVERFLOW) {
  477. s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
  478. (val & 0x10);
  479. vbe_update_vgaregs(s);
  480. }
  481. return;
  482. }
  483. s->cr[s->cr_index] = val;
  484. vbe_update_vgaregs(s);
  485. switch(s->cr_index) {
  486. case VGA_CRTC_H_TOTAL:
  487. case VGA_CRTC_H_SYNC_START:
  488. case VGA_CRTC_H_SYNC_END:
  489. case VGA_CRTC_V_TOTAL:
  490. case VGA_CRTC_OVERFLOW:
  491. case VGA_CRTC_V_SYNC_END:
  492. case VGA_CRTC_MODE:
  493. s->update_retrace_info(s);
  494. break;
  495. }
  496. break;
  497. case VGA_IS1_RM:
  498. case VGA_IS1_RC:
  499. s->fcr = val & 0x10;
  500. break;
  501. }
  502. }
  503. /*
  504. * Sanity check vbe register writes.
  505. *
  506. * As we don't have a way to signal errors to the guest in the bochs
  507. * dispi interface we'll go adjust the registers to the closest valid
  508. * value.
  509. */
  510. static void vbe_fixup_regs(VGACommonState *s)
  511. {
  512. uint16_t *r = s->vbe_regs;
  513. uint32_t bits, linelength, maxy, offset;
  514. if (!vbe_enabled(s)) {
  515. /* vbe is turned off -- nothing to do */
  516. return;
  517. }
  518. /* check depth */
  519. switch (r[VBE_DISPI_INDEX_BPP]) {
  520. case 4:
  521. case 8:
  522. case 16:
  523. case 24:
  524. case 32:
  525. bits = r[VBE_DISPI_INDEX_BPP];
  526. break;
  527. case 15:
  528. bits = 16;
  529. break;
  530. default:
  531. bits = r[VBE_DISPI_INDEX_BPP] = 8;
  532. break;
  533. }
  534. /* check width */
  535. r[VBE_DISPI_INDEX_XRES] &= ~7u;
  536. if (r[VBE_DISPI_INDEX_XRES] == 0) {
  537. r[VBE_DISPI_INDEX_XRES] = 8;
  538. }
  539. if (r[VBE_DISPI_INDEX_XRES] > VBE_DISPI_MAX_XRES) {
  540. r[VBE_DISPI_INDEX_XRES] = VBE_DISPI_MAX_XRES;
  541. }
  542. r[VBE_DISPI_INDEX_VIRT_WIDTH] &= ~7u;
  543. if (r[VBE_DISPI_INDEX_VIRT_WIDTH] > VBE_DISPI_MAX_XRES) {
  544. r[VBE_DISPI_INDEX_VIRT_WIDTH] = VBE_DISPI_MAX_XRES;
  545. }
  546. if (r[VBE_DISPI_INDEX_VIRT_WIDTH] < r[VBE_DISPI_INDEX_XRES]) {
  547. r[VBE_DISPI_INDEX_VIRT_WIDTH] = r[VBE_DISPI_INDEX_XRES];
  548. }
  549. /* check height */
  550. linelength = r[VBE_DISPI_INDEX_VIRT_WIDTH] * bits / 8;
  551. maxy = s->vbe_size / linelength;
  552. if (r[VBE_DISPI_INDEX_YRES] == 0) {
  553. r[VBE_DISPI_INDEX_YRES] = 1;
  554. }
  555. if (r[VBE_DISPI_INDEX_YRES] > VBE_DISPI_MAX_YRES) {
  556. r[VBE_DISPI_INDEX_YRES] = VBE_DISPI_MAX_YRES;
  557. }
  558. if (r[VBE_DISPI_INDEX_YRES] > maxy) {
  559. r[VBE_DISPI_INDEX_YRES] = maxy;
  560. }
  561. /* check offset */
  562. if (r[VBE_DISPI_INDEX_X_OFFSET] > VBE_DISPI_MAX_XRES) {
  563. r[VBE_DISPI_INDEX_X_OFFSET] = VBE_DISPI_MAX_XRES;
  564. }
  565. if (r[VBE_DISPI_INDEX_Y_OFFSET] > VBE_DISPI_MAX_YRES) {
  566. r[VBE_DISPI_INDEX_Y_OFFSET] = VBE_DISPI_MAX_YRES;
  567. }
  568. offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
  569. offset += r[VBE_DISPI_INDEX_Y_OFFSET] * linelength;
  570. if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
  571. r[VBE_DISPI_INDEX_Y_OFFSET] = 0;
  572. offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
  573. if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
  574. r[VBE_DISPI_INDEX_X_OFFSET] = 0;
  575. offset = 0;
  576. }
  577. }
  578. /* update vga state */
  579. r[VBE_DISPI_INDEX_VIRT_HEIGHT] = maxy;
  580. s->vbe_line_offset = linelength;
  581. s->vbe_start_addr = offset / 4;
  582. }
  583. /* we initialize the VGA graphic mode */
  584. static void vbe_update_vgaregs(VGACommonState *s)
  585. {
  586. int h, shift_control;
  587. if (!vbe_enabled(s)) {
  588. /* vbe is turned off -- nothing to do */
  589. return;
  590. }
  591. /* graphic mode + memory map 1 */
  592. s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
  593. VGA_GR06_GRAPHICS_MODE;
  594. s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
  595. s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
  596. /* width */
  597. s->cr[VGA_CRTC_H_DISP] =
  598. (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
  599. /* height (only meaningful if < 1024) */
  600. h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
  601. s->cr[VGA_CRTC_V_DISP_END] = h;
  602. s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
  603. ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
  604. /* line compare to 1023 */
  605. s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
  606. s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
  607. s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
  608. if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
  609. shift_control = 0;
  610. s->sr_vbe[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
  611. } else {
  612. shift_control = 2;
  613. /* set chain 4 mode */
  614. s->sr_vbe[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
  615. /* activate all planes */
  616. s->sr_vbe[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
  617. }
  618. s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
  619. (shift_control << 5);
  620. s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
  621. }
  622. static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
  623. {
  624. VGACommonState *s = opaque;
  625. return s->vbe_index;
  626. }
  627. uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
  628. {
  629. VGACommonState *s = opaque;
  630. uint32_t val;
  631. if (s->vbe_index < VBE_DISPI_INDEX_NB) {
  632. if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
  633. switch(s->vbe_index) {
  634. /* XXX: do not hardcode ? */
  635. case VBE_DISPI_INDEX_XRES:
  636. val = VBE_DISPI_MAX_XRES;
  637. break;
  638. case VBE_DISPI_INDEX_YRES:
  639. val = VBE_DISPI_MAX_YRES;
  640. break;
  641. case VBE_DISPI_INDEX_BPP:
  642. val = VBE_DISPI_MAX_BPP;
  643. break;
  644. default:
  645. val = s->vbe_regs[s->vbe_index];
  646. break;
  647. }
  648. } else {
  649. val = s->vbe_regs[s->vbe_index];
  650. }
  651. } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
  652. val = s->vbe_size / (64 * KiB);
  653. } else {
  654. val = 0;
  655. }
  656. trace_vga_vbe_read(s->vbe_index, val);
  657. return val;
  658. }
  659. void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
  660. {
  661. VGACommonState *s = opaque;
  662. s->vbe_index = val;
  663. }
  664. void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
  665. {
  666. VGACommonState *s = opaque;
  667. if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
  668. trace_vga_vbe_write(s->vbe_index, val);
  669. switch(s->vbe_index) {
  670. case VBE_DISPI_INDEX_ID:
  671. if (val == VBE_DISPI_ID0 ||
  672. val == VBE_DISPI_ID1 ||
  673. val == VBE_DISPI_ID2 ||
  674. val == VBE_DISPI_ID3 ||
  675. val == VBE_DISPI_ID4 ||
  676. val == VBE_DISPI_ID5) {
  677. s->vbe_regs[s->vbe_index] = val;
  678. }
  679. break;
  680. case VBE_DISPI_INDEX_XRES:
  681. case VBE_DISPI_INDEX_YRES:
  682. case VBE_DISPI_INDEX_BPP:
  683. case VBE_DISPI_INDEX_VIRT_WIDTH:
  684. case VBE_DISPI_INDEX_X_OFFSET:
  685. case VBE_DISPI_INDEX_Y_OFFSET:
  686. s->vbe_regs[s->vbe_index] = val;
  687. vbe_fixup_regs(s);
  688. vbe_update_vgaregs(s);
  689. break;
  690. case VBE_DISPI_INDEX_BANK:
  691. val &= s->vbe_bank_mask;
  692. s->vbe_regs[s->vbe_index] = val;
  693. s->bank_offset = (val << 16);
  694. vga_update_memory_access(s);
  695. break;
  696. case VBE_DISPI_INDEX_ENABLE:
  697. if ((val & VBE_DISPI_ENABLED) &&
  698. !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
  699. s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0;
  700. s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
  701. s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
  702. s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED;
  703. vbe_fixup_regs(s);
  704. vbe_update_vgaregs(s);
  705. /* clear the screen */
  706. if (!(val & VBE_DISPI_NOCLEARMEM)) {
  707. memset(s->vram_ptr, 0,
  708. s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
  709. }
  710. } else {
  711. s->bank_offset = 0;
  712. }
  713. s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
  714. s->vbe_regs[s->vbe_index] = val;
  715. vga_update_memory_access(s);
  716. break;
  717. default:
  718. break;
  719. }
  720. }
  721. }
  722. /* called for accesses between 0xa0000 and 0xc0000 */
  723. uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
  724. {
  725. int memory_map_mode, plane;
  726. uint32_t ret;
  727. /* convert to VGA memory offset */
  728. memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
  729. addr &= 0x1ffff;
  730. switch(memory_map_mode) {
  731. case 0:
  732. break;
  733. case 1:
  734. if (addr >= 0x10000)
  735. return 0xff;
  736. addr += s->bank_offset;
  737. break;
  738. case 2:
  739. addr -= 0x10000;
  740. if (addr >= 0x8000)
  741. return 0xff;
  742. break;
  743. default:
  744. case 3:
  745. addr -= 0x18000;
  746. if (addr >= 0x8000)
  747. return 0xff;
  748. break;
  749. }
  750. if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
  751. /* chain4 mode */
  752. plane = addr & 3;
  753. addr &= ~3;
  754. } else if (s->gr[VGA_GFX_MODE] & VGA_GR05_HOST_ODD_EVEN) {
  755. /* odd/even mode (aka text mode mapping) */
  756. plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
  757. } else {
  758. /* standard VGA latched access */
  759. plane = s->gr[VGA_GFX_PLANE_READ];
  760. }
  761. if (s->gr[VGA_GFX_MISC] & VGA_GR06_CHAIN_ODD_EVEN) {
  762. addr &= ~1;
  763. }
  764. /* Doubleword/word mode. See comment in vga_mem_writeb */
  765. if (s->cr[VGA_CRTC_UNDERLINE] & VGA_CR14_DW) {
  766. addr >>= 2;
  767. } else if ((s->gr[VGA_GFX_MODE] & VGA_GR05_HOST_ODD_EVEN) &&
  768. (s->cr[VGA_CRTC_MODE] & VGA_CR17_WORD_BYTE) == 0) {
  769. addr >>= 1;
  770. }
  771. if (addr * sizeof(uint32_t) >= s->vram_size) {
  772. return 0xff;
  773. }
  774. if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
  775. /* chain 4 mode: simplified access (but it should use the same
  776. * algorithms as below, see e.g. vga_mem_writeb's plane mask check).
  777. */
  778. return s->vram_ptr[(addr << 2) | plane];
  779. }
  780. s->latch = ((uint32_t *)s->vram_ptr)[addr];
  781. if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
  782. /* read mode 0 */
  783. ret = GET_PLANE(s->latch, plane);
  784. } else {
  785. /* read mode 1 */
  786. ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
  787. mask16[s->gr[VGA_GFX_COMPARE_MASK]];
  788. ret |= ret >> 16;
  789. ret |= ret >> 8;
  790. ret = (~ret) & 0xff;
  791. }
  792. return ret;
  793. }
  794. /* called for accesses between 0xa0000 and 0xc0000 */
  795. void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
  796. {
  797. int memory_map_mode, write_mode, b, func_select, mask;
  798. uint32_t write_mask, bit_mask, set_mask;
  799. int plane = 0;
  800. #ifdef DEBUG_VGA_MEM
  801. printf("vga: [0x" HWADDR_FMT_plx "] = 0x%02x\n", addr, val);
  802. #endif
  803. /* convert to VGA memory offset */
  804. memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
  805. addr &= 0x1ffff;
  806. switch(memory_map_mode) {
  807. case 0:
  808. break;
  809. case 1:
  810. if (addr >= 0x10000)
  811. return;
  812. addr += s->bank_offset;
  813. break;
  814. case 2:
  815. addr -= 0x10000;
  816. if (addr >= 0x8000)
  817. return;
  818. break;
  819. default:
  820. case 3:
  821. addr -= 0x18000;
  822. if (addr >= 0x8000)
  823. return;
  824. break;
  825. }
  826. mask = sr(s, VGA_SEQ_PLANE_WRITE);
  827. if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
  828. /* chain 4 mode : simplest access */
  829. plane = addr & 3;
  830. mask &= (1 << plane);
  831. addr &= ~3;
  832. } else {
  833. if ((sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_SEQ_MODE) == 0) {
  834. mask &= (addr & 1) ? 0x0a : 0x05;
  835. }
  836. if (s->gr[VGA_GFX_MISC] & VGA_GR06_CHAIN_ODD_EVEN) {
  837. addr &= ~1;
  838. }
  839. }
  840. /* Doubleword/word mode. These should be honored when displaying,
  841. * not when reading/writing to memory! For example, chain4 modes
  842. * use double-word mode and, on real hardware, would fetch bytes
  843. * 0,1,2,3, 16,17,18,19, 32,33,34,35, etc. Text modes use word
  844. * mode and, on real hardware, would fetch bytes 0,1, 8,9, etc.
  845. *
  846. * QEMU instead shifted addresses on memory accesses because it
  847. * allows more optimizations (e.g. chain4_alias) and simplifies
  848. * the draw_line handlers. Unfortunately, there is one case where
  849. * the difference shows. When fetching font data, accesses are
  850. * always in consecutive bytes, even if the text/attribute pairs
  851. * are done in word mode. Hence, doing a right shift when operating
  852. * on font data is wrong. So check the odd/even mode bits together with
  853. * word mode bit. The odd/even read bit is 0 when reading font data,
  854. * and the odd/even write bit is 1 when writing it.
  855. */
  856. if (s->cr[VGA_CRTC_UNDERLINE] & VGA_CR14_DW) {
  857. addr >>= 2;
  858. } else if ((sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_SEQ_MODE) == 0 &&
  859. (s->cr[VGA_CRTC_MODE] & VGA_CR17_WORD_BYTE) == 0) {
  860. addr >>= 1;
  861. }
  862. if (addr * sizeof(uint32_t) >= s->vram_size) {
  863. return;
  864. }
  865. if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
  866. if (mask) {
  867. s->vram_ptr[(addr << 2) | plane] = val;
  868. #ifdef DEBUG_VGA_MEM
  869. printf("vga: chain4: [0x" HWADDR_FMT_plx "]\n", addr);
  870. #endif
  871. s->plane_updated |= mask; /* only used to detect font change */
  872. memory_region_set_dirty(&s->vram, addr, 1);
  873. }
  874. return;
  875. }
  876. /* standard VGA latched access */
  877. write_mode = s->gr[VGA_GFX_MODE] & 3;
  878. switch(write_mode) {
  879. default:
  880. case 0:
  881. /* rotate */
  882. b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
  883. val = ((val >> b) | (val << (8 - b))) & 0xff;
  884. val |= val << 8;
  885. val |= val << 16;
  886. /* apply set/reset mask */
  887. set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
  888. val = (val & ~set_mask) |
  889. (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
  890. bit_mask = s->gr[VGA_GFX_BIT_MASK];
  891. break;
  892. case 1:
  893. val = s->latch;
  894. goto do_write;
  895. case 2:
  896. val = mask16[val & 0x0f];
  897. bit_mask = s->gr[VGA_GFX_BIT_MASK];
  898. break;
  899. case 3:
  900. /* rotate */
  901. b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
  902. val = (val >> b) | (val << (8 - b));
  903. bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
  904. val = mask16[s->gr[VGA_GFX_SR_VALUE]];
  905. break;
  906. }
  907. /* apply logical operation */
  908. func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
  909. switch(func_select) {
  910. case 0:
  911. default:
  912. /* nothing to do */
  913. break;
  914. case 1:
  915. /* and */
  916. val &= s->latch;
  917. break;
  918. case 2:
  919. /* or */
  920. val |= s->latch;
  921. break;
  922. case 3:
  923. /* xor */
  924. val ^= s->latch;
  925. break;
  926. }
  927. /* apply bit mask */
  928. bit_mask |= bit_mask << 8;
  929. bit_mask |= bit_mask << 16;
  930. val = (val & bit_mask) | (s->latch & ~bit_mask);
  931. do_write:
  932. /* mask data according to sr[2] */
  933. s->plane_updated |= mask; /* only used to detect font change */
  934. write_mask = mask16[mask];
  935. ((uint32_t *)s->vram_ptr)[addr] =
  936. (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
  937. (val & write_mask);
  938. #ifdef DEBUG_VGA_MEM
  939. printf("vga: latch: [0x" HWADDR_FMT_plx "] mask=0x%08x val=0x%08x\n",
  940. addr * 4, write_mask, val);
  941. #endif
  942. memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
  943. }
  944. typedef void *vga_draw_line_func(VGACommonState *s1, uint8_t *d,
  945. uint32_t srcaddr, int width, int hpel);
  946. #include "vga-access.h"
  947. #include "vga-helpers.h"
  948. /* return true if the palette was modified */
  949. static int update_palette16(VGACommonState *s)
  950. {
  951. int full_update, i;
  952. uint32_t v, col, *palette;
  953. full_update = 0;
  954. palette = s->last_palette;
  955. for(i = 0; i < 16; i++) {
  956. v = s->ar[i];
  957. if (s->ar[VGA_ATC_MODE] & 0x80) {
  958. v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
  959. } else {
  960. v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
  961. }
  962. v = v * 3;
  963. col = rgb_to_pixel32(c6_to_8(s->palette[v]),
  964. c6_to_8(s->palette[v + 1]),
  965. c6_to_8(s->palette[v + 2]));
  966. if (col != palette[i]) {
  967. full_update = 1;
  968. palette[i] = col;
  969. }
  970. }
  971. return full_update;
  972. }
  973. /* return true if the palette was modified */
  974. static int update_palette256(VGACommonState *s)
  975. {
  976. int full_update, i;
  977. uint32_t v, col, *palette;
  978. full_update = 0;
  979. palette = s->last_palette;
  980. v = 0;
  981. for(i = 0; i < 256; i++) {
  982. if (s->dac_8bit) {
  983. col = rgb_to_pixel32(s->palette[v],
  984. s->palette[v + 1],
  985. s->palette[v + 2]);
  986. } else {
  987. col = rgb_to_pixel32(c6_to_8(s->palette[v]),
  988. c6_to_8(s->palette[v + 1]),
  989. c6_to_8(s->palette[v + 2]));
  990. }
  991. if (col != palette[i]) {
  992. full_update = 1;
  993. palette[i] = col;
  994. }
  995. v += 3;
  996. }
  997. return full_update;
  998. }
  999. static void vga_get_params(VGACommonState *s,
  1000. VGADisplayParams *params)
  1001. {
  1002. if (vbe_enabled(s)) {
  1003. params->line_offset = s->vbe_line_offset;
  1004. params->start_addr = s->vbe_start_addr;
  1005. params->line_compare = 65535;
  1006. params->hpel = VGA_HPEL_NEUTRAL;
  1007. params->hpel_split = false;
  1008. } else {
  1009. /* compute line_offset in bytes */
  1010. params->line_offset = s->cr[VGA_CRTC_OFFSET] << 3;
  1011. /* starting address */
  1012. params->start_addr = s->cr[VGA_CRTC_START_LO] |
  1013. (s->cr[VGA_CRTC_START_HI] << 8);
  1014. /* line compare */
  1015. params->line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
  1016. ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
  1017. ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
  1018. params->hpel = s->ar[VGA_ATC_PEL];
  1019. params->hpel_split = s->ar[VGA_ATC_MODE] & 0x20;
  1020. }
  1021. }
  1022. /* update start_addr and line_offset. Return TRUE if modified */
  1023. static int update_basic_params(VGACommonState *s)
  1024. {
  1025. int full_update;
  1026. VGADisplayParams current;
  1027. full_update = 0;
  1028. s->get_params(s, &current);
  1029. if (memcmp(&current, &s->params, sizeof(current))) {
  1030. s->params = current;
  1031. full_update = 1;
  1032. }
  1033. return full_update;
  1034. }
  1035. static const uint8_t cursor_glyph[32 * 4] = {
  1036. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1037. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1038. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1039. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1040. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1041. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1042. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1043. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1044. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1045. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1046. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1047. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1048. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1049. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1050. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1051. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  1052. };
  1053. static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
  1054. int *pcwidth, int *pcheight)
  1055. {
  1056. int width, cwidth, height, cheight;
  1057. /* total width & height */
  1058. cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
  1059. cwidth = 8;
  1060. if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) {
  1061. cwidth = 9;
  1062. }
  1063. if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) {
  1064. cwidth = 16; /* NOTE: no 18 pixel wide */
  1065. }
  1066. width = (s->cr[VGA_CRTC_H_DISP] + 1);
  1067. if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
  1068. /* ugly hack for CGA 160x100x16 - explain me the logic */
  1069. height = 100;
  1070. } else {
  1071. height = s->cr[VGA_CRTC_V_DISP_END] |
  1072. ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
  1073. ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
  1074. height = (height + 1) / cheight;
  1075. }
  1076. *pwidth = width;
  1077. *pheight = height;
  1078. *pcwidth = cwidth;
  1079. *pcheight = cheight;
  1080. }
  1081. /*
  1082. * Text mode update
  1083. * Missing:
  1084. * - double scan
  1085. * - double width
  1086. * - underline
  1087. * - flashing
  1088. */
  1089. static void vga_draw_text(VGACommonState *s, int full_update)
  1090. {
  1091. DisplaySurface *surface = qemu_console_surface(s->con);
  1092. int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
  1093. int cx_min, cx_max, linesize, x_incr, line, line1;
  1094. uint32_t offset, fgcol, bgcol, v, cursor_offset;
  1095. uint8_t *d1, *d, *src, *dest, *cursor_ptr;
  1096. const uint8_t *font_ptr, *font_base[2];
  1097. int dup9, line_offset;
  1098. uint32_t *palette;
  1099. uint32_t *ch_attr_ptr;
  1100. int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
  1101. /* compute font data address (in plane 2) */
  1102. v = sr(s, VGA_SEQ_CHARACTER_MAP);
  1103. offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
  1104. if (offset != s->font_offsets[0]) {
  1105. s->font_offsets[0] = offset;
  1106. full_update = 1;
  1107. }
  1108. font_base[0] = s->vram_ptr + offset;
  1109. offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
  1110. font_base[1] = s->vram_ptr + offset;
  1111. if (offset != s->font_offsets[1]) {
  1112. s->font_offsets[1] = offset;
  1113. full_update = 1;
  1114. }
  1115. if (s->plane_updated & (1 << 2) || s->has_chain4_alias) {
  1116. /* if the plane 2 was modified since the last display, it
  1117. indicates the font may have been modified */
  1118. s->plane_updated = 0;
  1119. full_update = 1;
  1120. }
  1121. full_update |= update_basic_params(s);
  1122. line_offset = s->params.line_offset;
  1123. vga_get_text_resolution(s, &width, &height, &cw, &cheight);
  1124. if ((height * width) <= 1) {
  1125. /* better than nothing: exit if transient size is too small */
  1126. return;
  1127. }
  1128. if ((height * width) > CH_ATTR_SIZE) {
  1129. /* better than nothing: exit if transient size is too big */
  1130. return;
  1131. }
  1132. if (width != s->last_width || height != s->last_height ||
  1133. cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
  1134. s->last_scr_width = width * cw;
  1135. s->last_scr_height = height * cheight;
  1136. qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
  1137. surface = qemu_console_surface(s->con);
  1138. dpy_text_resize(s->con, width, height);
  1139. s->last_depth = 0;
  1140. s->last_width = width;
  1141. s->last_height = height;
  1142. s->last_ch = cheight;
  1143. s->last_cw = cw;
  1144. full_update = 1;
  1145. }
  1146. full_update |= update_palette16(s);
  1147. palette = s->last_palette;
  1148. x_incr = cw * surface_bytes_per_pixel(surface);
  1149. if (full_update) {
  1150. s->full_update_text = 1;
  1151. }
  1152. if (s->full_update_gfx) {
  1153. s->full_update_gfx = 0;
  1154. full_update |= 1;
  1155. }
  1156. cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
  1157. s->cr[VGA_CRTC_CURSOR_LO]) - s->params.start_addr;
  1158. if (cursor_offset != s->cursor_offset ||
  1159. s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
  1160. s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
  1161. /* if the cursor position changed, we update the old and new
  1162. chars */
  1163. if (s->cursor_offset < CH_ATTR_SIZE)
  1164. s->last_ch_attr[s->cursor_offset] = -1;
  1165. if (cursor_offset < CH_ATTR_SIZE)
  1166. s->last_ch_attr[cursor_offset] = -1;
  1167. s->cursor_offset = cursor_offset;
  1168. s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
  1169. s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
  1170. }
  1171. cursor_ptr = s->vram_ptr + (s->params.start_addr + cursor_offset) * 4;
  1172. if (now >= s->cursor_blink_time) {
  1173. s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
  1174. s->cursor_visible_phase = !s->cursor_visible_phase;
  1175. }
  1176. dest = surface_data(surface);
  1177. linesize = surface_stride(surface);
  1178. ch_attr_ptr = s->last_ch_attr;
  1179. line = 0;
  1180. offset = s->params.start_addr * 4;
  1181. for(cy = 0; cy < height; cy++) {
  1182. d1 = dest;
  1183. src = s->vram_ptr + offset;
  1184. cx_min = width;
  1185. cx_max = -1;
  1186. for(cx = 0; cx < width; cx++) {
  1187. if (src + sizeof(uint16_t) > s->vram_ptr + s->vram_size) {
  1188. break;
  1189. }
  1190. ch_attr = *(uint16_t *)src;
  1191. if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
  1192. if (cx < cx_min)
  1193. cx_min = cx;
  1194. if (cx > cx_max)
  1195. cx_max = cx;
  1196. *ch_attr_ptr = ch_attr;
  1197. #if HOST_BIG_ENDIAN
  1198. ch = ch_attr >> 8;
  1199. cattr = ch_attr & 0xff;
  1200. #else
  1201. ch = ch_attr & 0xff;
  1202. cattr = ch_attr >> 8;
  1203. #endif
  1204. font_ptr = font_base[(cattr >> 3) & 1];
  1205. font_ptr += 32 * 4 * ch;
  1206. bgcol = palette[cattr >> 4];
  1207. fgcol = palette[cattr & 0x0f];
  1208. if (cw == 16) {
  1209. vga_draw_glyph16(d1, linesize,
  1210. font_ptr, cheight, fgcol, bgcol);
  1211. } else if (cw != 9) {
  1212. vga_draw_glyph8(d1, linesize,
  1213. font_ptr, cheight, fgcol, bgcol);
  1214. } else {
  1215. dup9 = 0;
  1216. if (ch >= 0xb0 && ch <= 0xdf &&
  1217. (s->ar[VGA_ATC_MODE] & 0x04)) {
  1218. dup9 = 1;
  1219. }
  1220. vga_draw_glyph9(d1, linesize,
  1221. font_ptr, cheight, fgcol, bgcol, dup9);
  1222. }
  1223. if (src == cursor_ptr &&
  1224. !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
  1225. s->cursor_visible_phase) {
  1226. int line_start, line_last, h;
  1227. /* draw the cursor */
  1228. line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
  1229. line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
  1230. /* XXX: check that */
  1231. if (line_last > cheight - 1)
  1232. line_last = cheight - 1;
  1233. if (line_last >= line_start && line_start < cheight) {
  1234. h = line_last - line_start + 1;
  1235. d = d1 + linesize * line_start;
  1236. if (cw == 16) {
  1237. vga_draw_glyph16(d, linesize,
  1238. cursor_glyph, h, fgcol, bgcol);
  1239. } else if (cw != 9) {
  1240. vga_draw_glyph8(d, linesize,
  1241. cursor_glyph, h, fgcol, bgcol);
  1242. } else {
  1243. vga_draw_glyph9(d, linesize,
  1244. cursor_glyph, h, fgcol, bgcol, 1);
  1245. }
  1246. }
  1247. }
  1248. }
  1249. d1 += x_incr;
  1250. src += 4;
  1251. ch_attr_ptr++;
  1252. }
  1253. if (cx_max != -1) {
  1254. dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
  1255. (cx_max - cx_min + 1) * cw, cheight);
  1256. }
  1257. dest += linesize * cheight;
  1258. line1 = line + cheight;
  1259. offset += line_offset;
  1260. if (line < s->params.line_compare && line1 >= s->params.line_compare) {
  1261. offset = 0;
  1262. }
  1263. line = line1;
  1264. }
  1265. }
  1266. enum {
  1267. VGA_DRAW_LINE2,
  1268. VGA_DRAW_LINE2D2,
  1269. VGA_DRAW_LINE4,
  1270. VGA_DRAW_LINE4D2,
  1271. VGA_DRAW_LINE8D2,
  1272. VGA_DRAW_LINE8,
  1273. VGA_DRAW_LINE15_LE,
  1274. VGA_DRAW_LINE16_LE,
  1275. VGA_DRAW_LINE24_LE,
  1276. VGA_DRAW_LINE32_LE,
  1277. VGA_DRAW_LINE15_BE,
  1278. VGA_DRAW_LINE16_BE,
  1279. VGA_DRAW_LINE24_BE,
  1280. VGA_DRAW_LINE32_BE,
  1281. VGA_DRAW_LINE_NB,
  1282. };
  1283. static vga_draw_line_func * const vga_draw_line_table[VGA_DRAW_LINE_NB] = {
  1284. vga_draw_line2,
  1285. vga_draw_line2d2,
  1286. vga_draw_line4,
  1287. vga_draw_line4d2,
  1288. vga_draw_line8d2,
  1289. vga_draw_line8,
  1290. vga_draw_line15_le,
  1291. vga_draw_line16_le,
  1292. vga_draw_line24_le,
  1293. vga_draw_line32_le,
  1294. vga_draw_line15_be,
  1295. vga_draw_line16_be,
  1296. vga_draw_line24_be,
  1297. vga_draw_line32_be,
  1298. };
  1299. static int vga_get_bpp(VGACommonState *s)
  1300. {
  1301. int ret;
  1302. if (vbe_enabled(s)) {
  1303. ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
  1304. } else {
  1305. ret = 0;
  1306. }
  1307. return ret;
  1308. }
  1309. static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
  1310. {
  1311. int width, height;
  1312. if (vbe_enabled(s)) {
  1313. width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
  1314. height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
  1315. } else {
  1316. width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
  1317. height = s->cr[VGA_CRTC_V_DISP_END] |
  1318. ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
  1319. ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
  1320. height = (height + 1);
  1321. }
  1322. *pwidth = width;
  1323. *pheight = height;
  1324. }
  1325. void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
  1326. {
  1327. int y;
  1328. if (y1 >= VGA_MAX_HEIGHT)
  1329. return;
  1330. if (y2 >= VGA_MAX_HEIGHT)
  1331. y2 = VGA_MAX_HEIGHT;
  1332. for(y = y1; y < y2; y++) {
  1333. s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
  1334. }
  1335. }
  1336. static bool vga_scanline_invalidated(VGACommonState *s, int y)
  1337. {
  1338. if (y >= VGA_MAX_HEIGHT) {
  1339. return false;
  1340. }
  1341. return s->invalidated_y_table[y >> 5] & (1 << (y & 0x1f));
  1342. }
  1343. void vga_dirty_log_start(VGACommonState *s)
  1344. {
  1345. memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
  1346. }
  1347. void vga_dirty_log_stop(VGACommonState *s)
  1348. {
  1349. memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
  1350. }
  1351. /*
  1352. * graphic modes
  1353. */
  1354. static void vga_draw_graphic(VGACommonState *s, int full_update)
  1355. {
  1356. DisplaySurface *surface = qemu_console_surface(s->con);
  1357. int y1, y, update, linesize, y_start, double_scan, mask, depth;
  1358. int width, height, shift_control, bwidth, bits;
  1359. ram_addr_t page0, page1, region_start, region_end;
  1360. DirtyBitmapSnapshot *snap = NULL;
  1361. int disp_width, multi_scan, multi_run;
  1362. int hpel;
  1363. uint8_t *d;
  1364. uint32_t v, addr1, addr;
  1365. vga_draw_line_func *vga_draw_line = NULL;
  1366. bool allocate_surface, force_shadow = false;
  1367. pixman_format_code_t format;
  1368. #if HOST_BIG_ENDIAN
  1369. bool byteswap = !s->big_endian_fb;
  1370. #else
  1371. bool byteswap = s->big_endian_fb;
  1372. #endif
  1373. full_update |= update_basic_params(s);
  1374. s->get_resolution(s, &width, &height);
  1375. disp_width = width;
  1376. depth = s->get_bpp(s);
  1377. /* bits 5-6: 0 = 16-color mode, 1 = 4-color mode, 2 = 256-color mode. */
  1378. shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
  1379. double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
  1380. if (s->cr[VGA_CRTC_MODE] & 1) {
  1381. multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
  1382. - 1;
  1383. } else {
  1384. /* in CGA modes, multi_scan is ignored */
  1385. /* XXX: is it correct ? */
  1386. multi_scan = double_scan;
  1387. }
  1388. multi_run = multi_scan;
  1389. if (shift_control != s->shift_control ||
  1390. double_scan != s->double_scan) {
  1391. full_update = 1;
  1392. s->shift_control = shift_control;
  1393. s->double_scan = double_scan;
  1394. }
  1395. if (shift_control == 0) {
  1396. full_update |= update_palette16(s);
  1397. if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
  1398. disp_width <<= 1;
  1399. v = VGA_DRAW_LINE4D2;
  1400. } else {
  1401. v = VGA_DRAW_LINE4;
  1402. }
  1403. bits = 4;
  1404. } else if (shift_control == 1) {
  1405. full_update |= update_palette16(s);
  1406. if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
  1407. disp_width <<= 1;
  1408. v = VGA_DRAW_LINE2D2;
  1409. } else {
  1410. v = VGA_DRAW_LINE2;
  1411. }
  1412. bits = 4;
  1413. } else {
  1414. switch (depth) {
  1415. default:
  1416. case 0:
  1417. full_update |= update_palette256(s);
  1418. v = VGA_DRAW_LINE8D2;
  1419. bits = 4;
  1420. break;
  1421. case 8:
  1422. full_update |= update_palette256(s);
  1423. v = VGA_DRAW_LINE8;
  1424. bits = 8;
  1425. break;
  1426. case 15:
  1427. v = s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_LE;
  1428. bits = 16;
  1429. break;
  1430. case 16:
  1431. v = s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_LE;
  1432. bits = 16;
  1433. break;
  1434. case 24:
  1435. v = s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_LE;
  1436. bits = 24;
  1437. break;
  1438. case 32:
  1439. v = s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_LE;
  1440. bits = 32;
  1441. break;
  1442. }
  1443. }
  1444. /* Horizontal pel panning bit 3 is only used in text mode. */
  1445. hpel = bits <= 8 ? s->params.hpel & 7 : 0;
  1446. bwidth = DIV_ROUND_UP(width * bits, 8); /* scanline length */
  1447. if (hpel) {
  1448. bwidth += 4;
  1449. }
  1450. region_start = (s->params.start_addr * 4);
  1451. region_end = region_start + (ram_addr_t)s->params.line_offset * (height - 1) + bwidth;
  1452. if (region_end > s->vbe_size) {
  1453. /*
  1454. * On wrap around take the safe and slow route:
  1455. * - create a dirty bitmap snapshot for all vga memory.
  1456. * - force shadowing (so all vga memory access goes
  1457. * through vga_read_*() helpers).
  1458. *
  1459. * Given this affects only vga features which are pretty much
  1460. * unused by modern guests there should be no performance
  1461. * impact.
  1462. */
  1463. region_start = 0;
  1464. region_end = s->vbe_size;
  1465. force_shadow = true;
  1466. }
  1467. if (s->params.line_compare < height) {
  1468. /* split screen mode */
  1469. region_start = 0;
  1470. }
  1471. /*
  1472. * Check whether we can share the surface with the backend
  1473. * or whether we need a shadow surface. We share native
  1474. * endian surfaces for 15bpp and above and byteswapped
  1475. * surfaces for 24bpp and above.
  1476. */
  1477. format = qemu_default_pixman_format(depth, !byteswap);
  1478. if (format) {
  1479. allocate_surface = !dpy_gfx_check_format(s->con, format)
  1480. || s->force_shadow || force_shadow;
  1481. } else {
  1482. allocate_surface = true;
  1483. }
  1484. if (s->params.line_offset != s->last_line_offset ||
  1485. disp_width != s->last_width ||
  1486. height != s->last_height ||
  1487. s->last_depth != depth ||
  1488. s->last_byteswap != byteswap ||
  1489. allocate_surface != surface_is_allocated(surface)) {
  1490. /* display parameters changed -> need new display surface */
  1491. s->last_scr_width = disp_width;
  1492. s->last_scr_height = height;
  1493. s->last_width = disp_width;
  1494. s->last_height = height;
  1495. s->last_line_offset = s->params.line_offset;
  1496. s->last_depth = depth;
  1497. s->last_byteswap = byteswap;
  1498. /* 16 extra pixels are needed for double-width planar modes. */
  1499. s->panning_buf = g_realloc(s->panning_buf,
  1500. (disp_width + 16) * sizeof(uint32_t));
  1501. full_update = 1;
  1502. }
  1503. if (surface_data(surface) != s->vram_ptr + (s->params.start_addr * 4)
  1504. && !surface_is_allocated(surface)) {
  1505. /* base address changed (page flip) -> shared display surfaces
  1506. * must be updated with the new base address */
  1507. full_update = 1;
  1508. }
  1509. if (full_update) {
  1510. if (!allocate_surface) {
  1511. surface = qemu_create_displaysurface_from(disp_width,
  1512. height, format, s->params.line_offset,
  1513. s->vram_ptr + (s->params.start_addr * 4));
  1514. dpy_gfx_replace_surface(s->con, surface);
  1515. } else {
  1516. qemu_console_resize(s->con, disp_width, height);
  1517. surface = qemu_console_surface(s->con);
  1518. }
  1519. }
  1520. vga_draw_line = vga_draw_line_table[v];
  1521. if (surface_is_allocated(surface) && s->cursor_invalidate) {
  1522. s->cursor_invalidate(s);
  1523. }
  1524. #if 0
  1525. printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
  1526. width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
  1527. s->params.line_compare, sr(s, VGA_SEQ_CLOCK_MODE));
  1528. #endif
  1529. addr1 = (s->params.start_addr * 4);
  1530. y_start = -1;
  1531. d = surface_data(surface);
  1532. linesize = surface_stride(surface);
  1533. y1 = 0;
  1534. if (!full_update) {
  1535. snap = memory_region_snapshot_and_clear_dirty(&s->vram, region_start,
  1536. region_end - region_start,
  1537. DIRTY_MEMORY_VGA);
  1538. }
  1539. for(y = 0; y < height; y++) {
  1540. addr = addr1;
  1541. if (!(s->cr[VGA_CRTC_MODE] & 1)) {
  1542. int shift;
  1543. /* CGA compatibility handling */
  1544. shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
  1545. addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
  1546. }
  1547. if (!(s->cr[VGA_CRTC_MODE] & 2)) {
  1548. addr = (addr & ~0x8000) | ((y1 & 2) << 14);
  1549. }
  1550. page0 = addr & s->vbe_size_mask;
  1551. page1 = (addr + bwidth - 1) & s->vbe_size_mask;
  1552. if (full_update) {
  1553. update = 1;
  1554. } else if (page1 < page0) {
  1555. /* scanline wraps from end of video memory to the start */
  1556. assert(force_shadow);
  1557. update = memory_region_snapshot_get_dirty(&s->vram, snap,
  1558. page0, s->vbe_size - page0);
  1559. update |= memory_region_snapshot_get_dirty(&s->vram, snap,
  1560. 0, page1);
  1561. } else {
  1562. update = memory_region_snapshot_get_dirty(&s->vram, snap,
  1563. page0, page1 - page0);
  1564. }
  1565. /* explicit invalidation for the hardware cursor (cirrus only) */
  1566. update |= vga_scanline_invalidated(s, y);
  1567. if (update) {
  1568. if (y_start < 0)
  1569. y_start = y;
  1570. if (surface_is_allocated(surface)) {
  1571. uint8_t *p;
  1572. p = vga_draw_line(s, d, addr, width, hpel);
  1573. if (p) {
  1574. memcpy(d, p, disp_width * sizeof(uint32_t));
  1575. }
  1576. if (s->cursor_draw_line)
  1577. s->cursor_draw_line(s, d, y);
  1578. }
  1579. } else {
  1580. if (y_start >= 0) {
  1581. /* flush to display */
  1582. dpy_gfx_update(s->con, 0, y_start,
  1583. disp_width, y - y_start);
  1584. y_start = -1;
  1585. }
  1586. }
  1587. if (!multi_run) {
  1588. mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
  1589. if ((y1 & mask) == mask)
  1590. addr1 += s->params.line_offset;
  1591. y1++;
  1592. multi_run = multi_scan;
  1593. } else {
  1594. multi_run--;
  1595. }
  1596. /* line compare acts on the displayed lines */
  1597. if (y == s->params.line_compare) {
  1598. if (s->params.hpel_split) {
  1599. hpel = VGA_HPEL_NEUTRAL;
  1600. }
  1601. addr1 = 0;
  1602. }
  1603. d += linesize;
  1604. }
  1605. if (y_start >= 0) {
  1606. /* flush to display */
  1607. dpy_gfx_update(s->con, 0, y_start,
  1608. disp_width, y - y_start);
  1609. }
  1610. g_free(snap);
  1611. memset(s->invalidated_y_table, 0, sizeof(s->invalidated_y_table));
  1612. }
  1613. static void vga_draw_blank(VGACommonState *s, int full_update)
  1614. {
  1615. DisplaySurface *surface = qemu_console_surface(s->con);
  1616. int i, w;
  1617. uint8_t *d;
  1618. if (!full_update)
  1619. return;
  1620. if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
  1621. return;
  1622. if (!surface_is_allocated(surface)) {
  1623. /* unshare buffer, otherwise the blanking corrupts vga vram */
  1624. surface = qemu_create_displaysurface(s->last_scr_width,
  1625. s->last_scr_height);
  1626. dpy_gfx_replace_surface(s->con, surface);
  1627. }
  1628. w = s->last_scr_width * surface_bytes_per_pixel(surface);
  1629. d = surface_data(surface);
  1630. for(i = 0; i < s->last_scr_height; i++) {
  1631. memset(d, 0, w);
  1632. d += surface_stride(surface);
  1633. }
  1634. dpy_gfx_update_full(s->con);
  1635. }
  1636. #define GMODE_TEXT 0
  1637. #define GMODE_GRAPH 1
  1638. #define GMODE_BLANK 2
  1639. static void vga_update_display(void *opaque)
  1640. {
  1641. VGACommonState *s = opaque;
  1642. DisplaySurface *surface = qemu_console_surface(s->con);
  1643. int full_update, graphic_mode;
  1644. qemu_flush_coalesced_mmio_buffer();
  1645. if (surface_bits_per_pixel(surface) == 0) {
  1646. /* nothing to do */
  1647. } else {
  1648. full_update = 0;
  1649. if (!(s->ar_index & 0x20)) {
  1650. graphic_mode = GMODE_BLANK;
  1651. } else {
  1652. graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
  1653. }
  1654. if (graphic_mode != s->graphic_mode) {
  1655. s->graphic_mode = graphic_mode;
  1656. s->cursor_blink_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
  1657. full_update = 1;
  1658. }
  1659. switch(graphic_mode) {
  1660. case GMODE_TEXT:
  1661. vga_draw_text(s, full_update);
  1662. break;
  1663. case GMODE_GRAPH:
  1664. vga_draw_graphic(s, full_update);
  1665. break;
  1666. case GMODE_BLANK:
  1667. default:
  1668. vga_draw_blank(s, full_update);
  1669. break;
  1670. }
  1671. }
  1672. }
  1673. /* force a full display refresh */
  1674. static void vga_invalidate_display(void *opaque)
  1675. {
  1676. VGACommonState *s = opaque;
  1677. s->last_width = -1;
  1678. s->last_height = -1;
  1679. }
  1680. void vga_common_reset(VGACommonState *s)
  1681. {
  1682. s->sr_index = 0;
  1683. memset(s->sr, '\0', sizeof(s->sr));
  1684. memset(s->sr_vbe, '\0', sizeof(s->sr_vbe));
  1685. s->gr_index = 0;
  1686. memset(s->gr, '\0', sizeof(s->gr));
  1687. s->ar_index = 0;
  1688. memset(s->ar, '\0', sizeof(s->ar));
  1689. s->ar_flip_flop = 0;
  1690. s->cr_index = 0;
  1691. memset(s->cr, '\0', sizeof(s->cr));
  1692. s->msr = 0;
  1693. s->fcr = 0;
  1694. s->st00 = 0;
  1695. s->st01 = 0;
  1696. s->dac_state = 0;
  1697. s->dac_sub_index = 0;
  1698. s->dac_read_index = 0;
  1699. s->dac_write_index = 0;
  1700. memset(s->dac_cache, '\0', sizeof(s->dac_cache));
  1701. s->dac_8bit = 0;
  1702. memset(s->palette, '\0', sizeof(s->palette));
  1703. s->bank_offset = 0;
  1704. s->vbe_index = 0;
  1705. memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
  1706. s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
  1707. s->vbe_start_addr = 0;
  1708. s->vbe_line_offset = 0;
  1709. s->vbe_bank_mask = (s->vram_size >> 16) - 1;
  1710. memset(s->font_offsets, '\0', sizeof(s->font_offsets));
  1711. s->graphic_mode = -1; /* force full update */
  1712. s->shift_control = 0;
  1713. s->double_scan = 0;
  1714. memset(&s->params, '\0', sizeof(s->params));
  1715. s->plane_updated = 0;
  1716. s->last_cw = 0;
  1717. s->last_ch = 0;
  1718. s->last_width = 0;
  1719. s->last_height = 0;
  1720. s->last_scr_width = 0;
  1721. s->last_scr_height = 0;
  1722. s->cursor_start = 0;
  1723. s->cursor_end = 0;
  1724. s->cursor_offset = 0;
  1725. memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
  1726. memset(s->last_palette, '\0', sizeof(s->last_palette));
  1727. memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
  1728. switch (vga_retrace_method) {
  1729. case VGA_RETRACE_DUMB:
  1730. break;
  1731. case VGA_RETRACE_PRECISE:
  1732. memset(&s->retrace_info, 0, sizeof (s->retrace_info));
  1733. break;
  1734. }
  1735. vga_update_memory_access(s);
  1736. }
  1737. static void vga_reset(void *opaque)
  1738. {
  1739. VGACommonState *s = opaque;
  1740. vga_common_reset(s);
  1741. }
  1742. #define TEXTMODE_X(x) ((x) % width)
  1743. #define TEXTMODE_Y(x) ((x) / width)
  1744. #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
  1745. ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
  1746. /* relay text rendering to the display driver
  1747. * instead of doing a full vga_update_display() */
  1748. static void vga_update_text(void *opaque, console_ch_t *chardata)
  1749. {
  1750. VGACommonState *s = opaque;
  1751. int graphic_mode, i, cursor_offset, cursor_visible;
  1752. int cw, cheight, width, height, size, c_min, c_max;
  1753. uint32_t *src;
  1754. console_ch_t *dst, val;
  1755. char msg_buffer[80];
  1756. int full_update = 0;
  1757. qemu_flush_coalesced_mmio_buffer();
  1758. if (!(s->ar_index & 0x20)) {
  1759. graphic_mode = GMODE_BLANK;
  1760. } else {
  1761. graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
  1762. }
  1763. if (graphic_mode != s->graphic_mode) {
  1764. s->graphic_mode = graphic_mode;
  1765. full_update = 1;
  1766. }
  1767. if (s->last_width == -1) {
  1768. s->last_width = 0;
  1769. full_update = 1;
  1770. }
  1771. switch (graphic_mode) {
  1772. case GMODE_TEXT:
  1773. /* TODO: update palette */
  1774. full_update |= update_basic_params(s);
  1775. /* total width & height */
  1776. cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
  1777. cw = 8;
  1778. if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) {
  1779. cw = 9;
  1780. }
  1781. if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) {
  1782. cw = 16; /* NOTE: no 18 pixel wide */
  1783. }
  1784. width = (s->cr[VGA_CRTC_H_DISP] + 1);
  1785. if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
  1786. /* ugly hack for CGA 160x100x16 - explain me the logic */
  1787. height = 100;
  1788. } else {
  1789. height = s->cr[VGA_CRTC_V_DISP_END] |
  1790. ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
  1791. ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
  1792. height = (height + 1) / cheight;
  1793. }
  1794. size = (height * width);
  1795. if (size > CH_ATTR_SIZE) {
  1796. if (!full_update)
  1797. return;
  1798. snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
  1799. width, height);
  1800. break;
  1801. }
  1802. if (width != s->last_width || height != s->last_height ||
  1803. cw != s->last_cw || cheight != s->last_ch) {
  1804. s->last_scr_width = width * cw;
  1805. s->last_scr_height = height * cheight;
  1806. qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
  1807. dpy_text_resize(s->con, width, height);
  1808. s->last_depth = 0;
  1809. s->last_width = width;
  1810. s->last_height = height;
  1811. s->last_ch = cheight;
  1812. s->last_cw = cw;
  1813. full_update = 1;
  1814. }
  1815. if (full_update) {
  1816. s->full_update_gfx = 1;
  1817. }
  1818. if (s->full_update_text) {
  1819. s->full_update_text = 0;
  1820. full_update |= 1;
  1821. }
  1822. /* Update "hardware" cursor */
  1823. cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
  1824. s->cr[VGA_CRTC_CURSOR_LO]) - s->params.start_addr;
  1825. if (cursor_offset != s->cursor_offset ||
  1826. s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
  1827. s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
  1828. cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
  1829. if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
  1830. dpy_text_cursor(s->con,
  1831. TEXTMODE_X(cursor_offset),
  1832. TEXTMODE_Y(cursor_offset));
  1833. else
  1834. dpy_text_cursor(s->con, -1, -1);
  1835. s->cursor_offset = cursor_offset;
  1836. s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
  1837. s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
  1838. }
  1839. src = (uint32_t *) s->vram_ptr + s->params.start_addr;
  1840. dst = chardata;
  1841. if (full_update) {
  1842. for (i = 0; i < size; src ++, dst ++, i ++)
  1843. console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
  1844. dpy_text_update(s->con, 0, 0, width, height);
  1845. } else {
  1846. c_max = 0;
  1847. for (i = 0; i < size; src ++, dst ++, i ++) {
  1848. console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
  1849. if (*dst != val) {
  1850. *dst = val;
  1851. c_max = i;
  1852. break;
  1853. }
  1854. }
  1855. c_min = i;
  1856. for (; i < size; src ++, dst ++, i ++) {
  1857. console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
  1858. if (*dst != val) {
  1859. *dst = val;
  1860. c_max = i;
  1861. }
  1862. }
  1863. if (c_min <= c_max) {
  1864. i = TEXTMODE_Y(c_min);
  1865. dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
  1866. }
  1867. }
  1868. return;
  1869. case GMODE_GRAPH:
  1870. if (!full_update)
  1871. return;
  1872. s->get_resolution(s, &width, &height);
  1873. snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
  1874. width, height);
  1875. break;
  1876. case GMODE_BLANK:
  1877. default:
  1878. if (!full_update)
  1879. return;
  1880. snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
  1881. break;
  1882. }
  1883. /* Display a message */
  1884. s->last_width = 60;
  1885. s->last_height = height = 3;
  1886. dpy_text_cursor(s->con, -1, -1);
  1887. dpy_text_resize(s->con, s->last_width, height);
  1888. for (dst = chardata, i = 0; i < s->last_width * height; i ++)
  1889. console_write_ch(dst ++, ' ');
  1890. size = strlen(msg_buffer);
  1891. width = (s->last_width - size) / 2;
  1892. dst = chardata + s->last_width + width;
  1893. for (i = 0; i < size; i ++)
  1894. console_write_ch(dst ++, ATTR2CHTYPE(msg_buffer[i], QEMU_COLOR_BLUE,
  1895. QEMU_COLOR_BLACK, 1));
  1896. dpy_text_update(s->con, 0, 0, s->last_width, height);
  1897. }
  1898. static uint64_t vga_mem_read(void *opaque, hwaddr addr,
  1899. unsigned size)
  1900. {
  1901. VGACommonState *s = opaque;
  1902. return vga_mem_readb(s, addr);
  1903. }
  1904. static void vga_mem_write(void *opaque, hwaddr addr,
  1905. uint64_t data, unsigned size)
  1906. {
  1907. VGACommonState *s = opaque;
  1908. vga_mem_writeb(s, addr, data);
  1909. }
  1910. const MemoryRegionOps vga_mem_ops = {
  1911. .read = vga_mem_read,
  1912. .write = vga_mem_write,
  1913. .endianness = DEVICE_LITTLE_ENDIAN,
  1914. .impl = {
  1915. .min_access_size = 1,
  1916. .max_access_size = 1,
  1917. },
  1918. };
  1919. static int vga_common_post_load(void *opaque, int version_id)
  1920. {
  1921. VGACommonState *s = opaque;
  1922. /* force refresh */
  1923. s->graphic_mode = -1;
  1924. vbe_update_vgaregs(s);
  1925. vga_update_memory_access(s);
  1926. return 0;
  1927. }
  1928. static bool vga_endian_state_needed(void *opaque)
  1929. {
  1930. VGACommonState *s = opaque;
  1931. /*
  1932. * Only send the endian state if it's different from the
  1933. * default one, thus ensuring backward compatibility for
  1934. * migration of the common case
  1935. */
  1936. return s->default_endian_fb != s->big_endian_fb;
  1937. }
  1938. static const VMStateDescription vmstate_vga_endian = {
  1939. .name = "vga.endian",
  1940. .version_id = 1,
  1941. .minimum_version_id = 1,
  1942. .needed = vga_endian_state_needed,
  1943. .fields = (const VMStateField[]) {
  1944. VMSTATE_BOOL(big_endian_fb, VGACommonState),
  1945. VMSTATE_END_OF_LIST()
  1946. }
  1947. };
  1948. const VMStateDescription vmstate_vga_common = {
  1949. .name = "vga",
  1950. .version_id = 2,
  1951. .minimum_version_id = 2,
  1952. .post_load = vga_common_post_load,
  1953. .fields = (const VMStateField[]) {
  1954. VMSTATE_UINT32(latch, VGACommonState),
  1955. VMSTATE_UINT8(sr_index, VGACommonState),
  1956. VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
  1957. VMSTATE_UINT8(gr_index, VGACommonState),
  1958. VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
  1959. VMSTATE_UINT8(ar_index, VGACommonState),
  1960. VMSTATE_BUFFER(ar, VGACommonState),
  1961. VMSTATE_INT32(ar_flip_flop, VGACommonState),
  1962. VMSTATE_UINT8(cr_index, VGACommonState),
  1963. VMSTATE_BUFFER(cr, VGACommonState),
  1964. VMSTATE_UINT8(msr, VGACommonState),
  1965. VMSTATE_UINT8(fcr, VGACommonState),
  1966. VMSTATE_UINT8(st00, VGACommonState),
  1967. VMSTATE_UINT8(st01, VGACommonState),
  1968. VMSTATE_UINT8(dac_state, VGACommonState),
  1969. VMSTATE_UINT8(dac_sub_index, VGACommonState),
  1970. VMSTATE_UINT8(dac_read_index, VGACommonState),
  1971. VMSTATE_UINT8(dac_write_index, VGACommonState),
  1972. VMSTATE_BUFFER(dac_cache, VGACommonState),
  1973. VMSTATE_BUFFER(palette, VGACommonState),
  1974. VMSTATE_INT32(bank_offset, VGACommonState),
  1975. VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState, NULL),
  1976. VMSTATE_UINT16(vbe_index, VGACommonState),
  1977. VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
  1978. VMSTATE_UINT32(vbe_start_addr, VGACommonState),
  1979. VMSTATE_UINT32(vbe_line_offset, VGACommonState),
  1980. VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
  1981. VMSTATE_END_OF_LIST()
  1982. },
  1983. .subsections = (const VMStateDescription * const []) {
  1984. &vmstate_vga_endian,
  1985. NULL
  1986. }
  1987. };
  1988. static const GraphicHwOps vga_ops = {
  1989. .invalidate = vga_invalidate_display,
  1990. .gfx_update = vga_update_display,
  1991. .text_update = vga_update_text,
  1992. };
  1993. static inline uint32_t uint_clamp(uint32_t val, uint32_t vmin, uint32_t vmax)
  1994. {
  1995. if (val < vmin) {
  1996. return vmin;
  1997. }
  1998. if (val > vmax) {
  1999. return vmax;
  2000. }
  2001. return val;
  2002. }
  2003. bool vga_common_init(VGACommonState *s, Object *obj, Error **errp)
  2004. {
  2005. int i, j, v, b;
  2006. Error *local_err = NULL;
  2007. for(i = 0;i < 256; i++) {
  2008. v = 0;
  2009. for(j = 0; j < 8; j++) {
  2010. v |= ((i >> j) & 1) << (j * 4);
  2011. }
  2012. expand4[i] = v;
  2013. v = 0;
  2014. for(j = 0; j < 4; j++) {
  2015. v |= ((i >> (2 * j)) & 3) << (j * 4);
  2016. }
  2017. expand2[i] = v;
  2018. }
  2019. for(i = 0; i < 16; i++) {
  2020. v = 0;
  2021. for(j = 0; j < 4; j++) {
  2022. b = ((i >> j) & 1);
  2023. v |= b << (2 * j);
  2024. v |= b << (2 * j + 1);
  2025. }
  2026. expand4to8[i] = v;
  2027. }
  2028. s->vram_size_mb = uint_clamp(s->vram_size_mb, 1, 512);
  2029. s->vram_size_mb = pow2ceil(s->vram_size_mb);
  2030. s->vram_size = s->vram_size_mb * MiB;
  2031. if (!s->vbe_size) {
  2032. s->vbe_size = s->vram_size;
  2033. }
  2034. s->vbe_size_mask = s->vbe_size - 1;
  2035. s->is_vbe_vmstate = 1;
  2036. if (s->global_vmstate && qemu_ram_block_by_name("vga.vram")) {
  2037. error_setg(errp, "Only one global VGA device can be used at a time");
  2038. return false;
  2039. }
  2040. memory_region_init_ram_nomigrate(&s->vram, obj, "vga.vram", s->vram_size,
  2041. &local_err);
  2042. if (local_err) {
  2043. error_propagate(errp, local_err);
  2044. return false;
  2045. }
  2046. vmstate_register_ram(&s->vram, s->global_vmstate ? NULL : DEVICE(obj));
  2047. xen_register_framebuffer(&s->vram);
  2048. s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
  2049. s->get_bpp = vga_get_bpp;
  2050. s->get_params = vga_get_params;
  2051. s->get_resolution = vga_get_resolution;
  2052. s->hw_ops = &vga_ops;
  2053. switch (vga_retrace_method) {
  2054. case VGA_RETRACE_DUMB:
  2055. s->retrace = vga_dumb_retrace;
  2056. s->update_retrace_info = vga_dumb_update_retrace_info;
  2057. break;
  2058. case VGA_RETRACE_PRECISE:
  2059. s->retrace = vga_precise_retrace;
  2060. s->update_retrace_info = vga_precise_update_retrace_info;
  2061. break;
  2062. }
  2063. /*
  2064. * Set default fb endian based on target, could probably be turned
  2065. * into a device attribute set by the machine/platform to remove
  2066. * all target endian dependencies from this file.
  2067. */
  2068. s->default_endian_fb = target_words_bigendian();
  2069. s->big_endian_fb = s->default_endian_fb;
  2070. vga_dirty_log_start(s);
  2071. return true;
  2072. }
  2073. static const MemoryRegionPortio vga_portio_list[] = {
  2074. { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
  2075. { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
  2076. { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
  2077. { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
  2078. { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
  2079. PORTIO_END_OF_LIST(),
  2080. };
  2081. static const MemoryRegionPortio vbe_portio_list_x86[] = {
  2082. { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
  2083. { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
  2084. { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
  2085. PORTIO_END_OF_LIST(),
  2086. };
  2087. static const MemoryRegionPortio vbe_portio_list_no_x86[] = {
  2088. { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
  2089. { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
  2090. PORTIO_END_OF_LIST(),
  2091. };
  2092. /* Used by both ISA and PCI */
  2093. MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
  2094. const MemoryRegionPortio **vga_ports,
  2095. const MemoryRegionPortio **vbe_ports)
  2096. {
  2097. MemoryRegion *vga_mem;
  2098. MachineState *ms = MACHINE(qdev_get_machine());
  2099. /*
  2100. * We unfortunately need two VBE lists since non-x86 machines might
  2101. * not be able to do 16-bit accesses at unaligned addresses (0x1cf)
  2102. */
  2103. if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
  2104. *vbe_ports = vbe_portio_list_x86;
  2105. } else {
  2106. *vbe_ports = vbe_portio_list_no_x86;
  2107. }
  2108. *vga_ports = vga_portio_list;
  2109. vga_mem = g_malloc(sizeof(*vga_mem));
  2110. memory_region_init_io(vga_mem, obj, &vga_mem_ops, s,
  2111. "vga-lowmem", 0x20000);
  2112. memory_region_set_flush_coalesced(vga_mem);
  2113. return vga_mem;
  2114. }
  2115. void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
  2116. MemoryRegion *address_space_io, bool init_vga_ports)
  2117. {
  2118. MemoryRegion *vga_io_memory;
  2119. const MemoryRegionPortio *vga_ports, *vbe_ports;
  2120. qemu_register_reset(vga_reset, s);
  2121. s->bank_offset = 0;
  2122. s->legacy_address_space = address_space;
  2123. vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
  2124. memory_region_add_subregion_overlap(address_space,
  2125. 0x000a0000,
  2126. vga_io_memory,
  2127. 1);
  2128. memory_region_set_coalescing(vga_io_memory);
  2129. if (init_vga_ports) {
  2130. portio_list_init(&s->vga_port_list, obj, vga_ports, s, "vga");
  2131. portio_list_set_flush_coalesced(&s->vga_port_list);
  2132. portio_list_add(&s->vga_port_list, address_space_io, 0x3b0);
  2133. }
  2134. if (vbe_ports) {
  2135. portio_list_init(&s->vbe_port_list, obj, vbe_ports, s, "vbe");
  2136. portio_list_add(&s->vbe_port_list, address_space_io, 0x1ce);
  2137. }
  2138. }