riscv_htif.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361
  1. /*
  2. * QEMU RISC-V Host Target Interface (HTIF) Emulation
  3. *
  4. * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
  5. * Copyright (c) 2017-2018 SiFive, Inc.
  6. *
  7. * This provides HTIF device emulation for QEMU. At the moment this allows
  8. * for identical copies of bbl/linux to run on both spike and QEMU.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms and conditions of the GNU General Public License,
  12. * version 2 or later, as published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #include "qemu/osdep.h"
  23. #include "qapi/error.h"
  24. #include "qemu/log.h"
  25. #include "hw/char/riscv_htif.h"
  26. #include "chardev/char.h"
  27. #include "chardev/char-fe.h"
  28. #include "qemu/timer.h"
  29. #include "qemu/error-report.h"
  30. #include "exec/address-spaces.h"
  31. #include "exec/tswap.h"
  32. #include "system/dma.h"
  33. #include "system/runstate.h"
  34. #include "trace.h"
  35. #define HTIF_DEV_SHIFT 56
  36. #define HTIF_CMD_SHIFT 48
  37. #define HTIF_DEV_SYSTEM 0
  38. #define HTIF_DEV_CONSOLE 1
  39. #define HTIF_SYSTEM_CMD_SYSCALL 0
  40. #define HTIF_CONSOLE_CMD_GETC 0
  41. #define HTIF_CONSOLE_CMD_PUTC 1
  42. /* PK system call number */
  43. #define PK_SYS_WRITE 64
  44. const char *sig_file;
  45. uint8_t line_size = 16;
  46. static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr;
  47. void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
  48. uint64_t st_size)
  49. {
  50. if (strcmp("fromhost", st_name) == 0) {
  51. fromhost_addr = st_value;
  52. if (st_size != 8) {
  53. error_report("HTIF fromhost must be 8 bytes");
  54. exit(1);
  55. }
  56. } else if (strcmp("tohost", st_name) == 0) {
  57. tohost_addr = st_value;
  58. if (st_size != 8) {
  59. error_report("HTIF tohost must be 8 bytes");
  60. exit(1);
  61. }
  62. } else if (strcmp("begin_signature", st_name) == 0) {
  63. begin_sig_addr = st_value;
  64. } else if (strcmp("end_signature", st_name) == 0) {
  65. end_sig_addr = st_value;
  66. }
  67. }
  68. /*
  69. * Called by the char dev to see if HTIF is ready to accept input.
  70. */
  71. static int htif_can_recv(void *opaque)
  72. {
  73. return 1;
  74. }
  75. /*
  76. * Called by the char dev to supply input to HTIF console.
  77. * We assume that we will receive one character at a time.
  78. */
  79. static void htif_recv(void *opaque, const uint8_t *buf, int size)
  80. {
  81. HTIFState *s = opaque;
  82. if (size != 1) {
  83. return;
  84. }
  85. /*
  86. * TODO - we need to check whether mfromhost is zero which indicates
  87. * the device is ready to receive. The current implementation
  88. * will drop characters
  89. */
  90. uint64_t val_written = s->pending_read;
  91. uint64_t resp = 0x100 | *buf;
  92. s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
  93. }
  94. /*
  95. * Called by the char dev to supply special events to the HTIF console.
  96. * Not used for HTIF.
  97. */
  98. static void htif_event(void *opaque, QEMUChrEvent event)
  99. {
  100. }
  101. static int htif_be_change(void *opaque)
  102. {
  103. HTIFState *s = opaque;
  104. qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
  105. htif_be_change, s, NULL, true);
  106. return 0;
  107. }
  108. /*
  109. * See below the tohost register format.
  110. *
  111. * Bits 63:56 indicate the "device".
  112. * Bits 55:48 indicate the "command".
  113. *
  114. * Device 0 is the syscall device, which is used to emulate Unixy syscalls.
  115. * It only implements command 0, which has two subfunctions:
  116. * - If bit 0 is clear, then bits 47:0 represent a pointer to a struct
  117. * describing the syscall.
  118. * - If bit 1 is set, then bits 47:1 represent an exit code, with a zero
  119. * value indicating success and other values indicating failure.
  120. *
  121. * Device 1 is the blocking character device.
  122. * - Command 0 reads a character
  123. * - Command 1 writes a character from the 8 LSBs of tohost
  124. *
  125. * For RV32, the tohost register is zero-extended, so only device=0 and
  126. * command=0 (i.e. HTIF syscalls/exit codes) are supported.
  127. */
  128. static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
  129. {
  130. uint8_t device = val_written >> HTIF_DEV_SHIFT;
  131. uint8_t cmd = val_written >> HTIF_CMD_SHIFT;
  132. uint64_t payload = val_written & 0xFFFFFFFFFFFFULL;
  133. int resp = 0;
  134. trace_htif_uart_write_to_host(device, cmd, payload);
  135. /*
  136. * Currently, there is a fixed mapping of devices:
  137. * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy)
  138. * 1: Console
  139. */
  140. if (unlikely(device == HTIF_DEV_SYSTEM)) {
  141. /* frontend syscall handler, shutdown and exit code support */
  142. if (cmd == HTIF_SYSTEM_CMD_SYSCALL) {
  143. if (payload & 0x1) {
  144. /* exit code */
  145. int exit_code = payload >> 1;
  146. /*
  147. * Dump signature data if sig_file is specified and
  148. * begin/end_signature symbols exist.
  149. */
  150. if (sig_file && begin_sig_addr && end_sig_addr) {
  151. uint64_t sig_len = end_sig_addr - begin_sig_addr;
  152. char *sig_data = g_malloc(sig_len);
  153. dma_memory_read(&address_space_memory, begin_sig_addr,
  154. sig_data, sig_len, MEMTXATTRS_UNSPECIFIED);
  155. FILE *signature = fopen(sig_file, "w");
  156. if (signature == NULL) {
  157. error_report("Unable to open %s with error %s",
  158. sig_file, strerror(errno));
  159. exit(1);
  160. }
  161. for (int i = 0; i < sig_len; i += line_size) {
  162. for (int j = line_size; j > 0; j--) {
  163. if (i + j <= sig_len) {
  164. fprintf(signature, "%02x",
  165. sig_data[i + j - 1] & 0xff);
  166. } else {
  167. fprintf(signature, "%02x", 0);
  168. }
  169. }
  170. fprintf(signature, "\n");
  171. }
  172. fclose(signature);
  173. g_free(sig_data);
  174. }
  175. qemu_system_shutdown_request_with_code(
  176. SHUTDOWN_CAUSE_GUEST_SHUTDOWN, exit_code);
  177. return;
  178. } else {
  179. uint64_t syscall[8];
  180. cpu_physical_memory_read(payload, syscall, sizeof(syscall));
  181. if (le64_to_cpu(syscall[0]) == PK_SYS_WRITE &&
  182. le64_to_cpu(syscall[1]) == HTIF_DEV_CONSOLE &&
  183. le64_to_cpu(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
  184. uint8_t ch;
  185. cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch, 1);
  186. /*
  187. * XXX this blocks entire thread. Rewrite to use
  188. * qemu_chr_fe_write and background I/O callbacks
  189. */
  190. qemu_chr_fe_write_all(&s->chr, &ch, 1);
  191. resp = 0x100 | (uint8_t)payload;
  192. } else {
  193. qemu_log_mask(LOG_UNIMP,
  194. "pk syscall proxy not supported\n");
  195. }
  196. }
  197. } else {
  198. qemu_log("HTIF device %d: unknown command\n", device);
  199. }
  200. } else if (likely(device == HTIF_DEV_CONSOLE)) {
  201. /* HTIF Console */
  202. if (cmd == HTIF_CONSOLE_CMD_GETC) {
  203. /* this should be a queue, but not yet implemented as such */
  204. s->pending_read = val_written;
  205. s->tohost = 0; /* clear to indicate we read */
  206. return;
  207. } else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
  208. uint8_t ch = (uint8_t)payload;
  209. /*
  210. * XXX this blocks entire thread. Rewrite to use
  211. * qemu_chr_fe_write and background I/O callbacks
  212. */
  213. qemu_chr_fe_write_all(&s->chr, &ch, 1);
  214. resp = 0x100 | (uint8_t)payload;
  215. } else {
  216. qemu_log("HTIF device %d: unknown command\n", device);
  217. }
  218. } else {
  219. qemu_log("HTIF unknown device or command\n");
  220. trace_htif_uart_unknown_device_command(device, cmd, payload);
  221. }
  222. /*
  223. * Latest bbl does not set fromhost to 0 if there is a value in tohost.
  224. * With this code enabled, qemu hangs waiting for fromhost to go to 0.
  225. * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10.
  226. * HTIF needs protocol documentation and a more complete state machine.
  227. *
  228. * while (!s->fromhost_inprogress &&
  229. * s->fromhost != 0x0) {
  230. * }
  231. */
  232. s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
  233. s->tohost = 0; /* clear to indicate we read */
  234. }
  235. #define TOHOST_OFFSET1 (s->tohost_offset)
  236. #define TOHOST_OFFSET2 (s->tohost_offset + 4)
  237. #define FROMHOST_OFFSET1 (s->fromhost_offset)
  238. #define FROMHOST_OFFSET2 (s->fromhost_offset + 4)
  239. /* CPU wants to read an HTIF register */
  240. static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
  241. {
  242. HTIFState *s = opaque;
  243. if (addr == TOHOST_OFFSET1) {
  244. return s->tohost & 0xFFFFFFFF;
  245. } else if (addr == TOHOST_OFFSET2) {
  246. return (s->tohost >> 32) & 0xFFFFFFFF;
  247. } else if (addr == FROMHOST_OFFSET1) {
  248. return s->fromhost & 0xFFFFFFFF;
  249. } else if (addr == FROMHOST_OFFSET2) {
  250. return (s->fromhost >> 32) & 0xFFFFFFFF;
  251. } else {
  252. qemu_log("Invalid htif read: address %016" PRIx64 "\n",
  253. (uint64_t)addr);
  254. return 0;
  255. }
  256. }
  257. /* CPU wrote to an HTIF register */
  258. static void htif_mm_write(void *opaque, hwaddr addr,
  259. uint64_t value, unsigned size)
  260. {
  261. HTIFState *s = opaque;
  262. if (addr == TOHOST_OFFSET1) {
  263. if (s->tohost == 0x0) {
  264. s->allow_tohost = 1;
  265. s->tohost = value & 0xFFFFFFFF;
  266. } else {
  267. s->allow_tohost = 0;
  268. }
  269. } else if (addr == TOHOST_OFFSET2) {
  270. if (s->allow_tohost) {
  271. s->tohost |= value << 32;
  272. htif_handle_tohost_write(s, s->tohost);
  273. }
  274. } else if (addr == FROMHOST_OFFSET1) {
  275. s->fromhost_inprogress = 1;
  276. s->fromhost = value & 0xFFFFFFFF;
  277. } else if (addr == FROMHOST_OFFSET2) {
  278. s->fromhost |= value << 32;
  279. s->fromhost_inprogress = 0;
  280. } else {
  281. qemu_log("Invalid htif write: address %016" PRIx64 "\n",
  282. (uint64_t)addr);
  283. }
  284. }
  285. static const MemoryRegionOps htif_mm_ops = {
  286. .read = htif_mm_read,
  287. .write = htif_mm_write,
  288. .endianness = DEVICE_LITTLE_ENDIAN,
  289. .impl = {
  290. .min_access_size = 4,
  291. .max_access_size = 4,
  292. },
  293. };
  294. HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
  295. uint64_t nonelf_base, bool custom_base)
  296. {
  297. uint64_t base, size, tohost_offset, fromhost_offset;
  298. if (custom_base) {
  299. fromhost_addr = nonelf_base;
  300. tohost_addr = nonelf_base + 8;
  301. } else {
  302. if (!fromhost_addr || !tohost_addr) {
  303. error_report("Invalid HTIF fromhost or tohost address");
  304. exit(1);
  305. }
  306. }
  307. base = MIN(tohost_addr, fromhost_addr);
  308. size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
  309. tohost_offset = tohost_addr - base;
  310. fromhost_offset = fromhost_addr - base;
  311. HTIFState *s = g_new0(HTIFState, 1);
  312. s->tohost_offset = tohost_offset;
  313. s->fromhost_offset = fromhost_offset;
  314. s->pending_read = 0;
  315. s->allow_tohost = 0;
  316. s->fromhost_inprogress = 0;
  317. qemu_chr_fe_init(&s->chr, chr, &error_abort);
  318. qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
  319. htif_be_change, s, NULL, true);
  320. memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
  321. TYPE_HTIF_UART, size);
  322. memory_region_add_subregion_overlap(address_space, base,
  323. &s->mmio, 1);
  324. return s;
  325. }