2
0

debugcon.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144
  1. /*
  2. * QEMU Bochs-style debug console ("port E9") emulation
  3. *
  4. * Copyright (c) 2003-2004 Fabrice Bellard
  5. * Copyright (c) 2008 Citrix Systems, Inc.
  6. * Copyright (c) Intel Corporation; author: H. Peter Anvin
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a copy
  9. * of this software and associated documentation files (the "Software"), to deal
  10. * in the Software without restriction, including without limitation the rights
  11. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. * copies of the Software, and to permit persons to whom the Software is
  13. * furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice shall be included in
  16. * all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. * THE SOFTWARE.
  25. */
  26. #include "qemu/osdep.h"
  27. #include "qapi/error.h"
  28. #include "qemu/module.h"
  29. #include "chardev/char-fe.h"
  30. #include "hw/isa/isa.h"
  31. #include "hw/qdev-properties.h"
  32. #include "hw/qdev-properties-system.h"
  33. #include "qom/object.h"
  34. #define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
  35. OBJECT_DECLARE_SIMPLE_TYPE(ISADebugconState, ISA_DEBUGCON_DEVICE)
  36. //#define DEBUG_DEBUGCON
  37. typedef struct DebugconState {
  38. MemoryRegion io;
  39. CharBackend chr;
  40. uint32_t readback;
  41. } DebugconState;
  42. struct ISADebugconState {
  43. ISADevice parent_obj;
  44. uint32_t iobase;
  45. DebugconState state;
  46. };
  47. static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val,
  48. unsigned width)
  49. {
  50. DebugconState *s = opaque;
  51. unsigned char ch = val;
  52. #ifdef DEBUG_DEBUGCON
  53. printf(" [debugcon: write addr=0x%04" HWADDR_PRIx " val=0x%02" PRIx64 "]\n", addr, val);
  54. #endif
  55. /* XXX this blocks entire thread. Rewrite to use
  56. * qemu_chr_fe_write and background I/O callbacks */
  57. qemu_chr_fe_write_all(&s->chr, &ch, 1);
  58. }
  59. static uint64_t debugcon_ioport_read(void *opaque, hwaddr addr, unsigned width)
  60. {
  61. DebugconState *s = opaque;
  62. #ifdef DEBUG_DEBUGCON
  63. printf("debugcon: read addr=0x%04" HWADDR_PRIx "\n", addr);
  64. #endif
  65. return s->readback;
  66. }
  67. static const MemoryRegionOps debugcon_ops = {
  68. .read = debugcon_ioport_read,
  69. .write = debugcon_ioport_write,
  70. .valid.min_access_size = 1,
  71. .valid.max_access_size = 1,
  72. .endianness = DEVICE_LITTLE_ENDIAN,
  73. };
  74. static void debugcon_realize_core(DebugconState *s, Error **errp)
  75. {
  76. if (!qemu_chr_fe_backend_connected(&s->chr)) {
  77. error_setg(errp, "Can't create debugcon device, empty char device");
  78. return;
  79. }
  80. qemu_chr_fe_set_handlers(&s->chr, NULL, NULL, NULL, NULL, s, NULL, true);
  81. }
  82. static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)
  83. {
  84. ISADevice *d = ISA_DEVICE(dev);
  85. ISADebugconState *isa = ISA_DEBUGCON_DEVICE(dev);
  86. DebugconState *s = &isa->state;
  87. Error *err = NULL;
  88. debugcon_realize_core(s, &err);
  89. if (err != NULL) {
  90. error_propagate(errp, err);
  91. return;
  92. }
  93. memory_region_init_io(&s->io, OBJECT(dev), &debugcon_ops, s,
  94. TYPE_ISA_DEBUGCON_DEVICE, 1);
  95. memory_region_add_subregion(isa_address_space_io(d),
  96. isa->iobase, &s->io);
  97. }
  98. static const Property debugcon_isa_properties[] = {
  99. DEFINE_PROP_UINT32("iobase", ISADebugconState, iobase, 0xe9),
  100. DEFINE_PROP_CHR("chardev", ISADebugconState, state.chr),
  101. DEFINE_PROP_UINT32("readback", ISADebugconState, state.readback, 0xe9),
  102. };
  103. static void debugcon_isa_class_initfn(ObjectClass *klass, void *data)
  104. {
  105. DeviceClass *dc = DEVICE_CLASS(klass);
  106. dc->realize = debugcon_isa_realizefn;
  107. device_class_set_props(dc, debugcon_isa_properties);
  108. set_bit(DEVICE_CATEGORY_MISC, dc->categories);
  109. }
  110. static const TypeInfo debugcon_isa_info = {
  111. .name = TYPE_ISA_DEBUGCON_DEVICE,
  112. .parent = TYPE_ISA_DEVICE,
  113. .instance_size = sizeof(ISADebugconState),
  114. .class_init = debugcon_isa_class_initfn,
  115. };
  116. static void debugcon_register_types(void)
  117. {
  118. type_register_static(&debugcon_isa_info);
  119. }
  120. type_init(debugcon_register_types)