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xlnx-zcu102.c 9.8 KB

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  1. /*
  2. * Xilinx ZynqMP ZCU102 board
  3. *
  4. * Copyright (C) 2015 Xilinx Inc
  5. * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15. * for more details.
  16. */
  17. #include "qemu/osdep.h"
  18. #include "qapi/error.h"
  19. #include "hw/arm/xlnx-zynqmp.h"
  20. #include "hw/arm/boot.h"
  21. #include "hw/boards.h"
  22. #include "qemu/error-report.h"
  23. #include "qemu/log.h"
  24. #include "system/device_tree.h"
  25. #include "qom/object.h"
  26. #include "net/can_emu.h"
  27. #include "audio/audio.h"
  28. struct XlnxZCU102 {
  29. MachineState parent_obj;
  30. XlnxZynqMPState soc;
  31. bool secure;
  32. bool virt;
  33. CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
  34. struct arm_boot_info binfo;
  35. };
  36. #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
  37. OBJECT_DECLARE_SIMPLE_TYPE(XlnxZCU102, ZCU102_MACHINE)
  38. static bool zcu102_get_secure(Object *obj, Error **errp)
  39. {
  40. XlnxZCU102 *s = ZCU102_MACHINE(obj);
  41. return s->secure;
  42. }
  43. static void zcu102_set_secure(Object *obj, bool value, Error **errp)
  44. {
  45. XlnxZCU102 *s = ZCU102_MACHINE(obj);
  46. s->secure = value;
  47. }
  48. static bool zcu102_get_virt(Object *obj, Error **errp)
  49. {
  50. XlnxZCU102 *s = ZCU102_MACHINE(obj);
  51. return s->virt;
  52. }
  53. static void zcu102_set_virt(Object *obj, bool value, Error **errp)
  54. {
  55. XlnxZCU102 *s = ZCU102_MACHINE(obj);
  56. s->virt = value;
  57. }
  58. static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
  59. {
  60. XlnxZCU102 *s = container_of(binfo, XlnxZCU102, binfo);
  61. bool method_is_hvc;
  62. char **node_path;
  63. const char *r;
  64. int prop_len;
  65. int i;
  66. /* If EL3 is enabled, we keep all firmware nodes active. */
  67. if (!s->secure) {
  68. node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware",
  69. &error_fatal);
  70. for (i = 0; node_path && node_path[i]; i++) {
  71. r = qemu_fdt_getprop(fdt, node_path[i], "method", &prop_len, NULL);
  72. method_is_hvc = r && !strcmp("hvc", r);
  73. /* Allow HVC based firmware if EL2 is enabled. */
  74. if (method_is_hvc && s->virt) {
  75. continue;
  76. }
  77. qemu_fdt_setprop_string(fdt, node_path[i], "status", "disabled");
  78. }
  79. g_strfreev(node_path);
  80. }
  81. }
  82. static void bbram_attach_drive(XlnxBBRam *dev)
  83. {
  84. DriveInfo *dinfo;
  85. BlockBackend *blk;
  86. dinfo = drive_get_by_index(IF_PFLASH, 2);
  87. blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
  88. if (blk) {
  89. qdev_prop_set_drive(DEVICE(dev), "drive", blk);
  90. }
  91. }
  92. static void efuse_attach_drive(XlnxEFuse *dev)
  93. {
  94. DriveInfo *dinfo;
  95. BlockBackend *blk;
  96. dinfo = drive_get_by_index(IF_PFLASH, 3);
  97. blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
  98. if (blk) {
  99. qdev_prop_set_drive(DEVICE(dev), "drive", blk);
  100. }
  101. }
  102. static void xlnx_zcu102_init(MachineState *machine)
  103. {
  104. XlnxZCU102 *s = ZCU102_MACHINE(machine);
  105. int i;
  106. uint64_t ram_size = machine->ram_size;
  107. /* Create the memory region to pass to the SoC */
  108. if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) {
  109. error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of "
  110. "0x%llx", ram_size,
  111. XLNX_ZYNQMP_MAX_RAM_SIZE);
  112. exit(1);
  113. }
  114. if (ram_size < 0x08000000) {
  115. qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
  116. ram_size);
  117. }
  118. object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_XLNX_ZYNQMP);
  119. if (machine->audiodev) {
  120. qdev_prop_set_string(DEVICE(&s->soc.dp), "audiodev", machine->audiodev);
  121. }
  122. object_property_set_link(OBJECT(&s->soc), "ddr-ram", OBJECT(machine->ram),
  123. &error_abort);
  124. object_property_set_bool(OBJECT(&s->soc), "secure", s->secure,
  125. &error_fatal);
  126. object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
  127. &error_fatal);
  128. for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
  129. gchar *bus_name = g_strdup_printf("canbus%d", i);
  130. object_property_set_link(OBJECT(&s->soc), bus_name,
  131. OBJECT(s->canbus[i]), &error_fatal);
  132. g_free(bus_name);
  133. }
  134. qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
  135. /* Attach bbram backend, if given */
  136. bbram_attach_drive(&s->soc.bbram);
  137. /* Attach efuse backend, if given */
  138. efuse_attach_drive(&s->soc.efuse);
  139. /* Create and plug in the SD cards */
  140. for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
  141. BusState *bus;
  142. DriveInfo *di = drive_get(IF_SD, 0, i);
  143. BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
  144. DeviceState *carddev;
  145. char *bus_name;
  146. bus_name = g_strdup_printf("sd-bus%d", i);
  147. bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
  148. g_free(bus_name);
  149. if (!bus) {
  150. error_report("No SD bus found for SD card %d", i);
  151. exit(1);
  152. }
  153. carddev = qdev_new(TYPE_SD_CARD);
  154. qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
  155. qdev_realize_and_unref(carddev, bus, &error_fatal);
  156. }
  157. for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
  158. BusState *spi_bus;
  159. DeviceState *flash_dev;
  160. qemu_irq cs_line;
  161. DriveInfo *dinfo = drive_get(IF_MTD, 0, i);
  162. gchar *bus_name = g_strdup_printf("spi%d", i);
  163. spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
  164. g_free(bus_name);
  165. flash_dev = qdev_new("sst25wf080");
  166. if (dinfo) {
  167. qdev_prop_set_drive_err(flash_dev, "drive",
  168. blk_by_legacy_dinfo(dinfo), &error_fatal);
  169. }
  170. qdev_prop_set_uint8(flash_dev, "cs", i);
  171. qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
  172. cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
  173. sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line);
  174. }
  175. for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
  176. BusState *spi_bus;
  177. DeviceState *flash_dev;
  178. qemu_irq cs_line;
  179. DriveInfo *dinfo = drive_get(IF_MTD, 0, XLNX_ZYNQMP_NUM_SPIS + i);
  180. int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
  181. gchar *bus_name = g_strdup_printf("qspi%d", bus);
  182. spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
  183. g_free(bus_name);
  184. flash_dev = qdev_new("n25q512a11");
  185. if (dinfo) {
  186. qdev_prop_set_drive_err(flash_dev, "drive",
  187. blk_by_legacy_dinfo(dinfo), &error_fatal);
  188. }
  189. qdev_prop_set_uint8(flash_dev, "cs", i);
  190. qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
  191. cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
  192. sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line);
  193. }
  194. /* TODO create and connect IDE devices for ide_drive_get() */
  195. s->binfo.ram_size = ram_size;
  196. s->binfo.loader_start = 0;
  197. s->binfo.modify_dtb = zcu102_modify_dtb;
  198. s->binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
  199. arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
  200. }
  201. static void xlnx_zcu102_machine_instance_init(Object *obj)
  202. {
  203. XlnxZCU102 *s = ZCU102_MACHINE(obj);
  204. /* Default to secure mode being disabled */
  205. s->secure = false;
  206. /* Default to virt (EL2) being disabled */
  207. s->virt = false;
  208. object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
  209. (Object **)&s->canbus[0],
  210. object_property_allow_set_link,
  211. 0);
  212. object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
  213. (Object **)&s->canbus[1],
  214. object_property_allow_set_link,
  215. 0);
  216. }
  217. static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
  218. {
  219. MachineClass *mc = MACHINE_CLASS(oc);
  220. mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \
  221. "the value of smp";
  222. mc->init = xlnx_zcu102_init;
  223. mc->block_default_type = IF_IDE;
  224. mc->units_per_default_bus = 1;
  225. mc->ignore_memory_transaction_failures = true;
  226. mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
  227. mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
  228. mc->default_ram_id = "ddr-ram";
  229. mc->auto_create_sdcard = true;
  230. machine_add_audiodev_property(mc);
  231. object_class_property_add_bool(oc, "secure", zcu102_get_secure,
  232. zcu102_set_secure);
  233. object_class_property_set_description(oc, "secure",
  234. "Set on/off to enable/disable the ARM "
  235. "Security Extensions (TrustZone)");
  236. object_class_property_add_bool(oc, "virtualization", zcu102_get_virt,
  237. zcu102_set_virt);
  238. object_class_property_set_description(oc, "virtualization",
  239. "Set on/off to enable/disable emulating a "
  240. "guest CPU which implements the ARM "
  241. "Virtualization Extensions");
  242. }
  243. static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
  244. .name = TYPE_ZCU102_MACHINE,
  245. .parent = TYPE_MACHINE,
  246. .class_init = xlnx_zcu102_machine_class_init,
  247. .instance_init = xlnx_zcu102_machine_instance_init,
  248. .instance_size = sizeof(XlnxZCU102),
  249. };
  250. static void xlnx_zcu102_machine_init_register_types(void)
  251. {
  252. type_register_static(&xlnx_zcu102_machine_init_typeinfo);
  253. }
  254. type_init(xlnx_zcu102_machine_init_register_types)