npcm7xx_boards.c 19 KB

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  1. /*
  2. * Machine definitions for boards featuring an NPCM7xx SoC.
  3. *
  4. * Copyright 2020 Google LLC
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14. * for more details.
  15. */
  16. #include "qemu/osdep.h"
  17. #include "hw/arm/npcm7xx.h"
  18. #include "hw/core/cpu.h"
  19. #include "hw/i2c/i2c_mux_pca954x.h"
  20. #include "hw/i2c/smbus_eeprom.h"
  21. #include "hw/loader.h"
  22. #include "hw/nvram/eeprom_at24c.h"
  23. #include "hw/qdev-core.h"
  24. #include "hw/qdev-properties.h"
  25. #include "qapi/error.h"
  26. #include "qemu/datadir.h"
  27. #include "qemu/units.h"
  28. #include "system/blockdev.h"
  29. #include "system/system.h"
  30. #include "system/block-backend.h"
  31. #include "qemu/error-report.h"
  32. #define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \
  33. NPCM7XX_PWRON_STRAP_SPI0F18 | \
  34. NPCM7XX_PWRON_STRAP_SFAB | \
  35. NPCM7XX_PWRON_STRAP_BSPA | \
  36. NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) | \
  37. NPCM7XX_PWRON_STRAP_SECEN | \
  38. NPCM7XX_PWRON_STRAP_HIZ | \
  39. NPCM7XX_PWRON_STRAP_ECC | \
  40. NPCM7XX_PWRON_STRAP_RESERVE1 | \
  41. NPCM7XX_PWRON_STRAP_J2EN | \
  42. NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT))
  43. #define NPCM750_EVB_POWER_ON_STRAPS ( \
  44. NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
  45. #define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
  46. #define QUANTA_GBS_POWER_ON_STRAPS ( \
  47. NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
  48. #define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
  49. #define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
  50. static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
  51. static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
  52. {
  53. const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom;
  54. g_autofree char *filename = NULL;
  55. int ret;
  56. filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
  57. if (!filename) {
  58. error_report("Could not find ROM image '%s'", bios_name);
  59. if (!machine->kernel_filename) {
  60. /* We can't boot without a bootrom or a kernel image. */
  61. exit(1);
  62. }
  63. return;
  64. }
  65. ret = load_image_mr(filename, &soc->irom);
  66. if (ret < 0) {
  67. error_report("Failed to load ROM image '%s'", filename);
  68. exit(1);
  69. }
  70. }
  71. static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
  72. const char *flash_type, DriveInfo *dinfo)
  73. {
  74. DeviceState *flash;
  75. qemu_irq flash_cs;
  76. flash = qdev_new(flash_type);
  77. if (dinfo) {
  78. qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
  79. }
  80. qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
  81. flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
  82. qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
  83. }
  84. static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
  85. {
  86. memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
  87. object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
  88. &error_abort);
  89. }
  90. static void sdhci_attach_drive(SDHCIState *sdhci, int unit)
  91. {
  92. DriveInfo *di = drive_get(IF_SD, 0, unit);
  93. BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
  94. BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus");
  95. if (bus == NULL) {
  96. error_report("No SD bus found in SOC object");
  97. exit(1);
  98. }
  99. DeviceState *carddev = qdev_new(TYPE_SD_CARD);
  100. qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
  101. qdev_realize_and_unref(carddev, bus, &error_fatal);
  102. }
  103. static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
  104. uint32_t hw_straps)
  105. {
  106. NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
  107. Object *obj;
  108. obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
  109. &error_abort, NULL);
  110. object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
  111. return NPCM7XX(obj);
  112. }
  113. static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
  114. {
  115. g_assert(num < ARRAY_SIZE(soc->smbus));
  116. return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
  117. }
  118. static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
  119. NPCM7xxState *soc, const int *fan_counts)
  120. {
  121. SplitIRQ *splitters = machine->fan_splitter;
  122. /*
  123. * PWM 0~3 belong to module 0 output 0~3.
  124. * PWM 4~7 belong to module 1 output 0~3.
  125. */
  126. for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) {
  127. for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {
  128. int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;
  129. DeviceState *splitter;
  130. if (fan_counts[splitter_no] < 1) {
  131. continue;
  132. }
  133. object_initialize_child(OBJECT(machine), "fan-splitter[*]",
  134. &splitters[splitter_no], TYPE_SPLIT_IRQ);
  135. splitter = DEVICE(&splitters[splitter_no]);
  136. qdev_prop_set_uint16(splitter, "num-lines",
  137. fan_counts[splitter_no]);
  138. qdev_realize(splitter, NULL, &error_abort);
  139. qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",
  140. j, qdev_get_gpio_in(splitter, 0));
  141. }
  142. }
  143. }
  144. static void npcm7xx_connect_pwm_fan(NPCM7xxState *soc, SplitIRQ *splitter,
  145. int fan_no, int output_no)
  146. {
  147. DeviceState *fan;
  148. int fan_input;
  149. qemu_irq fan_duty_gpio;
  150. g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);
  151. /*
  152. * Fan 0~1 belong to module 0 input 0~1.
  153. * Fan 2~3 belong to module 1 input 0~1.
  154. * ...
  155. * Fan 14~15 belong to module 7 input 0~1.
  156. * Fan 16~17 belong to module 0 input 2~3.
  157. * Fan 18~19 belong to module 1 input 2~3.
  158. */
  159. if (fan_no < 16) {
  160. fan = DEVICE(&soc->mft[fan_no / 2]);
  161. fan_input = fan_no % 2;
  162. } else {
  163. fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);
  164. fan_input = fan_no % 2 + 2;
  165. }
  166. /* Connect the Fan to PWM module */
  167. fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);
  168. qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);
  169. }
  170. static void npcm750_evb_i2c_init(NPCM7xxState *soc)
  171. {
  172. /* lm75 temperature sensor on SVB, tmp105 is compatible */
  173. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48);
  174. /* lm75 temperature sensor on EB, tmp105 is compatible */
  175. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48);
  176. /* tmp100 temperature sensor on EB, tmp105 is compatible */
  177. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48);
  178. /* tmp100 temperature sensor on SVB, tmp105 is compatible */
  179. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
  180. }
  181. static void npcm750_evb_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
  182. {
  183. SplitIRQ *splitter = machine->fan_splitter;
  184. static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2};
  185. npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
  186. npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
  187. npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
  188. npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
  189. npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
  190. npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
  191. npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
  192. npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);
  193. npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);
  194. npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);
  195. npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);
  196. npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);
  197. npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);
  198. npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);
  199. npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);
  200. npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);
  201. npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);
  202. }
  203. static void quanta_gsj_i2c_init(NPCM7xxState *soc)
  204. {
  205. /* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */
  206. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c);
  207. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c);
  208. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
  209. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
  210. at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 0x55, 8192);
  211. at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 0x55, 8192);
  212. /*
  213. * i2c-11:
  214. * - power-brick@36: delta,dps800
  215. * - hotswap@15: ti,lm5066i
  216. */
  217. /*
  218. * i2c-12:
  219. * - ucd90160@6b
  220. */
  221. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 15), "pca9548", 0x75);
  222. }
  223. static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
  224. {
  225. SplitIRQ *splitter = machine->fan_splitter;
  226. static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0};
  227. npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
  228. npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
  229. npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
  230. npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
  231. npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
  232. npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
  233. npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
  234. }
  235. static void quanta_gbs_i2c_init(NPCM7xxState *soc)
  236. {
  237. /*
  238. * i2c-0:
  239. * pca9546@71
  240. *
  241. * i2c-1:
  242. * pca9535@24
  243. * pca9535@20
  244. * pca9535@21
  245. * pca9535@22
  246. * pca9535@23
  247. * pca9535@25
  248. * pca9535@26
  249. *
  250. * i2c-2:
  251. * sbtsi@4c
  252. *
  253. * i2c-5:
  254. * atmel,24c64@50 mb_fru
  255. * pca9546@71
  256. * - channel 0: max31725@54
  257. * - channel 1: max31725@55
  258. * - channel 2: max31725@5d
  259. * atmel,24c64@51 fan_fru
  260. * - channel 3: atmel,24c64@52 hsbp_fru
  261. *
  262. * i2c-6:
  263. * pca9545@73
  264. *
  265. * i2c-7:
  266. * pca9545@72
  267. *
  268. * i2c-8:
  269. * adi,adm1272@10
  270. *
  271. * i2c-9:
  272. * pca9546@71
  273. * - channel 0: isil,isl68137@60
  274. * - channel 1: isil,isl68137@61
  275. * - channel 2: isil,isl68137@63
  276. * - channel 3: isil,isl68137@45
  277. *
  278. * i2c-10:
  279. * pca9545@71
  280. *
  281. * i2c-11:
  282. * pca9545@76
  283. *
  284. * i2c-12:
  285. * maxim,max34451@4e
  286. * isil,isl68137@5d
  287. * isil,isl68137@5e
  288. *
  289. * i2c-14:
  290. * pca9545@70
  291. */
  292. }
  293. static void kudo_bmc_i2c_init(NPCM7xxState *soc)
  294. {
  295. I2CSlave *i2c_mux;
  296. i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1),
  297. TYPE_PCA9548, 0x75);
  298. /* tmp105 is compatible with the lm75 */
  299. i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x5c);
  300. i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x5c);
  301. i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), "tmp105", 0x5c);
  302. i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), "tmp105", 0x5c);
  303. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x77);
  304. i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77);
  305. at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192); /* mbfru */
  306. i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13),
  307. TYPE_PCA9548, 0x77);
  308. /* tmp105 is compatible with the lm75 */
  309. i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "tmp105", 0x48);
  310. i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 3), "tmp105", 0x49);
  311. i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48);
  312. i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49);
  313. at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192); /* bmcfru */
  314. /* TODO: Add remaining i2c devices. */
  315. }
  316. static void npcm750_evb_init(MachineState *machine)
  317. {
  318. NPCM7xxState *soc;
  319. soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
  320. npcm7xx_connect_dram(soc, machine->ram);
  321. qdev_realize(DEVICE(soc), NULL, &error_fatal);
  322. npcm7xx_load_bootrom(machine, soc);
  323. npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
  324. npcm750_evb_i2c_init(soc);
  325. npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc);
  326. npcm7xx_load_kernel(machine, soc);
  327. }
  328. static void quanta_gsj_init(MachineState *machine)
  329. {
  330. NPCM7xxState *soc;
  331. soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
  332. npcm7xx_connect_dram(soc, machine->ram);
  333. qdev_realize(DEVICE(soc), NULL, &error_fatal);
  334. npcm7xx_load_bootrom(machine, soc);
  335. npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
  336. drive_get(IF_MTD, 0, 0));
  337. quanta_gsj_i2c_init(soc);
  338. quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc);
  339. npcm7xx_load_kernel(machine, soc);
  340. }
  341. static void quanta_gbs_init(MachineState *machine)
  342. {
  343. NPCM7xxState *soc;
  344. soc = npcm7xx_create_soc(machine, QUANTA_GBS_POWER_ON_STRAPS);
  345. npcm7xx_connect_dram(soc, machine->ram);
  346. qdev_realize(DEVICE(soc), NULL, &error_fatal);
  347. npcm7xx_load_bootrom(machine, soc);
  348. npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f",
  349. drive_get(IF_MTD, 0, 0));
  350. quanta_gbs_i2c_init(soc);
  351. sdhci_attach_drive(&soc->mmc.sdhci, 0);
  352. npcm7xx_load_kernel(machine, soc);
  353. }
  354. static void kudo_bmc_init(MachineState *machine)
  355. {
  356. NPCM7xxState *soc;
  357. soc = npcm7xx_create_soc(machine, KUDO_BMC_POWER_ON_STRAPS);
  358. npcm7xx_connect_dram(soc, machine->ram);
  359. qdev_realize(DEVICE(soc), NULL, &error_fatal);
  360. npcm7xx_load_bootrom(machine, soc);
  361. npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f",
  362. drive_get(IF_MTD, 0, 0));
  363. npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
  364. drive_get(IF_MTD, 3, 0));
  365. kudo_bmc_i2c_init(soc);
  366. sdhci_attach_drive(&soc->mmc.sdhci, 0);
  367. npcm7xx_load_kernel(machine, soc);
  368. }
  369. static void mori_bmc_init(MachineState *machine)
  370. {
  371. NPCM7xxState *soc;
  372. soc = npcm7xx_create_soc(machine, MORI_BMC_POWER_ON_STRAPS);
  373. npcm7xx_connect_dram(soc, machine->ram);
  374. qdev_realize(DEVICE(soc), NULL, &error_fatal);
  375. npcm7xx_load_bootrom(machine, soc);
  376. npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
  377. drive_get(IF_MTD, 3, 0));
  378. npcm7xx_load_kernel(machine, soc);
  379. }
  380. static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
  381. {
  382. NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
  383. MachineClass *mc = MACHINE_CLASS(nmc);
  384. nmc->soc_type = type;
  385. mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
  386. }
  387. static void npcm7xx_machine_class_init(ObjectClass *oc, void *data)
  388. {
  389. MachineClass *mc = MACHINE_CLASS(oc);
  390. static const char * const valid_cpu_types[] = {
  391. ARM_CPU_TYPE_NAME("cortex-a9"),
  392. NULL
  393. };
  394. mc->no_floppy = 1;
  395. mc->no_cdrom = 1;
  396. mc->no_parallel = 1;
  397. mc->default_ram_id = "ram";
  398. mc->valid_cpu_types = valid_cpu_types;
  399. }
  400. /*
  401. * Schematics:
  402. * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf
  403. */
  404. static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data)
  405. {
  406. NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
  407. MachineClass *mc = MACHINE_CLASS(oc);
  408. npcm7xx_set_soc_type(nmc, TYPE_NPCM750);
  409. mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex-A9)";
  410. mc->init = npcm750_evb_init;
  411. mc->auto_create_sdcard = true;
  412. mc->default_ram_size = 512 * MiB;
  413. };
  414. static void gsj_machine_class_init(ObjectClass *oc, void *data)
  415. {
  416. NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
  417. MachineClass *mc = MACHINE_CLASS(oc);
  418. npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
  419. mc->desc = "Quanta GSJ (Cortex-A9)";
  420. mc->init = quanta_gsj_init;
  421. mc->auto_create_sdcard = true;
  422. mc->default_ram_size = 512 * MiB;
  423. };
  424. static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data)
  425. {
  426. NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
  427. MachineClass *mc = MACHINE_CLASS(oc);
  428. npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
  429. mc->desc = "Quanta GBS (Cortex-A9)";
  430. mc->init = quanta_gbs_init;
  431. mc->auto_create_sdcard = true;
  432. mc->default_ram_size = 1 * GiB;
  433. }
  434. static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data)
  435. {
  436. NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
  437. MachineClass *mc = MACHINE_CLASS(oc);
  438. npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
  439. mc->desc = "Kudo BMC (Cortex-A9)";
  440. mc->init = kudo_bmc_init;
  441. mc->auto_create_sdcard = true;
  442. mc->default_ram_size = 1 * GiB;
  443. };
  444. static void mori_bmc_machine_class_init(ObjectClass *oc, void *data)
  445. {
  446. NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
  447. MachineClass *mc = MACHINE_CLASS(oc);
  448. npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
  449. mc->desc = "Mori BMC (Cortex-A9)";
  450. mc->init = mori_bmc_init;
  451. mc->auto_create_sdcard = true;
  452. mc->default_ram_size = 1 * GiB;
  453. }
  454. static const TypeInfo npcm7xx_machine_types[] = {
  455. {
  456. .name = TYPE_NPCM7XX_MACHINE,
  457. .parent = TYPE_MACHINE,
  458. .instance_size = sizeof(NPCM7xxMachine),
  459. .class_size = sizeof(NPCM7xxMachineClass),
  460. .class_init = npcm7xx_machine_class_init,
  461. .abstract = true,
  462. }, {
  463. .name = MACHINE_TYPE_NAME("npcm750-evb"),
  464. .parent = TYPE_NPCM7XX_MACHINE,
  465. .class_init = npcm750_evb_machine_class_init,
  466. }, {
  467. .name = MACHINE_TYPE_NAME("quanta-gsj"),
  468. .parent = TYPE_NPCM7XX_MACHINE,
  469. .class_init = gsj_machine_class_init,
  470. }, {
  471. .name = MACHINE_TYPE_NAME("quanta-gbs-bmc"),
  472. .parent = TYPE_NPCM7XX_MACHINE,
  473. .class_init = gbs_bmc_machine_class_init,
  474. }, {
  475. .name = MACHINE_TYPE_NAME("kudo-bmc"),
  476. .parent = TYPE_NPCM7XX_MACHINE,
  477. .class_init = kudo_bmc_machine_class_init,
  478. }, {
  479. .name = MACHINE_TYPE_NAME("mori-bmc"),
  480. .parent = TYPE_NPCM7XX_MACHINE,
  481. .class_init = mori_bmc_machine_class_init,
  482. },
  483. };
  484. DEFINE_TYPES(npcm7xx_machine_types)