aspeed_ast10x0.c 17 KB

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  1. /*
  2. * ASPEED Ast10x0 SoC
  3. *
  4. * Copyright (C) 2022 ASPEED Technology Inc.
  5. *
  6. * This code is licensed under the GPL version 2 or later. See
  7. * the COPYING file in the top-level directory.
  8. *
  9. * Implementation extracted from the AST2600 and adapted for Ast10x0.
  10. */
  11. #include "qemu/osdep.h"
  12. #include "qapi/error.h"
  13. #include "exec/address-spaces.h"
  14. #include "system/system.h"
  15. #include "hw/qdev-clock.h"
  16. #include "hw/misc/unimp.h"
  17. #include "hw/arm/aspeed_soc.h"
  18. #define ASPEED_SOC_IOMEM_SIZE 0x00200000
  19. static const hwaddr aspeed_soc_ast1030_memmap[] = {
  20. [ASPEED_DEV_SRAM] = 0x00000000,
  21. [ASPEED_DEV_SECSRAM] = 0x79000000,
  22. [ASPEED_DEV_IOMEM] = 0x7E600000,
  23. [ASPEED_DEV_PWM] = 0x7E610000,
  24. [ASPEED_DEV_FMC] = 0x7E620000,
  25. [ASPEED_DEV_SPI1] = 0x7E630000,
  26. [ASPEED_DEV_SPI2] = 0x7E640000,
  27. [ASPEED_DEV_UDC] = 0x7E6A2000,
  28. [ASPEED_DEV_HACE] = 0x7E6D0000,
  29. [ASPEED_DEV_SCU] = 0x7E6E2000,
  30. [ASPEED_DEV_JTAG0] = 0x7E6E4000,
  31. [ASPEED_DEV_JTAG1] = 0x7E6E4100,
  32. [ASPEED_DEV_ADC] = 0x7E6E9000,
  33. [ASPEED_DEV_ESPI] = 0x7E6EE000,
  34. [ASPEED_DEV_SBC] = 0x7E6F2000,
  35. [ASPEED_DEV_GPIO] = 0x7E780000,
  36. [ASPEED_DEV_SGPIOM] = 0x7E780500,
  37. [ASPEED_DEV_TIMER1] = 0x7E782000,
  38. [ASPEED_DEV_UART1] = 0x7E783000,
  39. [ASPEED_DEV_UART2] = 0x7E78D000,
  40. [ASPEED_DEV_UART3] = 0x7E78E000,
  41. [ASPEED_DEV_UART4] = 0x7E78F000,
  42. [ASPEED_DEV_UART5] = 0x7E784000,
  43. [ASPEED_DEV_UART6] = 0x7E790000,
  44. [ASPEED_DEV_UART7] = 0x7E790100,
  45. [ASPEED_DEV_UART8] = 0x7E790200,
  46. [ASPEED_DEV_UART9] = 0x7E790300,
  47. [ASPEED_DEV_UART10] = 0x7E790400,
  48. [ASPEED_DEV_UART11] = 0x7E790500,
  49. [ASPEED_DEV_UART12] = 0x7E790600,
  50. [ASPEED_DEV_UART13] = 0x7E790700,
  51. [ASPEED_DEV_WDT] = 0x7E785000,
  52. [ASPEED_DEV_LPC] = 0x7E789000,
  53. [ASPEED_DEV_PECI] = 0x7E78B000,
  54. [ASPEED_DEV_I3C] = 0x7E7A0000,
  55. [ASPEED_DEV_I2C] = 0x7E7B0000,
  56. };
  57. static const int aspeed_soc_ast1030_irqmap[] = {
  58. [ASPEED_DEV_UART1] = 47,
  59. [ASPEED_DEV_UART2] = 48,
  60. [ASPEED_DEV_UART3] = 49,
  61. [ASPEED_DEV_UART4] = 50,
  62. [ASPEED_DEV_UART5] = 8,
  63. [ASPEED_DEV_UART6] = 57,
  64. [ASPEED_DEV_UART7] = 58,
  65. [ASPEED_DEV_UART8] = 59,
  66. [ASPEED_DEV_UART9] = 60,
  67. [ASPEED_DEV_UART10] = 61,
  68. [ASPEED_DEV_UART11] = 62,
  69. [ASPEED_DEV_UART12] = 63,
  70. [ASPEED_DEV_UART13] = 64,
  71. [ASPEED_DEV_GPIO] = 11,
  72. [ASPEED_DEV_TIMER1] = 16,
  73. [ASPEED_DEV_TIMER2] = 17,
  74. [ASPEED_DEV_TIMER3] = 18,
  75. [ASPEED_DEV_TIMER4] = 19,
  76. [ASPEED_DEV_TIMER5] = 20,
  77. [ASPEED_DEV_TIMER6] = 21,
  78. [ASPEED_DEV_TIMER7] = 22,
  79. [ASPEED_DEV_TIMER8] = 23,
  80. [ASPEED_DEV_WDT] = 24,
  81. [ASPEED_DEV_LPC] = 35,
  82. [ASPEED_DEV_PECI] = 38,
  83. [ASPEED_DEV_FMC] = 39,
  84. [ASPEED_DEV_ESPI] = 42,
  85. [ASPEED_DEV_PWM] = 44,
  86. [ASPEED_DEV_ADC] = 46,
  87. [ASPEED_DEV_SPI1] = 65,
  88. [ASPEED_DEV_SPI2] = 66,
  89. [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */
  90. [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
  91. [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
  92. [ASPEED_DEV_UDC] = 9,
  93. [ASPEED_DEV_SGPIOM] = 51,
  94. [ASPEED_DEV_JTAG0] = 27,
  95. [ASPEED_DEV_JTAG1] = 53,
  96. };
  97. static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
  98. {
  99. Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
  100. AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
  101. return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
  102. }
  103. static void aspeed_soc_ast1030_init(Object *obj)
  104. {
  105. Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
  106. AspeedSoCState *s = ASPEED_SOC(obj);
  107. AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
  108. char socname[8];
  109. char typename[64];
  110. int i;
  111. if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
  112. g_assert_not_reached();
  113. }
  114. object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
  115. s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
  116. snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
  117. object_initialize_child(obj, "scu", &s->scu, typename);
  118. qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
  119. object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
  120. object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
  121. snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
  122. object_initialize_child(obj, "i2c", &s->i2c, typename);
  123. object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
  124. snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
  125. object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
  126. snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
  127. object_initialize_child(obj, "adc", &s->adc, typename);
  128. snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
  129. object_initialize_child(obj, "fmc", &s->fmc, typename);
  130. for (i = 0; i < sc->spis_num; i++) {
  131. snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
  132. object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
  133. }
  134. object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
  135. object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
  136. object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
  137. for (i = 0; i < sc->wdts_num; i++) {
  138. snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
  139. object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
  140. }
  141. for (i = 0; i < sc->uarts_num; i++) {
  142. object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
  143. }
  144. snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
  145. object_initialize_child(obj, "gpio", &s->gpio, typename);
  146. snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
  147. object_initialize_child(obj, "hace", &s->hace, typename);
  148. object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
  149. object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
  150. TYPE_UNIMPLEMENTED_DEVICE);
  151. object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
  152. object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
  153. object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
  154. object_initialize_child(obj, "sgpiom", &s->sgpiom,
  155. TYPE_UNIMPLEMENTED_DEVICE);
  156. object_initialize_child(obj, "jtag[0]", &s->jtag[0],
  157. TYPE_UNIMPLEMENTED_DEVICE);
  158. object_initialize_child(obj, "jtag[1]", &s->jtag[1],
  159. TYPE_UNIMPLEMENTED_DEVICE);
  160. }
  161. static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
  162. {
  163. Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
  164. AspeedSoCState *s = ASPEED_SOC(dev_soc);
  165. AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
  166. DeviceState *armv7m;
  167. Error *err = NULL;
  168. int i;
  169. g_autofree char *sram_name = NULL;
  170. if (!clock_has_source(s->sysclk)) {
  171. error_setg(errp, "sysclk clock must be wired up by the board code");
  172. return;
  173. }
  174. /* General I/O memory space to catch all unimplemented device */
  175. aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
  176. sc->memmap[ASPEED_DEV_IOMEM],
  177. ASPEED_SOC_IOMEM_SIZE);
  178. aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented),
  179. "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC],
  180. 0x40000);
  181. /* AST1030 CPU Core */
  182. armv7m = DEVICE(&a->armv7m);
  183. qdev_prop_set_uint32(armv7m, "num-irq", 256);
  184. qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
  185. qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
  186. object_property_set_link(OBJECT(&a->armv7m), "memory",
  187. OBJECT(s->memory), &error_abort);
  188. sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
  189. /* Internal SRAM */
  190. sram_name = g_strdup_printf("aspeed.sram.%d",
  191. CPU(a->armv7m.cpu)->cpu_index);
  192. memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
  193. if (err != NULL) {
  194. error_propagate(errp, err);
  195. return;
  196. }
  197. memory_region_add_subregion(s->memory,
  198. sc->memmap[ASPEED_DEV_SRAM],
  199. &s->sram);
  200. memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
  201. sc->secsram_size, &err);
  202. if (err != NULL) {
  203. error_propagate(errp, err);
  204. return;
  205. }
  206. memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
  207. &s->secsram);
  208. /* SCU */
  209. if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
  210. return;
  211. }
  212. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
  213. /* I2C */
  214. object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram),
  215. &error_abort);
  216. if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
  217. return;
  218. }
  219. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
  220. for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
  221. qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
  222. sc->irqmap[ASPEED_DEV_I2C] + i);
  223. /* The AST1030 I2C controller has one IRQ per bus. */
  224. sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
  225. }
  226. /* I3C */
  227. if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
  228. return;
  229. }
  230. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
  231. for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
  232. qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
  233. sc->irqmap[ASPEED_DEV_I3C] + i);
  234. /* The AST1030 I3C controller has one IRQ per bus. */
  235. sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
  236. }
  237. /* PECI */
  238. if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
  239. return;
  240. }
  241. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
  242. sc->memmap[ASPEED_DEV_PECI]);
  243. sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
  244. aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
  245. /* LPC */
  246. if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
  247. return;
  248. }
  249. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
  250. /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
  251. sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
  252. aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
  253. /*
  254. * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
  255. */
  256. sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
  257. qdev_get_gpio_in(DEVICE(&a->armv7m),
  258. sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
  259. sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
  260. qdev_get_gpio_in(DEVICE(&a->armv7m),
  261. sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
  262. sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
  263. qdev_get_gpio_in(DEVICE(&a->armv7m),
  264. sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
  265. sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
  266. qdev_get_gpio_in(DEVICE(&a->armv7m),
  267. sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
  268. /* UART */
  269. if (!aspeed_soc_uart_realize(s, errp)) {
  270. return;
  271. }
  272. /* Timer */
  273. object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
  274. &error_abort);
  275. if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
  276. return;
  277. }
  278. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
  279. sc->memmap[ASPEED_DEV_TIMER1]);
  280. for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
  281. qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
  282. sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
  283. }
  284. /* ADC */
  285. if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
  286. return;
  287. }
  288. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
  289. sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
  290. aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
  291. /* FMC, The number of CS is set at the board level */
  292. object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
  293. &error_abort);
  294. if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
  295. return;
  296. }
  297. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
  298. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
  299. ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
  300. sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
  301. aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
  302. /* SPI */
  303. for (i = 0; i < sc->spis_num; i++) {
  304. object_property_set_link(OBJECT(&s->spi[i]), "dram",
  305. OBJECT(&s->sram), &error_abort);
  306. if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
  307. return;
  308. }
  309. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
  310. sc->memmap[ASPEED_DEV_SPI1 + i]);
  311. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
  312. ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
  313. }
  314. /* Secure Boot Controller */
  315. if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
  316. return;
  317. }
  318. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
  319. /* HACE */
  320. object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
  321. &error_abort);
  322. if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
  323. return;
  324. }
  325. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
  326. sc->memmap[ASPEED_DEV_HACE]);
  327. sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
  328. aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
  329. /* Watch dog */
  330. for (i = 0; i < sc->wdts_num; i++) {
  331. AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
  332. hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
  333. object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
  334. &error_abort);
  335. if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
  336. return;
  337. }
  338. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
  339. }
  340. /* GPIO */
  341. if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
  342. return;
  343. }
  344. aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
  345. sc->memmap[ASPEED_DEV_GPIO]);
  346. sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
  347. aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
  348. aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm",
  349. sc->memmap[ASPEED_DEV_PWM], 0x100);
  350. aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi",
  351. sc->memmap[ASPEED_DEV_ESPI], 0x800);
  352. aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc",
  353. sc->memmap[ASPEED_DEV_UDC], 0x1000);
  354. aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom",
  355. sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
  356. aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag",
  357. sc->memmap[ASPEED_DEV_JTAG0], 0x20);
  358. aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag",
  359. sc->memmap[ASPEED_DEV_JTAG1], 0x20);
  360. }
  361. static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
  362. {
  363. static const char * const valid_cpu_types[] = {
  364. ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
  365. NULL
  366. };
  367. DeviceClass *dc = DEVICE_CLASS(klass);
  368. AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
  369. /* Reason: The Aspeed SoC can only be instantiated from a board */
  370. dc->user_creatable = false;
  371. dc->realize = aspeed_soc_ast1030_realize;
  372. sc->valid_cpu_types = valid_cpu_types;
  373. sc->silicon_rev = AST1030_A1_SILICON_REV;
  374. sc->sram_size = 0xc0000;
  375. sc->secsram_size = 0x40000; /* 256 * KiB */
  376. sc->spis_num = 2;
  377. sc->ehcis_num = 0;
  378. sc->wdts_num = 4;
  379. sc->macs_num = 1;
  380. sc->uarts_num = 13;
  381. sc->uarts_base = ASPEED_DEV_UART1;
  382. sc->irqmap = aspeed_soc_ast1030_irqmap;
  383. sc->memmap = aspeed_soc_ast1030_memmap;
  384. sc->num_cpus = 1;
  385. sc->get_irq = aspeed_soc_ast1030_get_irq;
  386. }
  387. static const TypeInfo aspeed_soc_ast10x0_types[] = {
  388. {
  389. .name = TYPE_ASPEED10X0_SOC,
  390. .parent = TYPE_ASPEED_SOC,
  391. .instance_size = sizeof(Aspeed10x0SoCState),
  392. .abstract = true,
  393. }, {
  394. .name = "ast1030-a1",
  395. .parent = TYPE_ASPEED10X0_SOC,
  396. .instance_init = aspeed_soc_ast1030_init,
  397. .class_init = aspeed_soc_ast1030_class_init,
  398. },
  399. };
  400. DEFINE_TYPES(aspeed_soc_ast10x0_types)