target_arch_cpu.h 4.5 KB

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  1. /*
  2. * RISC-V CPU init and loop
  3. *
  4. * Copyright (c) 2019 Mark Corbin
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef TARGET_ARCH_CPU_H
  20. #define TARGET_ARCH_CPU_H
  21. #include "target_arch.h"
  22. #include "signal-common.h"
  23. #define TARGET_DEFAULT_CPU_MODEL "max"
  24. static inline void target_cpu_init(CPURISCVState *env,
  25. struct target_pt_regs *regs)
  26. {
  27. int i;
  28. for (i = 1; i < 32; i++) {
  29. env->gpr[i] = regs->regs[i];
  30. }
  31. env->pc = regs->sepc;
  32. }
  33. static inline G_NORETURN void target_cpu_loop(CPURISCVState *env)
  34. {
  35. CPUState *cs = env_cpu(env);
  36. int trapnr;
  37. abi_long ret;
  38. unsigned int syscall_num;
  39. int32_t signo, code;
  40. for (;;) {
  41. cpu_exec_start(cs);
  42. trapnr = cpu_exec(cs);
  43. cpu_exec_end(cs);
  44. process_queued_cpu_work(cs);
  45. signo = 0;
  46. switch (trapnr) {
  47. case EXCP_INTERRUPT:
  48. /* just indicate that signals should be handled asap */
  49. break;
  50. case EXCP_ATOMIC:
  51. cpu_exec_step_atomic(cs);
  52. break;
  53. case RISCV_EXCP_U_ECALL:
  54. syscall_num = env->gpr[xT0];
  55. env->pc += TARGET_INSN_SIZE;
  56. /* Compare to cpu_fetch_syscall_args() in riscv/riscv/trap.c */
  57. if (TARGET_FREEBSD_NR___syscall == syscall_num ||
  58. TARGET_FREEBSD_NR_syscall == syscall_num) {
  59. ret = do_freebsd_syscall(env,
  60. env->gpr[xA0],
  61. env->gpr[xA1],
  62. env->gpr[xA2],
  63. env->gpr[xA3],
  64. env->gpr[xA4],
  65. env->gpr[xA5],
  66. env->gpr[xA6],
  67. env->gpr[xA7],
  68. 0);
  69. } else {
  70. ret = do_freebsd_syscall(env,
  71. syscall_num,
  72. env->gpr[xA0],
  73. env->gpr[xA1],
  74. env->gpr[xA2],
  75. env->gpr[xA3],
  76. env->gpr[xA4],
  77. env->gpr[xA5],
  78. env->gpr[xA6],
  79. env->gpr[xA7]
  80. );
  81. }
  82. /*
  83. * Compare to cpu_set_syscall_retval() in
  84. * riscv/riscv/vm_machdep.c
  85. */
  86. if (ret >= 0) {
  87. env->gpr[xA0] = ret;
  88. env->gpr[xT0] = 0;
  89. } else if (ret == -TARGET_ERESTART) {
  90. env->pc -= TARGET_INSN_SIZE;
  91. } else if (ret != -TARGET_EJUSTRETURN) {
  92. env->gpr[xA0] = -ret;
  93. env->gpr[xT0] = 1;
  94. }
  95. break;
  96. case RISCV_EXCP_ILLEGAL_INST:
  97. signo = TARGET_SIGILL;
  98. code = TARGET_ILL_ILLOPC;
  99. break;
  100. case RISCV_EXCP_BREAKPOINT:
  101. signo = TARGET_SIGTRAP;
  102. code = TARGET_TRAP_BRKPT;
  103. break;
  104. case EXCP_DEBUG:
  105. signo = TARGET_SIGTRAP;
  106. code = TARGET_TRAP_BRKPT;
  107. break;
  108. default:
  109. fprintf(stderr, "qemu: unhandled CPU exception "
  110. "0x%x - aborting\n", trapnr);
  111. cpu_dump_state(cs, stderr, 0);
  112. abort();
  113. }
  114. if (signo) {
  115. force_sig_fault(signo, code, env->pc);
  116. }
  117. process_pending_signals(env);
  118. }
  119. }
  120. static inline void target_cpu_clone_regs(CPURISCVState *env, target_ulong newsp)
  121. {
  122. if (newsp) {
  123. env->gpr[xSP] = newsp;
  124. }
  125. env->gpr[xA0] = 0;
  126. env->gpr[xT0] = 0;
  127. }
  128. static inline void target_cpu_reset(CPUArchState *env)
  129. {
  130. }
  131. #endif /* TARGET_ARCH_CPU_H */