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vm86.c 16 KB

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  1. /*
  2. * vm86 linux syscall support
  3. *
  4. * Copyright (c) 2003 Fabrice Bellard
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "qemu/osdep.h"
  20. #include "qemu.h"
  21. #include "user-internals.h"
  22. //#define DEBUG_VM86
  23. #ifdef DEBUG_VM86
  24. # define LOG_VM86(...) qemu_log(__VA_ARGS__);
  25. #else
  26. # define LOG_VM86(...) do { } while (0)
  27. #endif
  28. #define set_flags(X,new,mask) \
  29. ((X) = ((X) & ~(mask)) | ((new) & (mask)))
  30. #define SAFE_MASK (0xDD5)
  31. #define RETURN_MASK (0xDFF)
  32. static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
  33. {
  34. return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1;
  35. }
  36. static inline void vm_putw(CPUX86State *env, uint32_t segptr,
  37. unsigned int reg16, unsigned int val)
  38. {
  39. cpu_stw_data(env, segptr + (reg16 & 0xffff), val);
  40. }
  41. static inline void vm_putl(CPUX86State *env, uint32_t segptr,
  42. unsigned int reg16, unsigned int val)
  43. {
  44. cpu_stl_data(env, segptr + (reg16 & 0xffff), val);
  45. }
  46. static inline unsigned int vm_getb(CPUX86State *env,
  47. uint32_t segptr, unsigned int reg16)
  48. {
  49. return cpu_ldub_data(env, segptr + (reg16 & 0xffff));
  50. }
  51. static inline unsigned int vm_getw(CPUX86State *env,
  52. uint32_t segptr, unsigned int reg16)
  53. {
  54. return cpu_lduw_data(env, segptr + (reg16 & 0xffff));
  55. }
  56. static inline unsigned int vm_getl(CPUX86State *env,
  57. uint32_t segptr, unsigned int reg16)
  58. {
  59. return cpu_ldl_data(env, segptr + (reg16 & 0xffff));
  60. }
  61. void save_v86_state(CPUX86State *env)
  62. {
  63. CPUState *cs = env_cpu(env);
  64. TaskState *ts = cs->opaque;
  65. struct target_vm86plus_struct * target_v86;
  66. if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0))
  67. /* FIXME - should return an error */
  68. return;
  69. /* put the VM86 registers in the userspace register structure */
  70. target_v86->regs.eax = tswap32(env->regs[R_EAX]);
  71. target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
  72. target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
  73. target_v86->regs.edx = tswap32(env->regs[R_EDX]);
  74. target_v86->regs.esi = tswap32(env->regs[R_ESI]);
  75. target_v86->regs.edi = tswap32(env->regs[R_EDI]);
  76. target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
  77. target_v86->regs.esp = tswap32(env->regs[R_ESP]);
  78. target_v86->regs.eip = tswap32(env->eip);
  79. target_v86->regs.cs = tswap16(env->segs[R_CS].selector);
  80. target_v86->regs.ss = tswap16(env->segs[R_SS].selector);
  81. target_v86->regs.ds = tswap16(env->segs[R_DS].selector);
  82. target_v86->regs.es = tswap16(env->segs[R_ES].selector);
  83. target_v86->regs.fs = tswap16(env->segs[R_FS].selector);
  84. target_v86->regs.gs = tswap16(env->segs[R_GS].selector);
  85. set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
  86. target_v86->regs.eflags = tswap32(env->eflags);
  87. unlock_user_struct(target_v86, ts->target_v86, 1);
  88. LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
  89. env->eflags, env->segs[R_CS].selector, env->eip);
  90. /* restore 32 bit registers */
  91. env->regs[R_EAX] = ts->vm86_saved_regs.eax;
  92. env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
  93. env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
  94. env->regs[R_EDX] = ts->vm86_saved_regs.edx;
  95. env->regs[R_ESI] = ts->vm86_saved_regs.esi;
  96. env->regs[R_EDI] = ts->vm86_saved_regs.edi;
  97. env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
  98. env->regs[R_ESP] = ts->vm86_saved_regs.esp;
  99. env->eflags = ts->vm86_saved_regs.eflags;
  100. env->eip = ts->vm86_saved_regs.eip;
  101. cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
  102. cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
  103. cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
  104. cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
  105. cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
  106. cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
  107. }
  108. /* return from vm86 mode to 32 bit. The vm86() syscall will return
  109. 'retval' */
  110. static inline void return_to_32bit(CPUX86State *env, int retval)
  111. {
  112. LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
  113. save_v86_state(env);
  114. env->regs[R_EAX] = retval;
  115. }
  116. static inline int set_IF(CPUX86State *env)
  117. {
  118. CPUState *cs = env_cpu(env);
  119. TaskState *ts = cs->opaque;
  120. ts->v86flags |= VIF_MASK;
  121. if (ts->v86flags & VIP_MASK) {
  122. return_to_32bit(env, TARGET_VM86_STI);
  123. return 1;
  124. }
  125. return 0;
  126. }
  127. static inline void clear_IF(CPUX86State *env)
  128. {
  129. CPUState *cs = env_cpu(env);
  130. TaskState *ts = cs->opaque;
  131. ts->v86flags &= ~VIF_MASK;
  132. }
  133. static inline void clear_TF(CPUX86State *env)
  134. {
  135. env->eflags &= ~TF_MASK;
  136. }
  137. static inline void clear_AC(CPUX86State *env)
  138. {
  139. env->eflags &= ~AC_MASK;
  140. }
  141. static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
  142. {
  143. CPUState *cs = env_cpu(env);
  144. TaskState *ts = cs->opaque;
  145. set_flags(ts->v86flags, eflags, ts->v86mask);
  146. set_flags(env->eflags, eflags, SAFE_MASK);
  147. if (eflags & IF_MASK)
  148. return set_IF(env);
  149. else
  150. clear_IF(env);
  151. return 0;
  152. }
  153. static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
  154. {
  155. CPUState *cs = env_cpu(env);
  156. TaskState *ts = cs->opaque;
  157. set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
  158. set_flags(env->eflags, flags, SAFE_MASK);
  159. if (flags & IF_MASK)
  160. return set_IF(env);
  161. else
  162. clear_IF(env);
  163. return 0;
  164. }
  165. static inline unsigned int get_vflags(CPUX86State *env)
  166. {
  167. CPUState *cs = env_cpu(env);
  168. TaskState *ts = cs->opaque;
  169. unsigned int flags;
  170. flags = env->eflags & RETURN_MASK;
  171. if (ts->v86flags & VIF_MASK)
  172. flags |= IF_MASK;
  173. flags |= IOPL_MASK;
  174. return flags | (ts->v86flags & ts->v86mask);
  175. }
  176. #define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff)
  177. /* handle VM86 interrupt (NOTE: the CPU core currently does not
  178. support TSS interrupt revectoring, so this code is always executed) */
  179. static void do_int(CPUX86State *env, int intno)
  180. {
  181. CPUState *cs = env_cpu(env);
  182. TaskState *ts = cs->opaque;
  183. uint32_t int_addr, segoffs, ssp;
  184. unsigned int sp;
  185. if (env->segs[R_CS].selector == TARGET_BIOSSEG)
  186. goto cannot_handle;
  187. if (is_revectored(intno, &ts->vm86plus.int_revectored))
  188. goto cannot_handle;
  189. if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
  190. &ts->vm86plus.int21_revectored))
  191. goto cannot_handle;
  192. int_addr = (intno << 2);
  193. segoffs = cpu_ldl_data(env, int_addr);
  194. if ((segoffs >> 16) == TARGET_BIOSSEG)
  195. goto cannot_handle;
  196. LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
  197. intno, segoffs >> 16, segoffs & 0xffff);
  198. /* save old state */
  199. ssp = env->segs[R_SS].selector << 4;
  200. sp = env->regs[R_ESP] & 0xffff;
  201. vm_putw(env, ssp, sp - 2, get_vflags(env));
  202. vm_putw(env, ssp, sp - 4, env->segs[R_CS].selector);
  203. vm_putw(env, ssp, sp - 6, env->eip);
  204. ADD16(env->regs[R_ESP], -6);
  205. /* goto interrupt handler */
  206. env->eip = segoffs & 0xffff;
  207. cpu_x86_load_seg(env, R_CS, segoffs >> 16);
  208. clear_TF(env);
  209. clear_IF(env);
  210. clear_AC(env);
  211. return;
  212. cannot_handle:
  213. LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
  214. return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
  215. }
  216. void handle_vm86_trap(CPUX86State *env, int trapno)
  217. {
  218. if (trapno == 1 || trapno == 3) {
  219. return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
  220. } else {
  221. do_int(env, trapno);
  222. }
  223. }
  224. #define CHECK_IF_IN_TRAP() \
  225. if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
  226. (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \
  227. newflags |= TF_MASK
  228. #define VM86_FAULT_RETURN \
  229. if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
  230. (ts->v86flags & (IF_MASK | VIF_MASK))) \
  231. return_to_32bit(env, TARGET_VM86_PICRETURN); \
  232. return
  233. void handle_vm86_fault(CPUX86State *env)
  234. {
  235. CPUState *cs = env_cpu(env);
  236. TaskState *ts = cs->opaque;
  237. uint32_t csp, ssp;
  238. unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
  239. int data32, pref_done;
  240. csp = env->segs[R_CS].selector << 4;
  241. ip = env->eip & 0xffff;
  242. ssp = env->segs[R_SS].selector << 4;
  243. sp = env->regs[R_ESP] & 0xffff;
  244. LOG_VM86("VM86 exception %04x:%08x\n",
  245. env->segs[R_CS].selector, env->eip);
  246. data32 = 0;
  247. pref_done = 0;
  248. do {
  249. opcode = vm_getb(env, csp, ip);
  250. ADD16(ip, 1);
  251. switch (opcode) {
  252. case 0x66: /* 32-bit data */ data32=1; break;
  253. case 0x67: /* 32-bit address */ break;
  254. case 0x2e: /* CS */ break;
  255. case 0x3e: /* DS */ break;
  256. case 0x26: /* ES */ break;
  257. case 0x36: /* SS */ break;
  258. case 0x65: /* GS */ break;
  259. case 0x64: /* FS */ break;
  260. case 0xf2: /* repnz */ break;
  261. case 0xf3: /* rep */ break;
  262. default: pref_done = 1;
  263. }
  264. } while (!pref_done);
  265. /* VM86 mode */
  266. switch(opcode) {
  267. case 0x9c: /* pushf */
  268. if (data32) {
  269. vm_putl(env, ssp, sp - 4, get_vflags(env));
  270. ADD16(env->regs[R_ESP], -4);
  271. } else {
  272. vm_putw(env, ssp, sp - 2, get_vflags(env));
  273. ADD16(env->regs[R_ESP], -2);
  274. }
  275. env->eip = ip;
  276. VM86_FAULT_RETURN;
  277. case 0x9d: /* popf */
  278. if (data32) {
  279. newflags = vm_getl(env, ssp, sp);
  280. ADD16(env->regs[R_ESP], 4);
  281. } else {
  282. newflags = vm_getw(env, ssp, sp);
  283. ADD16(env->regs[R_ESP], 2);
  284. }
  285. env->eip = ip;
  286. CHECK_IF_IN_TRAP();
  287. if (data32) {
  288. if (set_vflags_long(newflags, env))
  289. return;
  290. } else {
  291. if (set_vflags_short(newflags, env))
  292. return;
  293. }
  294. VM86_FAULT_RETURN;
  295. case 0xcd: /* int */
  296. intno = vm_getb(env, csp, ip);
  297. ADD16(ip, 1);
  298. env->eip = ip;
  299. if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
  300. if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >>
  301. (intno &7)) & 1) {
  302. return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
  303. return;
  304. }
  305. }
  306. do_int(env, intno);
  307. break;
  308. case 0xcf: /* iret */
  309. if (data32) {
  310. newip = vm_getl(env, ssp, sp) & 0xffff;
  311. newcs = vm_getl(env, ssp, sp + 4) & 0xffff;
  312. newflags = vm_getl(env, ssp, sp + 8);
  313. ADD16(env->regs[R_ESP], 12);
  314. } else {
  315. newip = vm_getw(env, ssp, sp);
  316. newcs = vm_getw(env, ssp, sp + 2);
  317. newflags = vm_getw(env, ssp, sp + 4);
  318. ADD16(env->regs[R_ESP], 6);
  319. }
  320. env->eip = newip;
  321. cpu_x86_load_seg(env, R_CS, newcs);
  322. CHECK_IF_IN_TRAP();
  323. if (data32) {
  324. if (set_vflags_long(newflags, env))
  325. return;
  326. } else {
  327. if (set_vflags_short(newflags, env))
  328. return;
  329. }
  330. VM86_FAULT_RETURN;
  331. case 0xfa: /* cli */
  332. env->eip = ip;
  333. clear_IF(env);
  334. VM86_FAULT_RETURN;
  335. case 0xfb: /* sti */
  336. env->eip = ip;
  337. if (set_IF(env))
  338. return;
  339. VM86_FAULT_RETURN;
  340. default:
  341. /* real VM86 GPF exception */
  342. return_to_32bit(env, TARGET_VM86_UNKNOWN);
  343. break;
  344. }
  345. }
  346. int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
  347. {
  348. CPUState *cs = env_cpu(env);
  349. TaskState *ts = cs->opaque;
  350. struct target_vm86plus_struct * target_v86;
  351. int ret;
  352. switch (subfunction) {
  353. case TARGET_VM86_REQUEST_IRQ:
  354. case TARGET_VM86_FREE_IRQ:
  355. case TARGET_VM86_GET_IRQ_BITS:
  356. case TARGET_VM86_GET_AND_RESET_IRQ:
  357. qemu_log_mask(LOG_UNIMP, "qemu: unsupported vm86 subfunction (%ld)\n",
  358. subfunction);
  359. ret = -TARGET_EINVAL;
  360. goto out;
  361. case TARGET_VM86_PLUS_INSTALL_CHECK:
  362. /* NOTE: on old vm86 stuff this will return the error
  363. from verify_area(), because the subfunction is
  364. interpreted as (invalid) address to vm86_struct.
  365. So the installation check works.
  366. */
  367. ret = 0;
  368. goto out;
  369. }
  370. /* save current CPU regs */
  371. ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
  372. ts->vm86_saved_regs.ebx = env->regs[R_EBX];
  373. ts->vm86_saved_regs.ecx = env->regs[R_ECX];
  374. ts->vm86_saved_regs.edx = env->regs[R_EDX];
  375. ts->vm86_saved_regs.esi = env->regs[R_ESI];
  376. ts->vm86_saved_regs.edi = env->regs[R_EDI];
  377. ts->vm86_saved_regs.ebp = env->regs[R_EBP];
  378. ts->vm86_saved_regs.esp = env->regs[R_ESP];
  379. ts->vm86_saved_regs.eflags = env->eflags;
  380. ts->vm86_saved_regs.eip = env->eip;
  381. ts->vm86_saved_regs.cs = env->segs[R_CS].selector;
  382. ts->vm86_saved_regs.ss = env->segs[R_SS].selector;
  383. ts->vm86_saved_regs.ds = env->segs[R_DS].selector;
  384. ts->vm86_saved_regs.es = env->segs[R_ES].selector;
  385. ts->vm86_saved_regs.fs = env->segs[R_FS].selector;
  386. ts->vm86_saved_regs.gs = env->segs[R_GS].selector;
  387. ts->target_v86 = vm86_addr;
  388. if (!lock_user_struct(VERIFY_READ, target_v86, vm86_addr, 1))
  389. return -TARGET_EFAULT;
  390. /* build vm86 CPU state */
  391. ts->v86flags = tswap32(target_v86->regs.eflags);
  392. env->eflags = (env->eflags & ~SAFE_MASK) |
  393. (tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK;
  394. ts->vm86plus.cpu_type = tswapal(target_v86->cpu_type);
  395. switch (ts->vm86plus.cpu_type) {
  396. case TARGET_CPU_286:
  397. ts->v86mask = 0;
  398. break;
  399. case TARGET_CPU_386:
  400. ts->v86mask = NT_MASK | IOPL_MASK;
  401. break;
  402. case TARGET_CPU_486:
  403. ts->v86mask = AC_MASK | NT_MASK | IOPL_MASK;
  404. break;
  405. default:
  406. ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK;
  407. break;
  408. }
  409. env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
  410. env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
  411. env->regs[R_EDX] = tswap32(target_v86->regs.edx);
  412. env->regs[R_ESI] = tswap32(target_v86->regs.esi);
  413. env->regs[R_EDI] = tswap32(target_v86->regs.edi);
  414. env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
  415. env->regs[R_ESP] = tswap32(target_v86->regs.esp);
  416. env->eip = tswap32(target_v86->regs.eip);
  417. cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
  418. cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
  419. cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
  420. cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
  421. cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
  422. cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
  423. ret = tswap32(target_v86->regs.eax); /* eax will be restored at
  424. the end of the syscall */
  425. memcpy(&ts->vm86plus.int_revectored,
  426. &target_v86->int_revectored, 32);
  427. memcpy(&ts->vm86plus.int21_revectored,
  428. &target_v86->int21_revectored, 32);
  429. ts->vm86plus.vm86plus.flags = tswapal(target_v86->vm86plus.flags);
  430. memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab,
  431. target_v86->vm86plus.vm86dbg_intxxtab, 32);
  432. unlock_user_struct(target_v86, vm86_addr, 0);
  433. LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
  434. env->segs[R_CS].selector, env->eip);
  435. /* now the virtual CPU is ready for vm86 execution ! */
  436. out:
  437. return ret;
  438. }