virtio-gpu-virgl.c 20 KB

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  1. /*
  2. * Virtio GPU Device
  3. *
  4. * Copyright Red Hat, Inc. 2013-2014
  5. *
  6. * Authors:
  7. * Dave Airlie <airlied@redhat.com>
  8. * Gerd Hoffmann <kraxel@redhat.com>
  9. *
  10. * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11. * See the COPYING file in the top-level directory.
  12. */
  13. #include "qemu/osdep.h"
  14. #include "qemu/error-report.h"
  15. #include "qemu/iov.h"
  16. #include "trace.h"
  17. #include "hw/virtio/virtio.h"
  18. #include "hw/virtio/virtio-gpu.h"
  19. #include <virglrenderer.h>
  20. static struct virgl_renderer_callbacks virtio_gpu_3d_cbs;
  21. static void virgl_cmd_create_resource_2d(VirtIOGPU *g,
  22. struct virtio_gpu_ctrl_command *cmd)
  23. {
  24. struct virtio_gpu_resource_create_2d c2d;
  25. struct virgl_renderer_resource_create_args args;
  26. VIRTIO_GPU_FILL_CMD(c2d);
  27. trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
  28. c2d.width, c2d.height);
  29. args.handle = c2d.resource_id;
  30. args.target = 2;
  31. args.format = c2d.format;
  32. args.bind = (1 << 1);
  33. args.width = c2d.width;
  34. args.height = c2d.height;
  35. args.depth = 1;
  36. args.array_size = 1;
  37. args.last_level = 0;
  38. args.nr_samples = 0;
  39. args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
  40. virgl_renderer_resource_create(&args, NULL, 0);
  41. }
  42. static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
  43. struct virtio_gpu_ctrl_command *cmd)
  44. {
  45. struct virtio_gpu_resource_create_3d c3d;
  46. struct virgl_renderer_resource_create_args args;
  47. VIRTIO_GPU_FILL_CMD(c3d);
  48. trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format,
  49. c3d.width, c3d.height, c3d.depth);
  50. args.handle = c3d.resource_id;
  51. args.target = c3d.target;
  52. args.format = c3d.format;
  53. args.bind = c3d.bind;
  54. args.width = c3d.width;
  55. args.height = c3d.height;
  56. args.depth = c3d.depth;
  57. args.array_size = c3d.array_size;
  58. args.last_level = c3d.last_level;
  59. args.nr_samples = c3d.nr_samples;
  60. args.flags = c3d.flags;
  61. virgl_renderer_resource_create(&args, NULL, 0);
  62. }
  63. static void virgl_cmd_resource_unref(VirtIOGPU *g,
  64. struct virtio_gpu_ctrl_command *cmd)
  65. {
  66. struct virtio_gpu_resource_unref unref;
  67. struct iovec *res_iovs = NULL;
  68. int num_iovs = 0;
  69. VIRTIO_GPU_FILL_CMD(unref);
  70. trace_virtio_gpu_cmd_res_unref(unref.resource_id);
  71. virgl_renderer_resource_detach_iov(unref.resource_id,
  72. &res_iovs,
  73. &num_iovs);
  74. if (res_iovs != NULL && num_iovs != 0) {
  75. virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs);
  76. }
  77. virgl_renderer_resource_unref(unref.resource_id);
  78. }
  79. static void virgl_cmd_context_create(VirtIOGPU *g,
  80. struct virtio_gpu_ctrl_command *cmd)
  81. {
  82. struct virtio_gpu_ctx_create cc;
  83. VIRTIO_GPU_FILL_CMD(cc);
  84. trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id,
  85. cc.debug_name);
  86. virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
  87. cc.debug_name);
  88. }
  89. static void virgl_cmd_context_destroy(VirtIOGPU *g,
  90. struct virtio_gpu_ctrl_command *cmd)
  91. {
  92. struct virtio_gpu_ctx_destroy cd;
  93. VIRTIO_GPU_FILL_CMD(cd);
  94. trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id);
  95. virgl_renderer_context_destroy(cd.hdr.ctx_id);
  96. }
  97. static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y,
  98. int width, int height)
  99. {
  100. if (!g->parent_obj.scanout[idx].con) {
  101. return;
  102. }
  103. dpy_gl_update(g->parent_obj.scanout[idx].con, x, y, width, height);
  104. }
  105. static void virgl_cmd_resource_flush(VirtIOGPU *g,
  106. struct virtio_gpu_ctrl_command *cmd)
  107. {
  108. struct virtio_gpu_resource_flush rf;
  109. int i;
  110. VIRTIO_GPU_FILL_CMD(rf);
  111. trace_virtio_gpu_cmd_res_flush(rf.resource_id,
  112. rf.r.width, rf.r.height, rf.r.x, rf.r.y);
  113. for (i = 0; i < g->parent_obj.conf.max_outputs; i++) {
  114. if (g->parent_obj.scanout[i].resource_id != rf.resource_id) {
  115. continue;
  116. }
  117. virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height);
  118. }
  119. }
  120. static GLuint virgl_borrow_texture_for_scanout(uint32_t id, bool *y_0_top,
  121. uint32_t *width,
  122. uint32_t *height)
  123. {
  124. struct virgl_renderer_texture_info info;
  125. int ret;
  126. memset(&info, 0, sizeof(info));
  127. ret = virgl_renderer_borrow_texture_for_scanout(id, &info);
  128. if (ret == -1) {
  129. return 0;
  130. }
  131. if (y_0_top) {
  132. *y_0_top = info.flags & VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
  133. }
  134. if (width) {
  135. *width = info.width;
  136. }
  137. if (height) {
  138. *height = info.height;
  139. }
  140. return info.tex_id;
  141. }
  142. static void virgl_cmd_set_scanout(VirtIOGPU *g,
  143. struct virtio_gpu_ctrl_command *cmd)
  144. {
  145. struct virtio_gpu_set_scanout ss;
  146. VIRTIO_GPU_FILL_CMD(ss);
  147. trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
  148. ss.r.width, ss.r.height, ss.r.x, ss.r.y);
  149. if (ss.scanout_id >= g->parent_obj.conf.max_outputs) {
  150. qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
  151. __func__, ss.scanout_id);
  152. cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
  153. return;
  154. }
  155. g->parent_obj.enable = 1;
  156. if (ss.resource_id && ss.r.width && ss.r.height) {
  157. qemu_console_resize(g->parent_obj.scanout[ss.scanout_id].con,
  158. ss.r.width, ss.r.height);
  159. virgl_renderer_force_ctx_0();
  160. dpy_gl_scanout_texture(
  161. g->parent_obj.scanout[ss.scanout_id].con, ss.resource_id,
  162. virgl_borrow_texture_for_scanout,
  163. ss.r.x, ss.r.y, ss.r.width, ss.r.height);
  164. } else {
  165. dpy_gfx_replace_surface(
  166. g->parent_obj.scanout[ss.scanout_id].con, NULL);
  167. dpy_gl_scanout_disable(g->parent_obj.scanout[ss.scanout_id].con);
  168. }
  169. g->parent_obj.scanout[ss.scanout_id].resource_id = ss.resource_id;
  170. }
  171. static void virgl_cmd_submit_3d(VirtIOGPU *g,
  172. struct virtio_gpu_ctrl_command *cmd)
  173. {
  174. struct virtio_gpu_cmd_submit cs;
  175. void *buf;
  176. size_t s;
  177. VIRTIO_GPU_FILL_CMD(cs);
  178. trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size);
  179. buf = g_malloc(cs.size);
  180. s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
  181. sizeof(cs), buf, cs.size);
  182. if (s != cs.size) {
  183. qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)",
  184. __func__, s, cs.size);
  185. cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
  186. goto out;
  187. }
  188. if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
  189. g->stats.req_3d++;
  190. g->stats.bytes_3d += cs.size;
  191. }
  192. virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
  193. out:
  194. g_free(buf);
  195. }
  196. static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g,
  197. struct virtio_gpu_ctrl_command *cmd)
  198. {
  199. struct virtio_gpu_transfer_to_host_2d t2d;
  200. struct virtio_gpu_box box;
  201. VIRTIO_GPU_FILL_CMD(t2d);
  202. trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);
  203. box.x = t2d.r.x;
  204. box.y = t2d.r.y;
  205. box.z = 0;
  206. box.w = t2d.r.width;
  207. box.h = t2d.r.height;
  208. box.d = 1;
  209. virgl_renderer_transfer_write_iov(t2d.resource_id,
  210. 0,
  211. 0,
  212. 0,
  213. 0,
  214. (struct virgl_box *)&box,
  215. t2d.offset, NULL, 0);
  216. }
  217. static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g,
  218. struct virtio_gpu_ctrl_command *cmd)
  219. {
  220. struct virtio_gpu_transfer_host_3d t3d;
  221. VIRTIO_GPU_FILL_CMD(t3d);
  222. trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id);
  223. virgl_renderer_transfer_write_iov(t3d.resource_id,
  224. t3d.hdr.ctx_id,
  225. t3d.level,
  226. t3d.stride,
  227. t3d.layer_stride,
  228. (struct virgl_box *)&t3d.box,
  229. t3d.offset, NULL, 0);
  230. }
  231. static void
  232. virgl_cmd_transfer_from_host_3d(VirtIOGPU *g,
  233. struct virtio_gpu_ctrl_command *cmd)
  234. {
  235. struct virtio_gpu_transfer_host_3d tf3d;
  236. VIRTIO_GPU_FILL_CMD(tf3d);
  237. trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id);
  238. virgl_renderer_transfer_read_iov(tf3d.resource_id,
  239. tf3d.hdr.ctx_id,
  240. tf3d.level,
  241. tf3d.stride,
  242. tf3d.layer_stride,
  243. (struct virgl_box *)&tf3d.box,
  244. tf3d.offset, NULL, 0);
  245. }
  246. static void virgl_resource_attach_backing(VirtIOGPU *g,
  247. struct virtio_gpu_ctrl_command *cmd)
  248. {
  249. struct virtio_gpu_resource_attach_backing att_rb;
  250. struct iovec *res_iovs;
  251. uint32_t res_niov;
  252. int ret;
  253. VIRTIO_GPU_FILL_CMD(att_rb);
  254. trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);
  255. ret = virtio_gpu_create_mapping_iov(g, att_rb.nr_entries, sizeof(att_rb),
  256. cmd, NULL, &res_iovs, &res_niov);
  257. if (ret != 0) {
  258. cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
  259. return;
  260. }
  261. ret = virgl_renderer_resource_attach_iov(att_rb.resource_id,
  262. res_iovs, res_niov);
  263. if (ret != 0)
  264. virtio_gpu_cleanup_mapping_iov(g, res_iovs, res_niov);
  265. }
  266. static void virgl_resource_detach_backing(VirtIOGPU *g,
  267. struct virtio_gpu_ctrl_command *cmd)
  268. {
  269. struct virtio_gpu_resource_detach_backing detach_rb;
  270. struct iovec *res_iovs = NULL;
  271. int num_iovs = 0;
  272. VIRTIO_GPU_FILL_CMD(detach_rb);
  273. trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id);
  274. virgl_renderer_resource_detach_iov(detach_rb.resource_id,
  275. &res_iovs,
  276. &num_iovs);
  277. if (res_iovs == NULL || num_iovs == 0) {
  278. return;
  279. }
  280. virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs);
  281. }
  282. static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g,
  283. struct virtio_gpu_ctrl_command *cmd)
  284. {
  285. struct virtio_gpu_ctx_resource att_res;
  286. VIRTIO_GPU_FILL_CMD(att_res);
  287. trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id,
  288. att_res.resource_id);
  289. virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
  290. }
  291. static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g,
  292. struct virtio_gpu_ctrl_command *cmd)
  293. {
  294. struct virtio_gpu_ctx_resource det_res;
  295. VIRTIO_GPU_FILL_CMD(det_res);
  296. trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id,
  297. det_res.resource_id);
  298. virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
  299. }
  300. static void virgl_cmd_get_capset_info(VirtIOGPU *g,
  301. struct virtio_gpu_ctrl_command *cmd)
  302. {
  303. struct virtio_gpu_get_capset_info info;
  304. struct virtio_gpu_resp_capset_info resp;
  305. VIRTIO_GPU_FILL_CMD(info);
  306. memset(&resp, 0, sizeof(resp));
  307. if (info.capset_index == 0) {
  308. resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
  309. virgl_renderer_get_cap_set(resp.capset_id,
  310. &resp.capset_max_version,
  311. &resp.capset_max_size);
  312. } else if (info.capset_index == 1) {
  313. resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2;
  314. virgl_renderer_get_cap_set(resp.capset_id,
  315. &resp.capset_max_version,
  316. &resp.capset_max_size);
  317. } else {
  318. resp.capset_max_version = 0;
  319. resp.capset_max_size = 0;
  320. }
  321. resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
  322. virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
  323. }
  324. static void virgl_cmd_get_capset(VirtIOGPU *g,
  325. struct virtio_gpu_ctrl_command *cmd)
  326. {
  327. struct virtio_gpu_get_capset gc;
  328. struct virtio_gpu_resp_capset *resp;
  329. uint32_t max_ver, max_size;
  330. VIRTIO_GPU_FILL_CMD(gc);
  331. virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
  332. &max_size);
  333. if (!max_size) {
  334. cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
  335. return;
  336. }
  337. resp = g_malloc0(sizeof(*resp) + max_size);
  338. resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
  339. virgl_renderer_fill_caps(gc.capset_id,
  340. gc.capset_version,
  341. (void *)resp->capset_data);
  342. virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
  343. g_free(resp);
  344. }
  345. void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
  346. struct virtio_gpu_ctrl_command *cmd)
  347. {
  348. VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);
  349. virgl_renderer_force_ctx_0();
  350. switch (cmd->cmd_hdr.type) {
  351. case VIRTIO_GPU_CMD_CTX_CREATE:
  352. virgl_cmd_context_create(g, cmd);
  353. break;
  354. case VIRTIO_GPU_CMD_CTX_DESTROY:
  355. virgl_cmd_context_destroy(g, cmd);
  356. break;
  357. case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
  358. virgl_cmd_create_resource_2d(g, cmd);
  359. break;
  360. case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
  361. virgl_cmd_create_resource_3d(g, cmd);
  362. break;
  363. case VIRTIO_GPU_CMD_SUBMIT_3D:
  364. virgl_cmd_submit_3d(g, cmd);
  365. break;
  366. case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
  367. virgl_cmd_transfer_to_host_2d(g, cmd);
  368. break;
  369. case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
  370. virgl_cmd_transfer_to_host_3d(g, cmd);
  371. break;
  372. case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
  373. virgl_cmd_transfer_from_host_3d(g, cmd);
  374. break;
  375. case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
  376. virgl_resource_attach_backing(g, cmd);
  377. break;
  378. case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
  379. virgl_resource_detach_backing(g, cmd);
  380. break;
  381. case VIRTIO_GPU_CMD_SET_SCANOUT:
  382. virgl_cmd_set_scanout(g, cmd);
  383. break;
  384. case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
  385. virgl_cmd_resource_flush(g, cmd);
  386. break;
  387. case VIRTIO_GPU_CMD_RESOURCE_UNREF:
  388. virgl_cmd_resource_unref(g, cmd);
  389. break;
  390. case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
  391. /* TODO add security */
  392. virgl_cmd_ctx_attach_resource(g, cmd);
  393. break;
  394. case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
  395. /* TODO add security */
  396. virgl_cmd_ctx_detach_resource(g, cmd);
  397. break;
  398. case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
  399. virgl_cmd_get_capset_info(g, cmd);
  400. break;
  401. case VIRTIO_GPU_CMD_GET_CAPSET:
  402. virgl_cmd_get_capset(g, cmd);
  403. break;
  404. case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
  405. virtio_gpu_get_display_info(g, cmd);
  406. break;
  407. case VIRTIO_GPU_CMD_GET_EDID:
  408. virtio_gpu_get_edid(g, cmd);
  409. break;
  410. default:
  411. cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
  412. break;
  413. }
  414. if (cmd->finished) {
  415. return;
  416. }
  417. if (cmd->error) {
  418. fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__,
  419. cmd->cmd_hdr.type, cmd->error);
  420. virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error);
  421. return;
  422. }
  423. if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
  424. virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
  425. return;
  426. }
  427. trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
  428. virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
  429. }
  430. static void virgl_write_fence(void *opaque, uint32_t fence)
  431. {
  432. VirtIOGPU *g = opaque;
  433. struct virtio_gpu_ctrl_command *cmd, *tmp;
  434. QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
  435. /*
  436. * the guest can end up emitting fences out of order
  437. * so we should check all fenced cmds not just the first one.
  438. */
  439. if (cmd->cmd_hdr.fence_id > fence) {
  440. continue;
  441. }
  442. trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id);
  443. virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
  444. QTAILQ_REMOVE(&g->fenceq, cmd, next);
  445. g_free(cmd);
  446. g->inflight--;
  447. if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
  448. fprintf(stderr, "inflight: %3d (-)\r", g->inflight);
  449. }
  450. }
  451. }
  452. static virgl_renderer_gl_context
  453. virgl_create_context(void *opaque, int scanout_idx,
  454. struct virgl_renderer_gl_ctx_param *params)
  455. {
  456. VirtIOGPU *g = opaque;
  457. QEMUGLContext ctx;
  458. QEMUGLParams qparams;
  459. qparams.major_ver = params->major_ver;
  460. qparams.minor_ver = params->minor_ver;
  461. ctx = dpy_gl_ctx_create(g->parent_obj.scanout[scanout_idx].con, &qparams);
  462. return (virgl_renderer_gl_context)ctx;
  463. }
  464. static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx)
  465. {
  466. VirtIOGPU *g = opaque;
  467. QEMUGLContext qctx = (QEMUGLContext)ctx;
  468. dpy_gl_ctx_destroy(g->parent_obj.scanout[0].con, qctx);
  469. }
  470. static int virgl_make_context_current(void *opaque, int scanout_idx,
  471. virgl_renderer_gl_context ctx)
  472. {
  473. VirtIOGPU *g = opaque;
  474. QEMUGLContext qctx = (QEMUGLContext)ctx;
  475. return dpy_gl_ctx_make_current(g->parent_obj.scanout[scanout_idx].con,
  476. qctx);
  477. }
  478. static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = {
  479. .version = 1,
  480. .write_fence = virgl_write_fence,
  481. .create_gl_context = virgl_create_context,
  482. .destroy_gl_context = virgl_destroy_context,
  483. .make_current = virgl_make_context_current,
  484. };
  485. static void virtio_gpu_print_stats(void *opaque)
  486. {
  487. VirtIOGPU *g = opaque;
  488. if (g->stats.requests) {
  489. fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n",
  490. g->stats.requests,
  491. g->stats.max_inflight,
  492. g->stats.req_3d,
  493. g->stats.bytes_3d);
  494. g->stats.requests = 0;
  495. g->stats.max_inflight = 0;
  496. g->stats.req_3d = 0;
  497. g->stats.bytes_3d = 0;
  498. } else {
  499. fprintf(stderr, "stats: idle\r");
  500. }
  501. timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
  502. }
  503. static void virtio_gpu_fence_poll(void *opaque)
  504. {
  505. VirtIOGPU *g = opaque;
  506. virgl_renderer_poll();
  507. virtio_gpu_process_cmdq(g);
  508. if (!QTAILQ_EMPTY(&g->cmdq) || !QTAILQ_EMPTY(&g->fenceq)) {
  509. timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10);
  510. }
  511. }
  512. void virtio_gpu_virgl_fence_poll(VirtIOGPU *g)
  513. {
  514. virtio_gpu_fence_poll(g);
  515. }
  516. void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g)
  517. {
  518. int i;
  519. for (i = 0; i < g->parent_obj.conf.max_outputs; i++) {
  520. dpy_gfx_replace_surface(g->parent_obj.scanout[i].con, NULL);
  521. dpy_gl_scanout_disable(g->parent_obj.scanout[i].con);
  522. }
  523. }
  524. void virtio_gpu_virgl_reset(VirtIOGPU *g)
  525. {
  526. virgl_renderer_reset();
  527. }
  528. int virtio_gpu_virgl_init(VirtIOGPU *g)
  529. {
  530. int ret;
  531. ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs);
  532. if (ret != 0) {
  533. error_report("virgl could not be initialized: %d", ret);
  534. return ret;
  535. }
  536. g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL,
  537. virtio_gpu_fence_poll, g);
  538. if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
  539. g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL,
  540. virtio_gpu_print_stats, g);
  541. timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
  542. }
  543. return 0;
  544. }
  545. int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g)
  546. {
  547. uint32_t capset2_max_ver, capset2_max_size;
  548. virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2,
  549. &capset2_max_ver,
  550. &capset2_max_size);
  551. return capset2_max_ver ? 2 : 1;
  552. }