npcm7xx_timer.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717
  1. /*
  2. * Nuvoton NPCM7xx Timer Controller
  3. *
  4. * Copyright 2020 Google LLC
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14. * for more details.
  15. */
  16. #include "qemu/osdep.h"
  17. #include "hw/irq.h"
  18. #include "hw/qdev-clock.h"
  19. #include "hw/qdev-properties.h"
  20. #include "hw/timer/npcm7xx_timer.h"
  21. #include "migration/vmstate.h"
  22. #include "qemu/bitops.h"
  23. #include "qemu/error-report.h"
  24. #include "qemu/log.h"
  25. #include "qemu/module.h"
  26. #include "qemu/timer.h"
  27. #include "qemu/units.h"
  28. #include "trace.h"
  29. /* 32-bit register indices. */
  30. enum NPCM7xxTimerRegisters {
  31. NPCM7XX_TIMER_TCSR0,
  32. NPCM7XX_TIMER_TCSR1,
  33. NPCM7XX_TIMER_TICR0,
  34. NPCM7XX_TIMER_TICR1,
  35. NPCM7XX_TIMER_TDR0,
  36. NPCM7XX_TIMER_TDR1,
  37. NPCM7XX_TIMER_TISR,
  38. NPCM7XX_TIMER_WTCR,
  39. NPCM7XX_TIMER_TCSR2,
  40. NPCM7XX_TIMER_TCSR3,
  41. NPCM7XX_TIMER_TICR2,
  42. NPCM7XX_TIMER_TICR3,
  43. NPCM7XX_TIMER_TDR2,
  44. NPCM7XX_TIMER_TDR3,
  45. NPCM7XX_TIMER_TCSR4 = 0x0040 / sizeof(uint32_t),
  46. NPCM7XX_TIMER_TICR4 = 0x0048 / sizeof(uint32_t),
  47. NPCM7XX_TIMER_TDR4 = 0x0050 / sizeof(uint32_t),
  48. NPCM7XX_TIMER_REGS_END,
  49. };
  50. /* Register field definitions. */
  51. #define NPCM7XX_TCSR_CEN BIT(30)
  52. #define NPCM7XX_TCSR_IE BIT(29)
  53. #define NPCM7XX_TCSR_PERIODIC BIT(27)
  54. #define NPCM7XX_TCSR_CRST BIT(26)
  55. #define NPCM7XX_TCSR_CACT BIT(25)
  56. #define NPCM7XX_TCSR_RSVD 0x01ffff00
  57. #define NPCM7XX_TCSR_PRESCALE_START 0
  58. #define NPCM7XX_TCSR_PRESCALE_LEN 8
  59. #define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2)
  60. #define NPCM7XX_WTCR_FREEZE_EN BIT(9)
  61. #define NPCM7XX_WTCR_WTE BIT(7)
  62. #define NPCM7XX_WTCR_WTIE BIT(6)
  63. #define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2)
  64. #define NPCM7XX_WTCR_WTIF BIT(3)
  65. #define NPCM7XX_WTCR_WTRF BIT(2)
  66. #define NPCM7XX_WTCR_WTRE BIT(1)
  67. #define NPCM7XX_WTCR_WTR BIT(0)
  68. /*
  69. * The number of clock cycles between interrupt and reset in watchdog, used
  70. * by the software to handle the interrupt before system is reset.
  71. */
  72. #define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024
  73. /* Start or resume the timer. */
  74. static void npcm7xx_timer_start(NPCM7xxBaseTimer *t)
  75. {
  76. int64_t now;
  77. now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  78. t->expires_ns = now + t->remaining_ns;
  79. timer_mod(&t->qtimer, t->expires_ns);
  80. }
  81. /* Stop counting. Record the time remaining so we can continue later. */
  82. static void npcm7xx_timer_pause(NPCM7xxBaseTimer *t)
  83. {
  84. int64_t now;
  85. timer_del(&t->qtimer);
  86. now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  87. t->remaining_ns = t->expires_ns - now;
  88. }
  89. /* Delete the timer and reset it to default state. */
  90. static void npcm7xx_timer_clear(NPCM7xxBaseTimer *t)
  91. {
  92. timer_del(&t->qtimer);
  93. t->expires_ns = 0;
  94. t->remaining_ns = 0;
  95. }
  96. /*
  97. * Returns the index of timer in the tc->timer array. This can be used to
  98. * locate the registers that belong to this timer.
  99. */
  100. static int npcm7xx_timer_index(NPCM7xxTimerCtrlState *tc, NPCM7xxTimer *timer)
  101. {
  102. int index = timer - tc->timer;
  103. g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL);
  104. return index;
  105. }
  106. /* Return the value by which to divide the reference clock rate. */
  107. static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
  108. {
  109. return extract32(tcsr, NPCM7XX_TCSR_PRESCALE_START,
  110. NPCM7XX_TCSR_PRESCALE_LEN) + 1;
  111. }
  112. /* Convert a timer cycle count to a time interval in nanoseconds. */
  113. static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
  114. {
  115. int64_t ticks = count;
  116. ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
  117. return clock_ticks_to_ns(t->ctrl->clock, ticks);
  118. }
  119. /* Convert a time interval in nanoseconds to a timer cycle count. */
  120. static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
  121. {
  122. if (ns < 0) {
  123. return 0;
  124. }
  125. return clock_ns_to_ticks(t->ctrl->clock, ns) /
  126. npcm7xx_tcsr_prescaler(t->tcsr);
  127. }
  128. static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
  129. {
  130. switch (NPCM7XX_WTCR_WTCLK(t->wtcr)) {
  131. case 0:
  132. return 1;
  133. case 1:
  134. return 256;
  135. case 2:
  136. return 2048;
  137. case 3:
  138. return 65536;
  139. default:
  140. g_assert_not_reached();
  141. }
  142. }
  143. static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
  144. int64_t cycles)
  145. {
  146. int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
  147. int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
  148. /*
  149. * The reset function always clears the current timer. The caller of the
  150. * this needs to decide whether to start the watchdog timer based on
  151. * specific flag in WTCR.
  152. */
  153. npcm7xx_timer_clear(&t->base_timer);
  154. t->base_timer.remaining_ns = ns;
  155. }
  156. static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer *t)
  157. {
  158. int64_t cycles = 1;
  159. uint32_t s = NPCM7XX_WTCR_WTIS(t->wtcr);
  160. g_assert(s <= 3);
  161. cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT;
  162. cycles <<= 2 * s;
  163. npcm7xx_watchdog_timer_reset_cycles(t, cycles);
  164. }
  165. /*
  166. * Raise the interrupt line if there's a pending interrupt and interrupts are
  167. * enabled for this timer. If not, lower it.
  168. */
  169. static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
  170. {
  171. NPCM7xxTimerCtrlState *tc = t->ctrl;
  172. int index = npcm7xx_timer_index(tc, t);
  173. bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index));
  174. qemu_set_irq(t->irq, pending);
  175. trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
  176. }
  177. /*
  178. * Called when the counter reaches zero. Sets the interrupt flag, and either
  179. * restarts or disables the timer.
  180. */
  181. static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
  182. {
  183. NPCM7xxTimerCtrlState *tc = t->ctrl;
  184. int index = npcm7xx_timer_index(tc, t);
  185. tc->tisr |= BIT(index);
  186. if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
  187. t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
  188. if (t->tcsr & NPCM7XX_TCSR_CEN) {
  189. npcm7xx_timer_start(&t->base_timer);
  190. }
  191. } else {
  192. t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
  193. }
  194. npcm7xx_timer_check_interrupt(t);
  195. }
  196. /*
  197. * Restart the timer from its initial value. If the timer was enabled and stays
  198. * enabled, adjust the QEMU timer according to the new count. If the timer is
  199. * transitioning from disabled to enabled, the caller is expected to start the
  200. * timer later.
  201. */
  202. static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
  203. {
  204. t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
  205. if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
  206. npcm7xx_timer_start(&t->base_timer);
  207. }
  208. }
  209. /* Register read and write handlers */
  210. static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
  211. {
  212. if (t->tcsr & NPCM7XX_TCSR_CEN) {
  213. int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  214. return npcm7xx_timer_ns_to_count(t, t->base_timer.expires_ns - now);
  215. }
  216. return npcm7xx_timer_ns_to_count(t, t->base_timer.remaining_ns);
  217. }
  218. static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
  219. {
  220. uint32_t old_tcsr = t->tcsr;
  221. uint32_t tdr;
  222. if (new_tcsr & NPCM7XX_TCSR_RSVD) {
  223. qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits in 0x%08x ignored\n",
  224. __func__, new_tcsr);
  225. new_tcsr &= ~NPCM7XX_TCSR_RSVD;
  226. }
  227. if (new_tcsr & NPCM7XX_TCSR_CACT) {
  228. qemu_log_mask(LOG_GUEST_ERROR, "%s: read-only bits in 0x%08x ignored\n",
  229. __func__, new_tcsr);
  230. new_tcsr &= ~NPCM7XX_TCSR_CACT;
  231. }
  232. if ((new_tcsr & NPCM7XX_TCSR_CRST) && (new_tcsr & NPCM7XX_TCSR_CEN)) {
  233. qemu_log_mask(LOG_GUEST_ERROR,
  234. "%s: both CRST and CEN set; ignoring CEN.\n",
  235. __func__);
  236. new_tcsr &= ~NPCM7XX_TCSR_CEN;
  237. }
  238. /* Calculate the value of TDR before potentially changing the prescaler. */
  239. tdr = npcm7xx_timer_read_tdr(t);
  240. t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr;
  241. if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
  242. /* Recalculate time remaining based on the current TDR value. */
  243. t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
  244. if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
  245. npcm7xx_timer_start(&t->base_timer);
  246. }
  247. }
  248. if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) {
  249. npcm7xx_timer_check_interrupt(t);
  250. }
  251. if (new_tcsr & NPCM7XX_TCSR_CRST) {
  252. npcm7xx_timer_restart(t, old_tcsr);
  253. t->tcsr &= ~NPCM7XX_TCSR_CRST;
  254. }
  255. if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
  256. if (new_tcsr & NPCM7XX_TCSR_CEN) {
  257. t->tcsr |= NPCM7XX_TCSR_CACT;
  258. npcm7xx_timer_start(&t->base_timer);
  259. } else {
  260. t->tcsr &= ~NPCM7XX_TCSR_CACT;
  261. npcm7xx_timer_pause(&t->base_timer);
  262. if (t->base_timer.remaining_ns <= 0) {
  263. npcm7xx_timer_reached_zero(t);
  264. }
  265. }
  266. }
  267. }
  268. static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr)
  269. {
  270. t->ticr = new_ticr;
  271. npcm7xx_timer_restart(t, t->tcsr);
  272. }
  273. static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value)
  274. {
  275. int i;
  276. s->tisr &= ~value;
  277. for (i = 0; i < ARRAY_SIZE(s->timer); i++) {
  278. if (value & (1U << i)) {
  279. npcm7xx_timer_check_interrupt(&s->timer[i]);
  280. }
  281. }
  282. }
  283. static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer *t, uint32_t new_wtcr)
  284. {
  285. uint32_t old_wtcr = t->wtcr;
  286. /*
  287. * WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits
  288. * unchanged.
  289. */
  290. if (new_wtcr & NPCM7XX_WTCR_WTIF) {
  291. new_wtcr &= ~NPCM7XX_WTCR_WTIF;
  292. } else if (old_wtcr & NPCM7XX_WTCR_WTIF) {
  293. new_wtcr |= NPCM7XX_WTCR_WTIF;
  294. }
  295. if (new_wtcr & NPCM7XX_WTCR_WTRF) {
  296. new_wtcr &= ~NPCM7XX_WTCR_WTRF;
  297. } else if (old_wtcr & NPCM7XX_WTCR_WTRF) {
  298. new_wtcr |= NPCM7XX_WTCR_WTRF;
  299. }
  300. t->wtcr = new_wtcr;
  301. if (new_wtcr & NPCM7XX_WTCR_WTR) {
  302. t->wtcr &= ~NPCM7XX_WTCR_WTR;
  303. npcm7xx_watchdog_timer_reset(t);
  304. if (new_wtcr & NPCM7XX_WTCR_WTE) {
  305. npcm7xx_timer_start(&t->base_timer);
  306. }
  307. } else if ((old_wtcr ^ new_wtcr) & NPCM7XX_WTCR_WTE) {
  308. if (new_wtcr & NPCM7XX_WTCR_WTE) {
  309. npcm7xx_timer_start(&t->base_timer);
  310. } else {
  311. npcm7xx_timer_pause(&t->base_timer);
  312. }
  313. }
  314. }
  315. static hwaddr npcm7xx_tcsr_index(hwaddr reg)
  316. {
  317. switch (reg) {
  318. case NPCM7XX_TIMER_TCSR0:
  319. return 0;
  320. case NPCM7XX_TIMER_TCSR1:
  321. return 1;
  322. case NPCM7XX_TIMER_TCSR2:
  323. return 2;
  324. case NPCM7XX_TIMER_TCSR3:
  325. return 3;
  326. case NPCM7XX_TIMER_TCSR4:
  327. return 4;
  328. default:
  329. g_assert_not_reached();
  330. }
  331. }
  332. static hwaddr npcm7xx_ticr_index(hwaddr reg)
  333. {
  334. switch (reg) {
  335. case NPCM7XX_TIMER_TICR0:
  336. return 0;
  337. case NPCM7XX_TIMER_TICR1:
  338. return 1;
  339. case NPCM7XX_TIMER_TICR2:
  340. return 2;
  341. case NPCM7XX_TIMER_TICR3:
  342. return 3;
  343. case NPCM7XX_TIMER_TICR4:
  344. return 4;
  345. default:
  346. g_assert_not_reached();
  347. }
  348. }
  349. static hwaddr npcm7xx_tdr_index(hwaddr reg)
  350. {
  351. switch (reg) {
  352. case NPCM7XX_TIMER_TDR0:
  353. return 0;
  354. case NPCM7XX_TIMER_TDR1:
  355. return 1;
  356. case NPCM7XX_TIMER_TDR2:
  357. return 2;
  358. case NPCM7XX_TIMER_TDR3:
  359. return 3;
  360. case NPCM7XX_TIMER_TDR4:
  361. return 4;
  362. default:
  363. g_assert_not_reached();
  364. }
  365. }
  366. static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size)
  367. {
  368. NPCM7xxTimerCtrlState *s = opaque;
  369. uint64_t value = 0;
  370. hwaddr reg;
  371. reg = offset / sizeof(uint32_t);
  372. switch (reg) {
  373. case NPCM7XX_TIMER_TCSR0:
  374. case NPCM7XX_TIMER_TCSR1:
  375. case NPCM7XX_TIMER_TCSR2:
  376. case NPCM7XX_TIMER_TCSR3:
  377. case NPCM7XX_TIMER_TCSR4:
  378. value = s->timer[npcm7xx_tcsr_index(reg)].tcsr;
  379. break;
  380. case NPCM7XX_TIMER_TICR0:
  381. case NPCM7XX_TIMER_TICR1:
  382. case NPCM7XX_TIMER_TICR2:
  383. case NPCM7XX_TIMER_TICR3:
  384. case NPCM7XX_TIMER_TICR4:
  385. value = s->timer[npcm7xx_ticr_index(reg)].ticr;
  386. break;
  387. case NPCM7XX_TIMER_TDR0:
  388. case NPCM7XX_TIMER_TDR1:
  389. case NPCM7XX_TIMER_TDR2:
  390. case NPCM7XX_TIMER_TDR3:
  391. case NPCM7XX_TIMER_TDR4:
  392. value = npcm7xx_timer_read_tdr(&s->timer[npcm7xx_tdr_index(reg)]);
  393. break;
  394. case NPCM7XX_TIMER_TISR:
  395. value = s->tisr;
  396. break;
  397. case NPCM7XX_TIMER_WTCR:
  398. value = s->watchdog_timer.wtcr;
  399. break;
  400. default:
  401. qemu_log_mask(LOG_GUEST_ERROR,
  402. "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
  403. __func__, offset);
  404. break;
  405. }
  406. trace_npcm7xx_timer_read(DEVICE(s)->canonical_path, offset, value);
  407. return value;
  408. }
  409. static void npcm7xx_timer_write(void *opaque, hwaddr offset,
  410. uint64_t v, unsigned size)
  411. {
  412. uint32_t reg = offset / sizeof(uint32_t);
  413. NPCM7xxTimerCtrlState *s = opaque;
  414. uint32_t value = v;
  415. trace_npcm7xx_timer_write(DEVICE(s)->canonical_path, offset, value);
  416. switch (reg) {
  417. case NPCM7XX_TIMER_TCSR0:
  418. case NPCM7XX_TIMER_TCSR1:
  419. case NPCM7XX_TIMER_TCSR2:
  420. case NPCM7XX_TIMER_TCSR3:
  421. case NPCM7XX_TIMER_TCSR4:
  422. npcm7xx_timer_write_tcsr(&s->timer[npcm7xx_tcsr_index(reg)], value);
  423. return;
  424. case NPCM7XX_TIMER_TICR0:
  425. case NPCM7XX_TIMER_TICR1:
  426. case NPCM7XX_TIMER_TICR2:
  427. case NPCM7XX_TIMER_TICR3:
  428. case NPCM7XX_TIMER_TICR4:
  429. npcm7xx_timer_write_ticr(&s->timer[npcm7xx_ticr_index(reg)], value);
  430. return;
  431. case NPCM7XX_TIMER_TDR0:
  432. case NPCM7XX_TIMER_TDR1:
  433. case NPCM7XX_TIMER_TDR2:
  434. case NPCM7XX_TIMER_TDR3:
  435. case NPCM7XX_TIMER_TDR4:
  436. qemu_log_mask(LOG_GUEST_ERROR,
  437. "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
  438. __func__, offset);
  439. return;
  440. case NPCM7XX_TIMER_TISR:
  441. npcm7xx_timer_write_tisr(s, value);
  442. return;
  443. case NPCM7XX_TIMER_WTCR:
  444. npcm7xx_timer_write_wtcr(&s->watchdog_timer, value);
  445. return;
  446. }
  447. qemu_log_mask(LOG_GUEST_ERROR,
  448. "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
  449. __func__, offset);
  450. }
  451. static const struct MemoryRegionOps npcm7xx_timer_ops = {
  452. .read = npcm7xx_timer_read,
  453. .write = npcm7xx_timer_write,
  454. .endianness = DEVICE_LITTLE_ENDIAN,
  455. .valid = {
  456. .min_access_size = 4,
  457. .max_access_size = 4,
  458. .unaligned = false,
  459. },
  460. };
  461. /* Called when the QEMU timer expires. */
  462. static void npcm7xx_timer_expired(void *opaque)
  463. {
  464. NPCM7xxTimer *t = opaque;
  465. if (t->tcsr & NPCM7XX_TCSR_CEN) {
  466. npcm7xx_timer_reached_zero(t);
  467. }
  468. }
  469. static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
  470. {
  471. NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
  472. int i;
  473. for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
  474. NPCM7xxTimer *t = &s->timer[i];
  475. npcm7xx_timer_clear(&t->base_timer);
  476. t->tcsr = 0x00000005;
  477. t->ticr = 0x00000000;
  478. }
  479. s->tisr = 0x00000000;
  480. /*
  481. * Set WTCLK to 1(default) and reset all flags except WTRF.
  482. * WTRF is not reset during a core domain reset.
  483. */
  484. s->watchdog_timer.wtcr = 0x00000400 | (s->watchdog_timer.wtcr &
  485. NPCM7XX_WTCR_WTRF);
  486. }
  487. static void npcm7xx_watchdog_timer_expired(void *opaque)
  488. {
  489. NPCM7xxWatchdogTimer *t = opaque;
  490. if (t->wtcr & NPCM7XX_WTCR_WTE) {
  491. if (t->wtcr & NPCM7XX_WTCR_WTIF) {
  492. if (t->wtcr & NPCM7XX_WTCR_WTRE) {
  493. t->wtcr |= NPCM7XX_WTCR_WTRF;
  494. /* send reset signal to CLK module*/
  495. qemu_irq_raise(t->reset_signal);
  496. }
  497. } else {
  498. t->wtcr |= NPCM7XX_WTCR_WTIF;
  499. if (t->wtcr & NPCM7XX_WTCR_WTIE) {
  500. /* send interrupt */
  501. qemu_irq_raise(t->irq);
  502. }
  503. npcm7xx_watchdog_timer_reset_cycles(t,
  504. NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES);
  505. npcm7xx_timer_start(&t->base_timer);
  506. }
  507. }
  508. }
  509. static void npcm7xx_timer_hold_reset(Object *obj, ResetType type)
  510. {
  511. NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
  512. int i;
  513. for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
  514. qemu_irq_lower(s->timer[i].irq);
  515. }
  516. qemu_irq_lower(s->watchdog_timer.irq);
  517. }
  518. static void npcm7xx_timer_init(Object *obj)
  519. {
  520. NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
  521. DeviceState *dev = DEVICE(obj);
  522. SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  523. int i;
  524. NPCM7xxWatchdogTimer *w;
  525. for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
  526. NPCM7xxTimer *t = &s->timer[i];
  527. t->ctrl = s;
  528. timer_init_ns(&t->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
  529. npcm7xx_timer_expired, t);
  530. sysbus_init_irq(sbd, &t->irq);
  531. }
  532. w = &s->watchdog_timer;
  533. w->ctrl = s;
  534. timer_init_ns(&w->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
  535. npcm7xx_watchdog_timer_expired, w);
  536. sysbus_init_irq(sbd, &w->irq);
  537. memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
  538. TYPE_NPCM7XX_TIMER, 4 * KiB);
  539. sysbus_init_mmio(sbd, &s->iomem);
  540. qdev_init_gpio_out_named(dev, &w->reset_signal,
  541. NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
  542. s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL, 0);
  543. }
  544. static const VMStateDescription vmstate_npcm7xx_base_timer = {
  545. .name = "npcm7xx-base-timer",
  546. .version_id = 0,
  547. .minimum_version_id = 0,
  548. .fields = (const VMStateField[]) {
  549. VMSTATE_TIMER(qtimer, NPCM7xxBaseTimer),
  550. VMSTATE_INT64(expires_ns, NPCM7xxBaseTimer),
  551. VMSTATE_INT64(remaining_ns, NPCM7xxBaseTimer),
  552. VMSTATE_END_OF_LIST(),
  553. },
  554. };
  555. static const VMStateDescription vmstate_npcm7xx_timer = {
  556. .name = "npcm7xx-timer",
  557. .version_id = 1,
  558. .minimum_version_id = 1,
  559. .fields = (const VMStateField[]) {
  560. VMSTATE_STRUCT(base_timer, NPCM7xxTimer,
  561. 0, vmstate_npcm7xx_base_timer,
  562. NPCM7xxBaseTimer),
  563. VMSTATE_UINT32(tcsr, NPCM7xxTimer),
  564. VMSTATE_UINT32(ticr, NPCM7xxTimer),
  565. VMSTATE_END_OF_LIST(),
  566. },
  567. };
  568. static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
  569. .name = "npcm7xx-watchdog-timer",
  570. .version_id = 0,
  571. .minimum_version_id = 0,
  572. .fields = (const VMStateField[]) {
  573. VMSTATE_STRUCT(base_timer, NPCM7xxWatchdogTimer,
  574. 0, vmstate_npcm7xx_base_timer,
  575. NPCM7xxBaseTimer),
  576. VMSTATE_UINT32(wtcr, NPCM7xxWatchdogTimer),
  577. VMSTATE_END_OF_LIST(),
  578. },
  579. };
  580. static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
  581. .name = "npcm7xx-timer-ctrl",
  582. .version_id = 2,
  583. .minimum_version_id = 2,
  584. .fields = (const VMStateField[]) {
  585. VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
  586. VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
  587. VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
  588. NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
  589. NPCM7xxTimer),
  590. VMSTATE_STRUCT(watchdog_timer, NPCM7xxTimerCtrlState,
  591. 0, vmstate_npcm7xx_watchdog_timer,
  592. NPCM7xxWatchdogTimer),
  593. VMSTATE_END_OF_LIST(),
  594. },
  595. };
  596. static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
  597. {
  598. ResettableClass *rc = RESETTABLE_CLASS(klass);
  599. DeviceClass *dc = DEVICE_CLASS(klass);
  600. QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
  601. dc->desc = "NPCM7xx Timer Controller";
  602. dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
  603. rc->phases.enter = npcm7xx_timer_enter_reset;
  604. rc->phases.hold = npcm7xx_timer_hold_reset;
  605. }
  606. static const TypeInfo npcm7xx_timer_info = {
  607. .name = TYPE_NPCM7XX_TIMER,
  608. .parent = TYPE_SYS_BUS_DEVICE,
  609. .instance_size = sizeof(NPCM7xxTimerCtrlState),
  610. .class_init = npcm7xx_timer_class_init,
  611. .instance_init = npcm7xx_timer_init,
  612. };
  613. static void npcm7xx_timer_register_type(void)
  614. {
  615. type_register_static(&npcm7xx_timer_info);
  616. }
  617. type_init(npcm7xx_timer_register_type);