imx_gpt.c 16 KB

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  1. /*
  2. * IMX GPT Timer
  3. *
  4. * Copyright (c) 2008 OK Labs
  5. * Copyright (c) 2011 NICTA Pty Ltd
  6. * Originally written by Hans Jiang
  7. * Updated by Peter Chubb
  8. * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
  9. *
  10. * This code is licensed under GPL version 2 or later. See
  11. * the COPYING file in the top-level directory.
  12. *
  13. */
  14. #include "qemu/osdep.h"
  15. #include "hw/irq.h"
  16. #include "hw/timer/imx_gpt.h"
  17. #include "migration/vmstate.h"
  18. #include "qemu/module.h"
  19. #include "qemu/log.h"
  20. #include "trace.h"
  21. static const char *imx_gpt_reg_name(uint32_t reg)
  22. {
  23. switch (reg) {
  24. case 0:
  25. return "CR";
  26. case 1:
  27. return "PR";
  28. case 2:
  29. return "SR";
  30. case 3:
  31. return "IR";
  32. case 4:
  33. return "OCR1";
  34. case 5:
  35. return "OCR2";
  36. case 6:
  37. return "OCR3";
  38. case 7:
  39. return "ICR1";
  40. case 8:
  41. return "ICR2";
  42. case 9:
  43. return "CNT";
  44. default:
  45. return "[?]";
  46. }
  47. }
  48. static const VMStateDescription vmstate_imx_timer_gpt = {
  49. .name = TYPE_IMX_GPT,
  50. .version_id = 3,
  51. .minimum_version_id = 3,
  52. .fields = (const VMStateField[]) {
  53. VMSTATE_UINT32(cr, IMXGPTState),
  54. VMSTATE_UINT32(pr, IMXGPTState),
  55. VMSTATE_UINT32(sr, IMXGPTState),
  56. VMSTATE_UINT32(ir, IMXGPTState),
  57. VMSTATE_UINT32(ocr1, IMXGPTState),
  58. VMSTATE_UINT32(ocr2, IMXGPTState),
  59. VMSTATE_UINT32(ocr3, IMXGPTState),
  60. VMSTATE_UINT32(icr1, IMXGPTState),
  61. VMSTATE_UINT32(icr2, IMXGPTState),
  62. VMSTATE_UINT32(cnt, IMXGPTState),
  63. VMSTATE_UINT32(next_timeout, IMXGPTState),
  64. VMSTATE_UINT32(next_int, IMXGPTState),
  65. VMSTATE_UINT32(freq, IMXGPTState),
  66. VMSTATE_PTIMER(timer, IMXGPTState),
  67. VMSTATE_END_OF_LIST()
  68. }
  69. };
  70. static const IMXClk imx25_gpt_clocks[] = {
  71. CLK_NONE, /* 000 No clock source */
  72. CLK_IPG, /* 001 ipg_clk, 532MHz*/
  73. CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
  74. CLK_NONE, /* 011 not defined */
  75. CLK_32k, /* 100 ipg_clk_32k */
  76. CLK_32k, /* 101 ipg_clk_32k */
  77. CLK_32k, /* 110 ipg_clk_32k */
  78. CLK_32k, /* 111 ipg_clk_32k */
  79. };
  80. static const IMXClk imx31_gpt_clocks[] = {
  81. CLK_NONE, /* 000 No clock source */
  82. CLK_IPG, /* 001 ipg_clk, 532MHz*/
  83. CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
  84. CLK_NONE, /* 011 not defined */
  85. CLK_32k, /* 100 ipg_clk_32k */
  86. CLK_NONE, /* 101 not defined */
  87. CLK_NONE, /* 110 not defined */
  88. CLK_NONE, /* 111 not defined */
  89. };
  90. static const IMXClk imx6_gpt_clocks[] = {
  91. CLK_NONE, /* 000 No clock source */
  92. CLK_IPG, /* 001 ipg_clk, 532MHz*/
  93. CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
  94. CLK_EXT, /* 011 External clock */
  95. CLK_32k, /* 100 ipg_clk_32k */
  96. CLK_HIGH_DIV, /* 101 reference clock / 8 */
  97. CLK_NONE, /* 110 not defined */
  98. CLK_HIGH, /* 111 reference clock */
  99. };
  100. static const IMXClk imx6ul_gpt_clocks[] = {
  101. CLK_NONE, /* 000 No clock source */
  102. CLK_IPG, /* 001 ipg_clk, 532MHz*/
  103. CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
  104. CLK_EXT, /* 011 External clock */
  105. CLK_32k, /* 100 ipg_clk_32k */
  106. CLK_NONE, /* 101 not defined */
  107. CLK_NONE, /* 110 not defined */
  108. CLK_NONE, /* 111 not defined */
  109. };
  110. static const IMXClk imx7_gpt_clocks[] = {
  111. CLK_NONE, /* 000 No clock source */
  112. CLK_IPG, /* 001 ipg_clk, 532MHz*/
  113. CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
  114. CLK_EXT, /* 011 External clock */
  115. CLK_32k, /* 100 ipg_clk_32k */
  116. CLK_HIGH, /* 101 reference clock */
  117. CLK_NONE, /* 110 not defined */
  118. CLK_NONE, /* 111 not defined */
  119. };
  120. /* Must be called from within ptimer_transaction_begin/commit block */
  121. static void imx_gpt_set_freq(IMXGPTState *s)
  122. {
  123. uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
  124. s->freq = imx_ccm_get_clock_frequency(s->ccm,
  125. s->clocks[clksrc]) / (1 + s->pr);
  126. trace_imx_gpt_set_freq(clksrc, s->freq);
  127. if (s->freq) {
  128. ptimer_set_freq(s->timer, s->freq);
  129. }
  130. }
  131. static void imx_gpt_update_int(IMXGPTState *s)
  132. {
  133. if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
  134. qemu_irq_raise(s->irq);
  135. } else {
  136. qemu_irq_lower(s->irq);
  137. }
  138. }
  139. static uint32_t imx_gpt_update_count(IMXGPTState *s)
  140. {
  141. s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
  142. return s->cnt;
  143. }
  144. static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
  145. uint32_t timeout)
  146. {
  147. if ((count < reg) && (timeout > reg)) {
  148. timeout = reg;
  149. }
  150. return timeout;
  151. }
  152. /* Must be called from within ptimer_transaction_begin/commit block */
  153. static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
  154. {
  155. uint32_t timeout = GPT_TIMER_MAX;
  156. uint32_t count;
  157. long long limit;
  158. if (!(s->cr & GPT_CR_EN)) {
  159. /* if not enabled just return */
  160. return;
  161. }
  162. /* update the count */
  163. count = imx_gpt_update_count(s);
  164. if (event) {
  165. /*
  166. * This is an event (the ptimer reached 0 and stopped), and the
  167. * timer counter is now equal to s->next_timeout.
  168. */
  169. if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) {
  170. /* We are in restart mode and we crossed the compare channel 1
  171. * value. We need to reset the counter to 0.
  172. */
  173. count = s->cnt = s->next_timeout = 0;
  174. } else if (count == GPT_TIMER_MAX) {
  175. /* We reached GPT_TIMER_MAX so we need to rollover */
  176. count = s->cnt = s->next_timeout = 0;
  177. }
  178. }
  179. /* now, find the next timeout related to count */
  180. if (s->ir & GPT_IR_OF1IE) {
  181. timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
  182. }
  183. if (s->ir & GPT_IR_OF2IE) {
  184. timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
  185. }
  186. if (s->ir & GPT_IR_OF3IE) {
  187. timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
  188. }
  189. /* find the next set of interrupts to raise for next timer event */
  190. s->next_int = 0;
  191. if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) {
  192. s->next_int |= GPT_SR_OF1;
  193. }
  194. if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) {
  195. s->next_int |= GPT_SR_OF2;
  196. }
  197. if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) {
  198. s->next_int |= GPT_SR_OF3;
  199. }
  200. if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) {
  201. s->next_int |= GPT_SR_ROV;
  202. }
  203. /* the new range to count down from */
  204. limit = timeout - imx_gpt_update_count(s);
  205. if (limit < 0) {
  206. /*
  207. * if we reach here, then QEMU is running too slow and we pass the
  208. * timeout limit while computing it. Let's deliver the interrupt
  209. * and compute a new limit.
  210. */
  211. s->sr |= s->next_int;
  212. imx_gpt_compute_next_timeout(s, event);
  213. imx_gpt_update_int(s);
  214. } else {
  215. /* New timeout value */
  216. s->next_timeout = timeout;
  217. /* reset the limit to the computed range */
  218. ptimer_set_limit(s->timer, limit, 1);
  219. }
  220. }
  221. static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
  222. {
  223. IMXGPTState *s = IMX_GPT(opaque);
  224. uint32_t reg_value = 0;
  225. switch (offset >> 2) {
  226. case 0: /* Control Register */
  227. reg_value = s->cr;
  228. break;
  229. case 1: /* prescaler */
  230. reg_value = s->pr;
  231. break;
  232. case 2: /* Status Register */
  233. reg_value = s->sr;
  234. break;
  235. case 3: /* Interrupt Register */
  236. reg_value = s->ir;
  237. break;
  238. case 4: /* Output Compare Register 1 */
  239. reg_value = s->ocr1;
  240. break;
  241. case 5: /* Output Compare Register 2 */
  242. reg_value = s->ocr2;
  243. break;
  244. case 6: /* Output Compare Register 3 */
  245. reg_value = s->ocr3;
  246. break;
  247. case 7: /* input Capture Register 1 */
  248. qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n",
  249. TYPE_IMX_GPT, __func__);
  250. reg_value = s->icr1;
  251. break;
  252. case 8: /* input Capture Register 2 */
  253. qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n",
  254. TYPE_IMX_GPT, __func__);
  255. reg_value = s->icr2;
  256. break;
  257. case 9: /* cnt */
  258. imx_gpt_update_count(s);
  259. reg_value = s->cnt;
  260. break;
  261. default:
  262. qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
  263. HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
  264. break;
  265. }
  266. trace_imx_gpt_read(imx_gpt_reg_name(offset >> 2), reg_value);
  267. return reg_value;
  268. }
  269. static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset)
  270. {
  271. ptimer_transaction_begin(s->timer);
  272. /* stop timer */
  273. ptimer_stop(s->timer);
  274. /* Soft reset and hard reset differ only in their handling of the CR
  275. * register -- soft reset preserves the values of some bits there.
  276. */
  277. if (is_soft_reset) {
  278. /* Clear all CR bits except those that are preserved by soft reset. */
  279. s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN |
  280. GPT_CR_WAITEN | GPT_CR_DBGEN |
  281. (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT);
  282. } else {
  283. s->cr = 0;
  284. }
  285. s->sr = 0;
  286. s->pr = 0;
  287. s->ir = 0;
  288. s->cnt = 0;
  289. s->ocr1 = GPT_TIMER_MAX;
  290. s->ocr2 = GPT_TIMER_MAX;
  291. s->ocr3 = GPT_TIMER_MAX;
  292. s->icr1 = 0;
  293. s->icr2 = 0;
  294. s->next_timeout = GPT_TIMER_MAX;
  295. s->next_int = 0;
  296. /* compute new freq */
  297. imx_gpt_set_freq(s);
  298. /* reset the limit to GPT_TIMER_MAX */
  299. ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
  300. /* if the timer is still enabled, restart it */
  301. if (s->freq && (s->cr & GPT_CR_EN)) {
  302. ptimer_run(s->timer, 1);
  303. }
  304. ptimer_transaction_commit(s->timer);
  305. }
  306. static void imx_gpt_soft_reset(DeviceState *dev)
  307. {
  308. IMXGPTState *s = IMX_GPT(dev);
  309. imx_gpt_reset_common(s, true);
  310. }
  311. static void imx_gpt_reset(DeviceState *dev)
  312. {
  313. IMXGPTState *s = IMX_GPT(dev);
  314. imx_gpt_reset_common(s, false);
  315. }
  316. static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
  317. unsigned size)
  318. {
  319. IMXGPTState *s = IMX_GPT(opaque);
  320. uint32_t oldreg;
  321. trace_imx_gpt_write(imx_gpt_reg_name(offset >> 2), (uint32_t)value);
  322. switch (offset >> 2) {
  323. case 0:
  324. oldreg = s->cr;
  325. s->cr = value & ~0x7c14;
  326. if (s->cr & GPT_CR_SWR) { /* force reset */
  327. /* handle the reset */
  328. imx_gpt_soft_reset(DEVICE(s));
  329. } else {
  330. /* set our freq, as the source might have changed */
  331. ptimer_transaction_begin(s->timer);
  332. imx_gpt_set_freq(s);
  333. if ((oldreg ^ s->cr) & GPT_CR_EN) {
  334. if (s->cr & GPT_CR_EN) {
  335. if (s->cr & GPT_CR_ENMOD) {
  336. s->next_timeout = GPT_TIMER_MAX;
  337. ptimer_set_count(s->timer, GPT_TIMER_MAX);
  338. imx_gpt_compute_next_timeout(s, false);
  339. }
  340. ptimer_run(s->timer, 1);
  341. } else {
  342. /* stop timer */
  343. ptimer_stop(s->timer);
  344. }
  345. }
  346. ptimer_transaction_commit(s->timer);
  347. }
  348. break;
  349. case 1: /* Prescaler */
  350. s->pr = value & 0xfff;
  351. ptimer_transaction_begin(s->timer);
  352. imx_gpt_set_freq(s);
  353. ptimer_transaction_commit(s->timer);
  354. break;
  355. case 2: /* SR */
  356. s->sr &= ~(value & 0x3f);
  357. imx_gpt_update_int(s);
  358. break;
  359. case 3: /* IR -- interrupt register */
  360. s->ir = value & 0x3f;
  361. imx_gpt_update_int(s);
  362. ptimer_transaction_begin(s->timer);
  363. imx_gpt_compute_next_timeout(s, false);
  364. ptimer_transaction_commit(s->timer);
  365. break;
  366. case 4: /* OCR1 -- output compare register */
  367. s->ocr1 = value;
  368. ptimer_transaction_begin(s->timer);
  369. /* In non-freerun mode, reset count when this register is written */
  370. if (!(s->cr & GPT_CR_FRR)) {
  371. s->next_timeout = GPT_TIMER_MAX;
  372. ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
  373. }
  374. /* compute the new timeout */
  375. imx_gpt_compute_next_timeout(s, false);
  376. ptimer_transaction_commit(s->timer);
  377. break;
  378. case 5: /* OCR2 -- output compare register */
  379. s->ocr2 = value;
  380. /* compute the new timeout */
  381. ptimer_transaction_begin(s->timer);
  382. imx_gpt_compute_next_timeout(s, false);
  383. ptimer_transaction_commit(s->timer);
  384. break;
  385. case 6: /* OCR3 -- output compare register */
  386. s->ocr3 = value;
  387. /* compute the new timeout */
  388. ptimer_transaction_begin(s->timer);
  389. imx_gpt_compute_next_timeout(s, false);
  390. ptimer_transaction_commit(s->timer);
  391. break;
  392. default:
  393. qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
  394. HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
  395. break;
  396. }
  397. }
  398. static void imx_gpt_timeout(void *opaque)
  399. {
  400. IMXGPTState *s = IMX_GPT(opaque);
  401. trace_imx_gpt_timeout();
  402. s->sr |= s->next_int;
  403. s->next_int = 0;
  404. imx_gpt_compute_next_timeout(s, true);
  405. imx_gpt_update_int(s);
  406. if (s->freq && (s->cr & GPT_CR_EN)) {
  407. ptimer_run(s->timer, 1);
  408. }
  409. }
  410. static const MemoryRegionOps imx_gpt_ops = {
  411. .read = imx_gpt_read,
  412. .write = imx_gpt_write,
  413. .endianness = DEVICE_NATIVE_ENDIAN,
  414. };
  415. static void imx_gpt_realize(DeviceState *dev, Error **errp)
  416. {
  417. IMXGPTState *s = IMX_GPT(dev);
  418. SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  419. sysbus_init_irq(sbd, &s->irq);
  420. memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
  421. 0x00001000);
  422. sysbus_init_mmio(sbd, &s->iomem);
  423. s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_LEGACY);
  424. }
  425. static void imx_gpt_class_init(ObjectClass *klass, void *data)
  426. {
  427. DeviceClass *dc = DEVICE_CLASS(klass);
  428. dc->realize = imx_gpt_realize;
  429. device_class_set_legacy_reset(dc, imx_gpt_reset);
  430. dc->vmsd = &vmstate_imx_timer_gpt;
  431. dc->desc = "i.MX general timer";
  432. }
  433. static void imx25_gpt_init(Object *obj)
  434. {
  435. IMXGPTState *s = IMX_GPT(obj);
  436. s->clocks = imx25_gpt_clocks;
  437. }
  438. static void imx31_gpt_init(Object *obj)
  439. {
  440. IMXGPTState *s = IMX_GPT(obj);
  441. s->clocks = imx31_gpt_clocks;
  442. }
  443. static void imx6_gpt_init(Object *obj)
  444. {
  445. IMXGPTState *s = IMX_GPT(obj);
  446. s->clocks = imx6_gpt_clocks;
  447. }
  448. static void imx6ul_gpt_init(Object *obj)
  449. {
  450. IMXGPTState *s = IMX_GPT(obj);
  451. s->clocks = imx6ul_gpt_clocks;
  452. }
  453. static void imx7_gpt_init(Object *obj)
  454. {
  455. IMXGPTState *s = IMX_GPT(obj);
  456. s->clocks = imx7_gpt_clocks;
  457. }
  458. static const TypeInfo imx25_gpt_info = {
  459. .name = TYPE_IMX25_GPT,
  460. .parent = TYPE_SYS_BUS_DEVICE,
  461. .instance_size = sizeof(IMXGPTState),
  462. .instance_init = imx25_gpt_init,
  463. .class_init = imx_gpt_class_init,
  464. };
  465. static const TypeInfo imx31_gpt_info = {
  466. .name = TYPE_IMX31_GPT,
  467. .parent = TYPE_IMX25_GPT,
  468. .instance_init = imx31_gpt_init,
  469. };
  470. static const TypeInfo imx6_gpt_info = {
  471. .name = TYPE_IMX6_GPT,
  472. .parent = TYPE_IMX25_GPT,
  473. .instance_init = imx6_gpt_init,
  474. };
  475. static const TypeInfo imx6ul_gpt_info = {
  476. .name = TYPE_IMX6UL_GPT,
  477. .parent = TYPE_IMX25_GPT,
  478. .instance_init = imx6ul_gpt_init,
  479. };
  480. static const TypeInfo imx7_gpt_info = {
  481. .name = TYPE_IMX7_GPT,
  482. .parent = TYPE_IMX25_GPT,
  483. .instance_init = imx7_gpt_init,
  484. };
  485. static void imx_gpt_register_types(void)
  486. {
  487. type_register_static(&imx25_gpt_info);
  488. type_register_static(&imx31_gpt_info);
  489. type_register_static(&imx6_gpt_info);
  490. type_register_static(&imx6ul_gpt_info);
  491. type_register_static(&imx7_gpt_info);
  492. }
  493. type_init(imx_gpt_register_types)