virtio-vga.c 8.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288
  1. #include "qemu/osdep.h"
  2. #include "hw/pci/pci.h"
  3. #include "hw/qdev-properties.h"
  4. #include "hw/virtio/virtio-gpu.h"
  5. #include "qapi/error.h"
  6. #include "qemu/module.h"
  7. #include "virtio-vga.h"
  8. #include "qom/object.h"
  9. static void virtio_vga_base_invalidate_display(void *opaque)
  10. {
  11. VirtIOVGABase *vvga = opaque;
  12. VirtIOGPUBase *g = vvga->vgpu;
  13. if (g->enable) {
  14. g->hw_ops->invalidate(g);
  15. } else {
  16. vvga->vga.hw_ops->invalidate(&vvga->vga);
  17. }
  18. }
  19. static void virtio_vga_base_update_display(void *opaque)
  20. {
  21. VirtIOVGABase *vvga = opaque;
  22. VirtIOGPUBase *g = vvga->vgpu;
  23. if (g->enable) {
  24. g->hw_ops->gfx_update(g);
  25. } else {
  26. vvga->vga.hw_ops->gfx_update(&vvga->vga);
  27. }
  28. }
  29. static void virtio_vga_base_text_update(void *opaque, console_ch_t *chardata)
  30. {
  31. VirtIOVGABase *vvga = opaque;
  32. VirtIOGPUBase *g = vvga->vgpu;
  33. if (g->enable) {
  34. if (g->hw_ops->text_update) {
  35. g->hw_ops->text_update(g, chardata);
  36. }
  37. } else {
  38. if (vvga->vga.hw_ops->text_update) {
  39. vvga->vga.hw_ops->text_update(&vvga->vga, chardata);
  40. }
  41. }
  42. }
  43. static void virtio_vga_base_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
  44. {
  45. VirtIOVGABase *vvga = opaque;
  46. VirtIOGPUBase *g = vvga->vgpu;
  47. if (g->hw_ops->ui_info) {
  48. g->hw_ops->ui_info(g, idx, info);
  49. }
  50. }
  51. static void virtio_vga_base_gl_block(void *opaque, bool block)
  52. {
  53. VirtIOVGABase *vvga = opaque;
  54. VirtIOGPUBase *g = vvga->vgpu;
  55. if (g->hw_ops->gl_block) {
  56. g->hw_ops->gl_block(g, block);
  57. }
  58. }
  59. static int virtio_vga_base_get_flags(void *opaque)
  60. {
  61. VirtIOVGABase *vvga = opaque;
  62. VirtIOGPUBase *g = vvga->vgpu;
  63. return g->hw_ops->get_flags(g);
  64. }
  65. static const GraphicHwOps virtio_vga_base_ops = {
  66. .get_flags = virtio_vga_base_get_flags,
  67. .invalidate = virtio_vga_base_invalidate_display,
  68. .gfx_update = virtio_vga_base_update_display,
  69. .text_update = virtio_vga_base_text_update,
  70. .ui_info = virtio_vga_base_ui_info,
  71. .gl_block = virtio_vga_base_gl_block,
  72. };
  73. static const VMStateDescription vmstate_virtio_vga_base = {
  74. .name = "virtio-vga",
  75. .version_id = 2,
  76. .minimum_version_id = 2,
  77. .fields = (const VMStateField[]) {
  78. /* no pci stuff here, saving the virtio device will handle that */
  79. VMSTATE_STRUCT(vga, VirtIOVGABase, 0,
  80. vmstate_vga_common, VGACommonState),
  81. VMSTATE_END_OF_LIST()
  82. }
  83. };
  84. /* VGA device wrapper around PCI device around virtio GPU */
  85. static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
  86. {
  87. VirtIOVGABase *vvga = VIRTIO_VGA_BASE(vpci_dev);
  88. VirtIOGPUBase *g = vvga->vgpu;
  89. VGACommonState *vga = &vvga->vga;
  90. uint32_t offset;
  91. int i;
  92. /* init vga compat bits */
  93. vga->vram_size_mb = 8;
  94. if (!vga_common_init(vga, OBJECT(vpci_dev), errp)) {
  95. return;
  96. }
  97. vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev),
  98. pci_address_space_io(&vpci_dev->pci_dev), true);
  99. pci_register_bar(&vpci_dev->pci_dev, 0,
  100. PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
  101. vpci_dev->modern_io_bar_idx = 5;
  102. if (!virtio_gpu_hostmem_enabled(g->conf)) {
  103. /*
  104. * Configure virtio bar and regions
  105. *
  106. * We use bar #2 for the mmio regions, to be compatible with stdvga.
  107. * virtio regions are moved to the end of bar #2, to make room for
  108. * the stdvga mmio registers at the start of bar #2.
  109. */
  110. vpci_dev->modern_mem_bar_idx = 2;
  111. vpci_dev->msix_bar_idx = 4;
  112. } else {
  113. vpci_dev->msix_bar_idx = 1;
  114. vpci_dev->modern_mem_bar_idx = 2;
  115. memory_region_init(&g->hostmem, OBJECT(g), "virtio-gpu-hostmem",
  116. g->conf.hostmem);
  117. pci_register_bar(&vpci_dev->pci_dev, 4,
  118. PCI_BASE_ADDRESS_SPACE_MEMORY |
  119. PCI_BASE_ADDRESS_MEM_PREFETCH |
  120. PCI_BASE_ADDRESS_MEM_TYPE_64,
  121. &g->hostmem);
  122. virtio_pci_add_shm_cap(vpci_dev, 4, 0, g->conf.hostmem,
  123. VIRTIO_GPU_SHM_ID_HOST_VISIBLE);
  124. }
  125. if (!(vpci_dev->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ)) {
  126. /*
  127. * with page-per-vq=off there is no padding space we can use
  128. * for the stdvga registers. Make the common and isr regions
  129. * smaller then.
  130. */
  131. vpci_dev->common.size /= 2;
  132. vpci_dev->isr.size /= 2;
  133. }
  134. offset = memory_region_size(&vpci_dev->modern_bar);
  135. offset -= vpci_dev->notify.size;
  136. vpci_dev->notify.offset = offset;
  137. offset -= vpci_dev->device.size;
  138. vpci_dev->device.offset = offset;
  139. offset -= vpci_dev->isr.size;
  140. vpci_dev->isr.offset = offset;
  141. offset -= vpci_dev->common.size;
  142. vpci_dev->common.offset = offset;
  143. /* init virtio bits */
  144. virtio_pci_force_virtio_1(vpci_dev);
  145. if (!qdev_realize(DEVICE(g), BUS(&vpci_dev->bus), errp)) {
  146. return;
  147. }
  148. /* add stdvga mmio regions */
  149. pci_std_vga_mmio_region_init(vga, OBJECT(vvga), &vpci_dev->modern_bar,
  150. vvga->vga_mrs, true, false);
  151. vga->con = g->scanout[0].con;
  152. graphic_console_set_hwops(vga->con, &virtio_vga_base_ops, vvga);
  153. for (i = 0; i < g->conf.max_outputs; i++) {
  154. object_property_set_link(OBJECT(g->scanout[i].con), "device",
  155. OBJECT(vpci_dev), &error_abort);
  156. }
  157. }
  158. static void virtio_vga_base_reset_hold(Object *obj, ResetType type)
  159. {
  160. VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(obj);
  161. VirtIOVGABase *vvga = VIRTIO_VGA_BASE(obj);
  162. /* reset virtio-gpu */
  163. if (klass->parent_phases.hold) {
  164. klass->parent_phases.hold(obj, type);
  165. }
  166. /* reset vga */
  167. vga_common_reset(&vvga->vga);
  168. vga_dirty_log_start(&vvga->vga);
  169. }
  170. static bool virtio_vga_get_big_endian_fb(Object *obj, Error **errp)
  171. {
  172. VirtIOVGABase *d = VIRTIO_VGA_BASE(obj);
  173. return d->vga.big_endian_fb;
  174. }
  175. static void virtio_vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
  176. {
  177. VirtIOVGABase *d = VIRTIO_VGA_BASE(obj);
  178. d->vga.big_endian_fb = value;
  179. }
  180. static const Property virtio_vga_base_properties[] = {
  181. DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy),
  182. };
  183. static void virtio_vga_base_class_init(ObjectClass *klass, void *data)
  184. {
  185. DeviceClass *dc = DEVICE_CLASS(klass);
  186. VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
  187. VirtIOVGABaseClass *v = VIRTIO_VGA_BASE_CLASS(klass);
  188. PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
  189. ResettableClass *rc = RESETTABLE_CLASS(klass);
  190. set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
  191. device_class_set_props(dc, virtio_vga_base_properties);
  192. dc->vmsd = &vmstate_virtio_vga_base;
  193. dc->hotpluggable = false;
  194. resettable_class_set_parent_phases(rc, NULL, virtio_vga_base_reset_hold,
  195. NULL, &v->parent_phases);
  196. k->realize = virtio_vga_base_realize;
  197. pcidev_k->romfile = "vgabios-virtio.bin";
  198. pcidev_k->class_id = PCI_CLASS_DISPLAY_VGA;
  199. /* Expose framebuffer byteorder via QOM */
  200. object_class_property_add_bool(klass, "big-endian-framebuffer",
  201. virtio_vga_get_big_endian_fb,
  202. virtio_vga_set_big_endian_fb);
  203. }
  204. static const TypeInfo virtio_vga_base_info = {
  205. .name = TYPE_VIRTIO_VGA_BASE,
  206. .parent = TYPE_VIRTIO_PCI,
  207. .instance_size = sizeof(VirtIOVGABase),
  208. .class_size = sizeof(VirtIOVGABaseClass),
  209. .class_init = virtio_vga_base_class_init,
  210. .abstract = true,
  211. };
  212. module_obj(TYPE_VIRTIO_VGA_BASE);
  213. module_kconfig(VIRTIO_VGA);
  214. #define TYPE_VIRTIO_VGA "virtio-vga"
  215. typedef struct VirtIOVGA VirtIOVGA;
  216. DECLARE_INSTANCE_CHECKER(VirtIOVGA, VIRTIO_VGA,
  217. TYPE_VIRTIO_VGA)
  218. struct VirtIOVGA {
  219. VirtIOVGABase parent_obj;
  220. VirtIOGPU vdev;
  221. };
  222. static void virtio_vga_inst_initfn(Object *obj)
  223. {
  224. VirtIOVGA *dev = VIRTIO_VGA(obj);
  225. virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
  226. TYPE_VIRTIO_GPU);
  227. VIRTIO_VGA_BASE(dev)->vgpu = VIRTIO_GPU_BASE(&dev->vdev);
  228. }
  229. static VirtioPCIDeviceTypeInfo virtio_vga_info = {
  230. .generic_name = TYPE_VIRTIO_VGA,
  231. .parent = TYPE_VIRTIO_VGA_BASE,
  232. .instance_size = sizeof(VirtIOVGA),
  233. .instance_init = virtio_vga_inst_initfn,
  234. };
  235. module_obj(TYPE_VIRTIO_VGA);
  236. static void virtio_vga_register_types(void)
  237. {
  238. type_register_static(&virtio_vga_base_info);
  239. virtio_pci_types_register(&virtio_vga_info);
  240. }
  241. type_init(virtio_vga_register_types)