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qtest.c 20 KB

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  1. /*
  2. * Test Server
  3. *
  4. * Copyright IBM, Corp. 2011
  5. *
  6. * Authors:
  7. * Anthony Liguori <aliguori@us.ibm.com>
  8. *
  9. * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10. * See the COPYING file in the top-level directory.
  11. *
  12. */
  13. #include "qemu/osdep.h"
  14. #include "qapi/error.h"
  15. #include "qemu-common.h"
  16. #include "cpu.h"
  17. #include "sysemu/qtest.h"
  18. #include "hw/qdev.h"
  19. #include "sysemu/char.h"
  20. #include "exec/ioport.h"
  21. #include "exec/memory.h"
  22. #include "hw/irq.h"
  23. #include "sysemu/accel.h"
  24. #include "sysemu/sysemu.h"
  25. #include "sysemu/cpus.h"
  26. #include "qemu/config-file.h"
  27. #include "qemu/option.h"
  28. #include "qemu/error-report.h"
  29. #include "qemu/cutils.h"
  30. #ifdef TARGET_PPC64
  31. #include "hw/ppc/spapr_rtas.h"
  32. #endif
  33. #define MAX_IRQ 256
  34. bool qtest_allowed;
  35. static DeviceState *irq_intercept_dev;
  36. static FILE *qtest_log_fp;
  37. static CharBackend qtest_chr;
  38. static GString *inbuf;
  39. static int irq_levels[MAX_IRQ];
  40. static qemu_timeval start_time;
  41. static bool qtest_opened;
  42. #define FMT_timeval "%ld.%06ld"
  43. /**
  44. * QTest Protocol
  45. *
  46. * Line based protocol, request/response based. Server can send async messages
  47. * so clients should always handle many async messages before the response
  48. * comes in.
  49. *
  50. * Valid requests
  51. *
  52. * Clock management:
  53. *
  54. * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
  55. * let you adjust the value of the clock (monotonically). All the commands
  56. * return the current value of the clock in nanoseconds.
  57. *
  58. * > clock_step
  59. * < OK VALUE
  60. *
  61. * Advance the clock to the next deadline. Useful when waiting for
  62. * asynchronous events.
  63. *
  64. * > clock_step NS
  65. * < OK VALUE
  66. *
  67. * Advance the clock by NS nanoseconds.
  68. *
  69. * > clock_set NS
  70. * < OK VALUE
  71. *
  72. * Advance the clock to NS nanoseconds (do nothing if it's already past).
  73. *
  74. * PIO and memory access:
  75. *
  76. * > outb ADDR VALUE
  77. * < OK
  78. *
  79. * > outw ADDR VALUE
  80. * < OK
  81. *
  82. * > outl ADDR VALUE
  83. * < OK
  84. *
  85. * > inb ADDR
  86. * < OK VALUE
  87. *
  88. * > inw ADDR
  89. * < OK VALUE
  90. *
  91. * > inl ADDR
  92. * < OK VALUE
  93. *
  94. * > writeb ADDR VALUE
  95. * < OK
  96. *
  97. * > writew ADDR VALUE
  98. * < OK
  99. *
  100. * > writel ADDR VALUE
  101. * < OK
  102. *
  103. * > writeq ADDR VALUE
  104. * < OK
  105. *
  106. * > readb ADDR
  107. * < OK VALUE
  108. *
  109. * > readw ADDR
  110. * < OK VALUE
  111. *
  112. * > readl ADDR
  113. * < OK VALUE
  114. *
  115. * > readq ADDR
  116. * < OK VALUE
  117. *
  118. * > read ADDR SIZE
  119. * < OK DATA
  120. *
  121. * > write ADDR SIZE DATA
  122. * < OK
  123. *
  124. * > b64read ADDR SIZE
  125. * < OK B64_DATA
  126. *
  127. * > b64write ADDR SIZE B64_DATA
  128. * < OK
  129. *
  130. * > memset ADDR SIZE VALUE
  131. * < OK
  132. *
  133. * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
  134. * For 'memset' a zero size is permitted and does nothing.
  135. *
  136. * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
  137. * than the expected size, the value will be zero filled at the end of the data
  138. * sequence.
  139. *
  140. * B64_DATA is an arbitrarily long base64 encoded string.
  141. * If the sizes do not match, the data will be truncated.
  142. *
  143. * IRQ management:
  144. *
  145. * > irq_intercept_in QOM-PATH
  146. * < OK
  147. *
  148. * > irq_intercept_out QOM-PATH
  149. * < OK
  150. *
  151. * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
  152. * QOM-PATH. When the pin is triggered, one of the following async messages
  153. * will be printed to the qtest stream:
  154. *
  155. * IRQ raise NUM
  156. * IRQ lower NUM
  157. *
  158. * where NUM is an IRQ number. For the PC, interrupts can be intercepted
  159. * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
  160. * NUM=0 even though it is remapped to GSI 2).
  161. */
  162. static int hex2nib(char ch)
  163. {
  164. if (ch >= '0' && ch <= '9') {
  165. return ch - '0';
  166. } else if (ch >= 'a' && ch <= 'f') {
  167. return 10 + (ch - 'a');
  168. } else if (ch >= 'A' && ch <= 'F') {
  169. return 10 + (ch - 'A');
  170. } else {
  171. return -1;
  172. }
  173. }
  174. static void qtest_get_time(qemu_timeval *tv)
  175. {
  176. qemu_gettimeofday(tv);
  177. tv->tv_sec -= start_time.tv_sec;
  178. tv->tv_usec -= start_time.tv_usec;
  179. if (tv->tv_usec < 0) {
  180. tv->tv_usec += 1000000;
  181. tv->tv_sec -= 1;
  182. }
  183. }
  184. static void qtest_send_prefix(CharBackend *chr)
  185. {
  186. qemu_timeval tv;
  187. if (!qtest_log_fp || !qtest_opened) {
  188. return;
  189. }
  190. qtest_get_time(&tv);
  191. fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
  192. (long) tv.tv_sec, (long) tv.tv_usec);
  193. }
  194. static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt, ...)
  195. {
  196. va_list ap;
  197. if (!qtest_log_fp || !qtest_opened) {
  198. return;
  199. }
  200. qtest_send_prefix(NULL);
  201. va_start(ap, fmt);
  202. vfprintf(qtest_log_fp, fmt, ap);
  203. va_end(ap);
  204. }
  205. static void do_qtest_send(CharBackend *chr, const char *str, size_t len)
  206. {
  207. qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
  208. if (qtest_log_fp && qtest_opened) {
  209. fprintf(qtest_log_fp, "%s", str);
  210. }
  211. }
  212. static void qtest_send(CharBackend *chr, const char *str)
  213. {
  214. do_qtest_send(chr, str, strlen(str));
  215. }
  216. static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend *chr,
  217. const char *fmt, ...)
  218. {
  219. va_list ap;
  220. gchar *buffer;
  221. va_start(ap, fmt);
  222. buffer = g_strdup_vprintf(fmt, ap);
  223. qtest_send(chr, buffer);
  224. g_free(buffer);
  225. va_end(ap);
  226. }
  227. static void qtest_irq_handler(void *opaque, int n, int level)
  228. {
  229. qemu_irq old_irq = *(qemu_irq *)opaque;
  230. qemu_set_irq(old_irq, level);
  231. if (irq_levels[n] != level) {
  232. CharBackend *chr = &qtest_chr;
  233. irq_levels[n] = level;
  234. qtest_send_prefix(chr);
  235. qtest_sendf(chr, "IRQ %s %d\n",
  236. level ? "raise" : "lower", n);
  237. }
  238. }
  239. static void qtest_process_command(CharBackend *chr, gchar **words)
  240. {
  241. const gchar *command;
  242. g_assert(words);
  243. command = words[0];
  244. if (qtest_log_fp) {
  245. qemu_timeval tv;
  246. int i;
  247. qtest_get_time(&tv);
  248. fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
  249. (long) tv.tv_sec, (long) tv.tv_usec);
  250. for (i = 0; words[i]; i++) {
  251. fprintf(qtest_log_fp, " %s", words[i]);
  252. }
  253. fprintf(qtest_log_fp, "\n");
  254. }
  255. g_assert(command);
  256. if (strcmp(words[0], "irq_intercept_out") == 0
  257. || strcmp(words[0], "irq_intercept_in") == 0) {
  258. DeviceState *dev;
  259. NamedGPIOList *ngl;
  260. g_assert(words[1]);
  261. dev = DEVICE(object_resolve_path(words[1], NULL));
  262. if (!dev) {
  263. qtest_send_prefix(chr);
  264. qtest_send(chr, "FAIL Unknown device\n");
  265. return;
  266. }
  267. if (irq_intercept_dev) {
  268. qtest_send_prefix(chr);
  269. if (irq_intercept_dev != dev) {
  270. qtest_send(chr, "FAIL IRQ intercept already enabled\n");
  271. } else {
  272. qtest_send(chr, "OK\n");
  273. }
  274. return;
  275. }
  276. QLIST_FOREACH(ngl, &dev->gpios, node) {
  277. /* We don't support intercept of named GPIOs yet */
  278. if (ngl->name) {
  279. continue;
  280. }
  281. if (words[0][14] == 'o') {
  282. int i;
  283. for (i = 0; i < ngl->num_out; ++i) {
  284. qemu_irq *disconnected = g_new0(qemu_irq, 1);
  285. qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
  286. disconnected, i);
  287. *disconnected = qdev_intercept_gpio_out(dev, icpt,
  288. ngl->name, i);
  289. }
  290. } else {
  291. qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
  292. ngl->num_in);
  293. }
  294. }
  295. irq_intercept_dev = dev;
  296. qtest_send_prefix(chr);
  297. qtest_send(chr, "OK\n");
  298. } else if (strcmp(words[0], "outb") == 0 ||
  299. strcmp(words[0], "outw") == 0 ||
  300. strcmp(words[0], "outl") == 0) {
  301. unsigned long addr;
  302. unsigned long value;
  303. g_assert(words[1] && words[2]);
  304. g_assert(qemu_strtoul(words[1], NULL, 0, &addr) == 0);
  305. g_assert(qemu_strtoul(words[2], NULL, 0, &value) == 0);
  306. g_assert(addr <= 0xffff);
  307. if (words[0][3] == 'b') {
  308. cpu_outb(addr, value);
  309. } else if (words[0][3] == 'w') {
  310. cpu_outw(addr, value);
  311. } else if (words[0][3] == 'l') {
  312. cpu_outl(addr, value);
  313. }
  314. qtest_send_prefix(chr);
  315. qtest_send(chr, "OK\n");
  316. } else if (strcmp(words[0], "inb") == 0 ||
  317. strcmp(words[0], "inw") == 0 ||
  318. strcmp(words[0], "inl") == 0) {
  319. unsigned long addr;
  320. uint32_t value = -1U;
  321. g_assert(words[1]);
  322. g_assert(qemu_strtoul(words[1], NULL, 0, &addr) == 0);
  323. g_assert(addr <= 0xffff);
  324. if (words[0][2] == 'b') {
  325. value = cpu_inb(addr);
  326. } else if (words[0][2] == 'w') {
  327. value = cpu_inw(addr);
  328. } else if (words[0][2] == 'l') {
  329. value = cpu_inl(addr);
  330. }
  331. qtest_send_prefix(chr);
  332. qtest_sendf(chr, "OK 0x%04x\n", value);
  333. } else if (strcmp(words[0], "writeb") == 0 ||
  334. strcmp(words[0], "writew") == 0 ||
  335. strcmp(words[0], "writel") == 0 ||
  336. strcmp(words[0], "writeq") == 0) {
  337. uint64_t addr;
  338. uint64_t value;
  339. g_assert(words[1] && words[2]);
  340. g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
  341. g_assert(qemu_strtou64(words[2], NULL, 0, &value) == 0);
  342. if (words[0][5] == 'b') {
  343. uint8_t data = value;
  344. cpu_physical_memory_write(addr, &data, 1);
  345. } else if (words[0][5] == 'w') {
  346. uint16_t data = value;
  347. tswap16s(&data);
  348. cpu_physical_memory_write(addr, &data, 2);
  349. } else if (words[0][5] == 'l') {
  350. uint32_t data = value;
  351. tswap32s(&data);
  352. cpu_physical_memory_write(addr, &data, 4);
  353. } else if (words[0][5] == 'q') {
  354. uint64_t data = value;
  355. tswap64s(&data);
  356. cpu_physical_memory_write(addr, &data, 8);
  357. }
  358. qtest_send_prefix(chr);
  359. qtest_send(chr, "OK\n");
  360. } else if (strcmp(words[0], "readb") == 0 ||
  361. strcmp(words[0], "readw") == 0 ||
  362. strcmp(words[0], "readl") == 0 ||
  363. strcmp(words[0], "readq") == 0) {
  364. uint64_t addr;
  365. uint64_t value = UINT64_C(-1);
  366. g_assert(words[1]);
  367. g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
  368. if (words[0][4] == 'b') {
  369. uint8_t data;
  370. cpu_physical_memory_read(addr, &data, 1);
  371. value = data;
  372. } else if (words[0][4] == 'w') {
  373. uint16_t data;
  374. cpu_physical_memory_read(addr, &data, 2);
  375. value = tswap16(data);
  376. } else if (words[0][4] == 'l') {
  377. uint32_t data;
  378. cpu_physical_memory_read(addr, &data, 4);
  379. value = tswap32(data);
  380. } else if (words[0][4] == 'q') {
  381. cpu_physical_memory_read(addr, &value, 8);
  382. tswap64s(&value);
  383. }
  384. qtest_send_prefix(chr);
  385. qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
  386. } else if (strcmp(words[0], "read") == 0) {
  387. uint64_t addr, len, i;
  388. uint8_t *data;
  389. char *enc;
  390. g_assert(words[1] && words[2]);
  391. g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
  392. g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
  393. /* We'd send garbage to libqtest if len is 0 */
  394. g_assert(len);
  395. data = g_malloc(len);
  396. cpu_physical_memory_read(addr, data, len);
  397. enc = g_malloc(2 * len + 1);
  398. for (i = 0; i < len; i++) {
  399. sprintf(&enc[i * 2], "%02x", data[i]);
  400. }
  401. qtest_send_prefix(chr);
  402. qtest_sendf(chr, "OK 0x%s\n", enc);
  403. g_free(data);
  404. g_free(enc);
  405. } else if (strcmp(words[0], "b64read") == 0) {
  406. uint64_t addr, len;
  407. uint8_t *data;
  408. gchar *b64_data;
  409. g_assert(words[1] && words[2]);
  410. g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
  411. g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
  412. data = g_malloc(len);
  413. cpu_physical_memory_read(addr, data, len);
  414. b64_data = g_base64_encode(data, len);
  415. qtest_send_prefix(chr);
  416. qtest_sendf(chr, "OK %s\n", b64_data);
  417. g_free(data);
  418. g_free(b64_data);
  419. } else if (strcmp(words[0], "write") == 0) {
  420. uint64_t addr, len, i;
  421. uint8_t *data;
  422. size_t data_len;
  423. g_assert(words[1] && words[2] && words[3]);
  424. g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
  425. g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
  426. data_len = strlen(words[3]);
  427. if (data_len < 3) {
  428. qtest_send(chr, "ERR invalid argument size\n");
  429. return;
  430. }
  431. data = g_malloc(len);
  432. for (i = 0; i < len; i++) {
  433. if ((i * 2 + 4) <= data_len) {
  434. data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
  435. data[i] |= hex2nib(words[3][i * 2 + 3]);
  436. } else {
  437. data[i] = 0;
  438. }
  439. }
  440. cpu_physical_memory_write(addr, data, len);
  441. g_free(data);
  442. qtest_send_prefix(chr);
  443. qtest_send(chr, "OK\n");
  444. } else if (strcmp(words[0], "memset") == 0) {
  445. uint64_t addr, len;
  446. uint8_t *data;
  447. unsigned long pattern;
  448. g_assert(words[1] && words[2] && words[3]);
  449. g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
  450. g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
  451. g_assert(qemu_strtoul(words[3], NULL, 0, &pattern) == 0);
  452. if (len) {
  453. data = g_malloc(len);
  454. memset(data, pattern, len);
  455. cpu_physical_memory_write(addr, data, len);
  456. g_free(data);
  457. }
  458. qtest_send_prefix(chr);
  459. qtest_send(chr, "OK\n");
  460. } else if (strcmp(words[0], "b64write") == 0) {
  461. uint64_t addr, len;
  462. uint8_t *data;
  463. size_t data_len;
  464. gsize out_len;
  465. g_assert(words[1] && words[2] && words[3]);
  466. g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
  467. g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
  468. data_len = strlen(words[3]);
  469. if (data_len < 3) {
  470. qtest_send(chr, "ERR invalid argument size\n");
  471. return;
  472. }
  473. data = g_base64_decode_inplace(words[3], &out_len);
  474. if (out_len != len) {
  475. qtest_log_send("b64write: data length mismatch (told %"PRIu64", "
  476. "found %zu)\n",
  477. len, out_len);
  478. out_len = MIN(out_len, len);
  479. }
  480. cpu_physical_memory_write(addr, data, out_len);
  481. qtest_send_prefix(chr);
  482. qtest_send(chr, "OK\n");
  483. } else if (strcmp(words[0], "endianness") == 0) {
  484. qtest_send_prefix(chr);
  485. #if defined(TARGET_WORDS_BIGENDIAN)
  486. qtest_sendf(chr, "OK big\n");
  487. #else
  488. qtest_sendf(chr, "OK little\n");
  489. #endif
  490. #ifdef TARGET_PPC64
  491. } else if (strcmp(words[0], "rtas") == 0) {
  492. uint64_t res, args, ret;
  493. unsigned long nargs, nret;
  494. g_assert(qemu_strtoul(words[2], NULL, 0, &nargs) == 0);
  495. g_assert(qemu_strtou64(words[3], NULL, 0, &args) == 0);
  496. g_assert(qemu_strtoul(words[4], NULL, 0, &nret) == 0);
  497. g_assert(qemu_strtou64(words[5], NULL, 0, &ret) == 0);
  498. res = qtest_rtas_call(words[1], nargs, args, nret, ret);
  499. qtest_send_prefix(chr);
  500. qtest_sendf(chr, "OK %"PRIu64"\n", res);
  501. #endif
  502. } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
  503. int64_t ns;
  504. if (words[1]) {
  505. g_assert(qemu_strtoi64(words[1], NULL, 0, &ns) == 0);
  506. } else {
  507. ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
  508. }
  509. qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
  510. qtest_send_prefix(chr);
  511. qtest_sendf(chr, "OK %"PRIi64"\n",
  512. (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
  513. } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
  514. int64_t ns;
  515. g_assert(words[1]);
  516. g_assert(qemu_strtoi64(words[1], NULL, 0, &ns) == 0);
  517. qtest_clock_warp(ns);
  518. qtest_send_prefix(chr);
  519. qtest_sendf(chr, "OK %"PRIi64"\n",
  520. (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
  521. } else {
  522. qtest_send_prefix(chr);
  523. qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
  524. }
  525. }
  526. static void qtest_process_inbuf(CharBackend *chr, GString *inbuf)
  527. {
  528. char *end;
  529. while ((end = strchr(inbuf->str, '\n')) != NULL) {
  530. size_t offset;
  531. GString *cmd;
  532. gchar **words;
  533. offset = end - inbuf->str;
  534. cmd = g_string_new_len(inbuf->str, offset);
  535. g_string_erase(inbuf, 0, offset + 1);
  536. words = g_strsplit(cmd->str, " ", 0);
  537. qtest_process_command(chr, words);
  538. g_strfreev(words);
  539. g_string_free(cmd, TRUE);
  540. }
  541. }
  542. static void qtest_read(void *opaque, const uint8_t *buf, int size)
  543. {
  544. CharBackend *chr = opaque;
  545. g_string_append_len(inbuf, (const gchar *)buf, size);
  546. qtest_process_inbuf(chr, inbuf);
  547. }
  548. static int qtest_can_read(void *opaque)
  549. {
  550. return 1024;
  551. }
  552. static void qtest_event(void *opaque, int event)
  553. {
  554. int i;
  555. switch (event) {
  556. case CHR_EVENT_OPENED:
  557. /*
  558. * We used to call qemu_system_reset() here, hoping we could
  559. * use the same process for multiple tests that way. Never
  560. * used. Injects an extra reset even when it's not used, and
  561. * that can mess up tests, e.g. -boot once.
  562. */
  563. for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
  564. irq_levels[i] = 0;
  565. }
  566. qemu_gettimeofday(&start_time);
  567. qtest_opened = true;
  568. if (qtest_log_fp) {
  569. fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
  570. (long) start_time.tv_sec, (long) start_time.tv_usec);
  571. }
  572. break;
  573. case CHR_EVENT_CLOSED:
  574. qtest_opened = false;
  575. if (qtest_log_fp) {
  576. qemu_timeval tv;
  577. qtest_get_time(&tv);
  578. fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
  579. (long) tv.tv_sec, (long) tv.tv_usec);
  580. }
  581. break;
  582. default:
  583. break;
  584. }
  585. }
  586. static int qtest_init_accel(MachineState *ms)
  587. {
  588. QemuOpts *opts = qemu_opts_create(qemu_find_opts("icount"), NULL, 0,
  589. &error_abort);
  590. qemu_opt_set(opts, "shift", "0", &error_abort);
  591. configure_icount(opts, &error_abort);
  592. qemu_opts_del(opts);
  593. return 0;
  594. }
  595. void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
  596. {
  597. Chardev *chr;
  598. chr = qemu_chr_new("qtest", qtest_chrdev);
  599. if (chr == NULL) {
  600. error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
  601. qtest_chrdev);
  602. return;
  603. }
  604. if (qtest_log) {
  605. if (strcmp(qtest_log, "none") != 0) {
  606. qtest_log_fp = fopen(qtest_log, "w+");
  607. }
  608. } else {
  609. qtest_log_fp = stderr;
  610. }
  611. qemu_chr_fe_init(&qtest_chr, chr, errp);
  612. qemu_chr_fe_set_handlers(&qtest_chr, qtest_can_read, qtest_read,
  613. qtest_event, &qtest_chr, NULL, true);
  614. qemu_chr_fe_set_echo(&qtest_chr, true);
  615. inbuf = g_string_new("");
  616. }
  617. bool qtest_driver(void)
  618. {
  619. return qtest_chr.chr != NULL;
  620. }
  621. static void qtest_accel_class_init(ObjectClass *oc, void *data)
  622. {
  623. AccelClass *ac = ACCEL_CLASS(oc);
  624. ac->name = "QTest";
  625. ac->available = qtest_available;
  626. ac->init_machine = qtest_init_accel;
  627. ac->allowed = &qtest_allowed;
  628. }
  629. #define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
  630. static const TypeInfo qtest_accel_type = {
  631. .name = TYPE_QTEST_ACCEL,
  632. .parent = TYPE_ACCEL,
  633. .class_init = qtest_accel_class_init,
  634. };
  635. static void qtest_type_init(void)
  636. {
  637. type_register_static(&qtest_accel_type);
  638. }
  639. type_init(qtest_type_init);