qemu-tech.texi 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371
  1. @node Implementation notes
  2. @appendix Implementation notes
  3. @menu
  4. * CPU emulation::
  5. * Translator Internals::
  6. * QEMU compared to other emulators::
  7. * Bibliography::
  8. @end menu
  9. @node CPU emulation
  10. @section CPU emulation
  11. @menu
  12. * x86:: x86 and x86-64 emulation
  13. * ARM:: ARM emulation
  14. * MIPS:: MIPS emulation
  15. * PPC:: PowerPC emulation
  16. * SPARC:: Sparc32 and Sparc64 emulation
  17. * Xtensa:: Xtensa emulation
  18. @end menu
  19. @node x86
  20. @subsection x86 and x86-64 emulation
  21. QEMU x86 target features:
  22. @itemize
  23. @item The virtual x86 CPU supports 16 bit and 32 bit addressing with segmentation.
  24. LDT/GDT and IDT are emulated. VM86 mode is also supported to run
  25. DOSEMU. There is some support for MMX/3DNow!, SSE, SSE2, SSE3, SSSE3,
  26. and SSE4 as well as x86-64 SVM.
  27. @item Support of host page sizes bigger than 4KB in user mode emulation.
  28. @item QEMU can emulate itself on x86.
  29. @item An extensive Linux x86 CPU test program is included @file{tests/test-i386}.
  30. It can be used to test other x86 virtual CPUs.
  31. @end itemize
  32. Current QEMU limitations:
  33. @itemize
  34. @item Limited x86-64 support.
  35. @item IPC syscalls are missing.
  36. @item The x86 segment limits and access rights are not tested at every
  37. memory access (yet). Hopefully, very few OSes seem to rely on that for
  38. normal use.
  39. @end itemize
  40. @node ARM
  41. @subsection ARM emulation
  42. @itemize
  43. @item Full ARM 7 user emulation.
  44. @item NWFPE FPU support included in user Linux emulation.
  45. @item Can run most ARM Linux binaries.
  46. @end itemize
  47. @node MIPS
  48. @subsection MIPS emulation
  49. @itemize
  50. @item The system emulation allows full MIPS32/MIPS64 Release 2 emulation,
  51. including privileged instructions, FPU and MMU, in both little and big
  52. endian modes.
  53. @item The Linux userland emulation can run many 32 bit MIPS Linux binaries.
  54. @end itemize
  55. Current QEMU limitations:
  56. @itemize
  57. @item Self-modifying code is not always handled correctly.
  58. @item 64 bit userland emulation is not implemented.
  59. @item The system emulation is not complete enough to run real firmware.
  60. @item The watchpoint debug facility is not implemented.
  61. @end itemize
  62. @node PPC
  63. @subsection PowerPC emulation
  64. @itemize
  65. @item Full PowerPC 32 bit emulation, including privileged instructions,
  66. FPU and MMU.
  67. @item Can run most PowerPC Linux binaries.
  68. @end itemize
  69. @node SPARC
  70. @subsection Sparc32 and Sparc64 emulation
  71. @itemize
  72. @item Full SPARC V8 emulation, including privileged
  73. instructions, FPU and MMU. SPARC V9 emulation includes most privileged
  74. and VIS instructions, FPU and I/D MMU. Alignment is fully enforced.
  75. @item Can run most 32-bit SPARC Linux binaries, SPARC32PLUS Linux binaries and
  76. some 64-bit SPARC Linux binaries.
  77. @end itemize
  78. Current QEMU limitations:
  79. @itemize
  80. @item IPC syscalls are missing.
  81. @item Floating point exception support is buggy.
  82. @item Atomic instructions are not correctly implemented.
  83. @item There are still some problems with Sparc64 emulators.
  84. @end itemize
  85. @node Xtensa
  86. @subsection Xtensa emulation
  87. @itemize
  88. @item Core Xtensa ISA emulation, including most options: code density,
  89. loop, extended L32R, 16- and 32-bit multiplication, 32-bit division,
  90. MAC16, miscellaneous operations, boolean, FP coprocessor, coprocessor
  91. context, debug, multiprocessor synchronization,
  92. conditional store, exceptions, relocatable vectors, unaligned exception,
  93. interrupts (including high priority and timer), hardware alignment,
  94. region protection, region translation, MMU, windowed registers, thread
  95. pointer, processor ID.
  96. @item Not implemented options: data/instruction cache (including cache
  97. prefetch and locking), XLMI, processor interface. Also options not
  98. covered by the core ISA (e.g. FLIX, wide branches) are not implemented.
  99. @item Can run most Xtensa Linux binaries.
  100. @item New core configuration that requires no additional instructions
  101. may be created from overlay with minimal amount of hand-written code.
  102. @end itemize
  103. @node Translator Internals
  104. @section Translator Internals
  105. QEMU is a dynamic translator. When it first encounters a piece of code,
  106. it converts it to the host instruction set. Usually dynamic translators
  107. are very complicated and highly CPU dependent. QEMU uses some tricks
  108. which make it relatively easily portable and simple while achieving good
  109. performances.
  110. QEMU's dynamic translation backend is called TCG, for "Tiny Code
  111. Generator". For more information, please take a look at @code{tcg/README}.
  112. Some notable features of QEMU's dynamic translator are:
  113. @table @strong
  114. @item CPU state optimisations:
  115. The target CPUs have many internal states which change the way it
  116. evaluates instructions. In order to achieve a good speed, the
  117. translation phase considers that some state information of the virtual
  118. CPU cannot change in it. The state is recorded in the Translation
  119. Block (TB). If the state changes (e.g. privilege level), a new TB will
  120. be generated and the previous TB won't be used anymore until the state
  121. matches the state recorded in the previous TB. The same idea can be applied
  122. to other aspects of the CPU state. For example, on x86, if the SS,
  123. DS and ES segments have a zero base, then the translator does not even
  124. generate an addition for the segment base.
  125. @item Direct block chaining:
  126. After each translated basic block is executed, QEMU uses the simulated
  127. Program Counter (PC) and other cpu state information (such as the CS
  128. segment base value) to find the next basic block.
  129. In order to accelerate the most common cases where the new simulated PC
  130. is known, QEMU can patch a basic block so that it jumps directly to the
  131. next one.
  132. The most portable code uses an indirect jump. An indirect jump makes
  133. it easier to make the jump target modification atomic. On some host
  134. architectures (such as x86 or PowerPC), the @code{JUMP} opcode is
  135. directly patched so that the block chaining has no overhead.
  136. @item Self-modifying code and translated code invalidation:
  137. Self-modifying code is a special challenge in x86 emulation because no
  138. instruction cache invalidation is signaled by the application when code
  139. is modified.
  140. User-mode emulation marks a host page as write-protected (if it is
  141. not already read-only) every time translated code is generated for a
  142. basic block. Then, if a write access is done to the page, Linux raises
  143. a SEGV signal. QEMU then invalidates all the translated code in the page
  144. and enables write accesses to the page. For system emulation, write
  145. protection is achieved through the software MMU.
  146. Correct translated code invalidation is done efficiently by maintaining
  147. a linked list of every translated block contained in a given page. Other
  148. linked lists are also maintained to undo direct block chaining.
  149. On RISC targets, correctly written software uses memory barriers and
  150. cache flushes, so some of the protection above would not be
  151. necessary. However, QEMU still requires that the generated code always
  152. matches the target instructions in memory in order to handle
  153. exceptions correctly.
  154. @item Exception support:
  155. longjmp() is used when an exception such as division by zero is
  156. encountered.
  157. The host SIGSEGV and SIGBUS signal handlers are used to get invalid
  158. memory accesses. QEMU keeps a map from host program counter to
  159. target program counter, and looks up where the exception happened
  160. based on the host program counter at the exception point.
  161. On some targets, some bits of the virtual CPU's state are not flushed to the
  162. memory until the end of the translation block. This is done for internal
  163. emulation state that is rarely accessed directly by the program and/or changes
  164. very often throughout the execution of a translation block---this includes
  165. condition codes on x86, delay slots on SPARC, conditional execution on
  166. ARM, and so on. This state is stored for each target instruction, and
  167. looked up on exceptions.
  168. @item MMU emulation:
  169. For system emulation QEMU uses a software MMU. In that mode, the MMU
  170. virtual to physical address translation is done at every memory
  171. access.
  172. QEMU uses an address translation cache (TLB) to speed up the translation.
  173. In order to avoid flushing the translated code each time the MMU
  174. mappings change, all caches in QEMU are physically indexed. This
  175. means that each basic block is indexed with its physical address.
  176. In order to avoid invalidating the basic block chain when MMU mappings
  177. change, chaining is only performed when the destination of the jump
  178. shares a page with the basic block that is performing the jump.
  179. The MMU can also distinguish RAM and ROM memory areas from MMIO memory
  180. areas. Access is faster for RAM and ROM because the translation cache also
  181. hosts the offset between guest address and host memory. Accessing MMIO
  182. memory areas instead calls out to C code for device emulation.
  183. Finally, the MMU helps tracking dirty pages and pages pointed to by
  184. translation blocks.
  185. @end table
  186. @node QEMU compared to other emulators
  187. @section QEMU compared to other emulators
  188. Like bochs [1], QEMU emulates an x86 CPU. But QEMU is much faster than
  189. bochs as it uses dynamic compilation. Bochs is closely tied to x86 PC
  190. emulation while QEMU can emulate several processors.
  191. Like Valgrind [2], QEMU does user space emulation and dynamic
  192. translation. Valgrind is mainly a memory debugger while QEMU has no
  193. support for it (QEMU could be used to detect out of bound memory
  194. accesses as Valgrind, but it has no support to track uninitialised data
  195. as Valgrind does). The Valgrind dynamic translator generates better code
  196. than QEMU (in particular it does register allocation) but it is closely
  197. tied to an x86 host and target and has no support for precise exceptions
  198. and system emulation.
  199. EM86 [3] is the closest project to user space QEMU (and QEMU still uses
  200. some of its code, in particular the ELF file loader). EM86 was limited
  201. to an alpha host and used a proprietary and slow interpreter (the
  202. interpreter part of the FX!32 Digital Win32 code translator [4]).
  203. TWIN from Willows Software was a Windows API emulator like Wine. It is less
  204. accurate than Wine but includes a protected mode x86 interpreter to launch
  205. x86 Windows executables. Such an approach has greater potential because most
  206. of the Windows API is executed natively but it is far more difficult to
  207. develop because all the data structures and function parameters exchanged
  208. between the API and the x86 code must be converted.
  209. User mode Linux [5] was the only solution before QEMU to launch a
  210. Linux kernel as a process while not needing any host kernel
  211. patches. However, user mode Linux requires heavy kernel patches while
  212. QEMU accepts unpatched Linux kernels. The price to pay is that QEMU is
  213. slower.
  214. The Plex86 [6] PC virtualizer is done in the same spirit as the now
  215. obsolete qemu-fast system emulator. It requires a patched Linux kernel
  216. to work (you cannot launch the same kernel on your PC), but the
  217. patches are really small. As it is a PC virtualizer (no emulation is
  218. done except for some privileged instructions), it has the potential of
  219. being faster than QEMU. The downside is that a complicated (and
  220. potentially unsafe) host kernel patch is needed.
  221. The commercial PC Virtualizers (VMWare [7], VirtualPC [8]) are faster
  222. than QEMU (without virtualization), but they all need specific, proprietary
  223. and potentially unsafe host drivers. Moreover, they are unable to
  224. provide cycle exact simulation as an emulator can.
  225. VirtualBox [9], Xen [10] and KVM [11] are based on QEMU. QEMU-SystemC
  226. [12] uses QEMU to simulate a system where some hardware devices are
  227. developed in SystemC.
  228. @node Bibliography
  229. @section Bibliography
  230. @table @asis
  231. @item [1]
  232. @url{http://bochs.sourceforge.net/}, the Bochs IA-32 Emulator Project,
  233. by Kevin Lawton et al.
  234. @item [2]
  235. @url{http://www.valgrind.org/}, Valgrind, an open-source memory debugger
  236. for GNU/Linux.
  237. @item [3]
  238. @url{http://ftp.dreamtime.org/pub/linux/Linux-Alpha/em86/v0.2/docs/em86.html},
  239. the EM86 x86 emulator on Alpha-Linux.
  240. @item [4]
  241. @url{http://www.usenix.org/publications/library/proceedings/usenix-nt97/@/full_papers/chernoff/chernoff.pdf},
  242. DIGITAL FX!32: Running 32-Bit x86 Applications on Alpha NT, by Anton
  243. Chernoff and Ray Hookway.
  244. @item [5]
  245. @url{http://user-mode-linux.sourceforge.net/},
  246. The User-mode Linux Kernel.
  247. @item [6]
  248. @url{http://www.plex86.org/},
  249. The new Plex86 project.
  250. @item [7]
  251. @url{http://www.vmware.com/},
  252. The VMWare PC virtualizer.
  253. @item [8]
  254. @url{https://www.microsoft.com/download/details.aspx?id=3702},
  255. The VirtualPC PC virtualizer.
  256. @item [9]
  257. @url{http://virtualbox.org/},
  258. The VirtualBox PC virtualizer.
  259. @item [10]
  260. @url{http://www.xen.org/},
  261. The Xen hypervisor.
  262. @item [11]
  263. @url{http://www.linux-kvm.org/},
  264. Kernel Based Virtual Machine (KVM).
  265. @item [12]
  266. @url{http://www.greensocs.com/projects/QEMUSystemC},
  267. QEMU-SystemC, a hardware co-simulator.
  268. @end table