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qtest.c 14 KB

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  1. /*
  2. * Test Server
  3. *
  4. * Copyright IBM, Corp. 2011
  5. *
  6. * Authors:
  7. * Anthony Liguori <aliguori@us.ibm.com>
  8. *
  9. * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10. * See the COPYING file in the top-level directory.
  11. *
  12. */
  13. #include "sysemu/qtest.h"
  14. #include "hw/qdev.h"
  15. #include "sysemu/char.h"
  16. #include "exec/ioport.h"
  17. #include "exec/memory.h"
  18. #include "hw/irq.h"
  19. #include "sysemu/sysemu.h"
  20. #include "sysemu/cpus.h"
  21. #define MAX_IRQ 256
  22. bool qtest_allowed;
  23. static DeviceState *irq_intercept_dev;
  24. static FILE *qtest_log_fp;
  25. static CharDriverState *qtest_chr;
  26. static GString *inbuf;
  27. static int irq_levels[MAX_IRQ];
  28. static qemu_timeval start_time;
  29. static bool qtest_opened;
  30. #define FMT_timeval "%ld.%06ld"
  31. /**
  32. * QTest Protocol
  33. *
  34. * Line based protocol, request/response based. Server can send async messages
  35. * so clients should always handle many async messages before the response
  36. * comes in.
  37. *
  38. * Valid requests
  39. *
  40. * Clock management:
  41. *
  42. * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
  43. * let you adjust the value of the clock (monotonically). All the commands
  44. * return the current value of the clock in nanoseconds.
  45. *
  46. * > clock_step
  47. * < OK VALUE
  48. *
  49. * Advance the clock to the next deadline. Useful when waiting for
  50. * asynchronous events.
  51. *
  52. * > clock_step NS
  53. * < OK VALUE
  54. *
  55. * Advance the clock by NS nanoseconds.
  56. *
  57. * > clock_set NS
  58. * < OK VALUE
  59. *
  60. * Advance the clock to NS nanoseconds (do nothing if it's already past).
  61. *
  62. * PIO and memory access:
  63. *
  64. * > outb ADDR VALUE
  65. * < OK
  66. *
  67. * > outw ADDR VALUE
  68. * < OK
  69. *
  70. * > outl ADDR VALUE
  71. * < OK
  72. *
  73. * > inb ADDR
  74. * < OK VALUE
  75. *
  76. * > inw ADDR
  77. * < OK VALUE
  78. *
  79. * > inl ADDR
  80. * < OK VALUE
  81. *
  82. * > writeb ADDR VALUE
  83. * < OK
  84. *
  85. * > writew ADDR VALUE
  86. * < OK
  87. *
  88. * > writel ADDR VALUE
  89. * < OK
  90. *
  91. * > writeq ADDR VALUE
  92. * < OK
  93. *
  94. * > readb ADDR
  95. * < OK VALUE
  96. *
  97. * > readw ADDR
  98. * < OK VALUE
  99. *
  100. * > readl ADDR
  101. * < OK VALUE
  102. *
  103. * > readq ADDR
  104. * < OK VALUE
  105. *
  106. * > read ADDR SIZE
  107. * < OK DATA
  108. *
  109. * > write ADDR SIZE DATA
  110. * < OK
  111. *
  112. * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
  113. *
  114. * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
  115. * than the expected size, the value will be zero filled at the end of the data
  116. * sequence.
  117. *
  118. * IRQ management:
  119. *
  120. * > irq_intercept_in QOM-PATH
  121. * < OK
  122. *
  123. * > irq_intercept_out QOM-PATH
  124. * < OK
  125. *
  126. * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
  127. * QOM-PATH. When the pin is triggered, one of the following async messages
  128. * will be printed to the qtest stream:
  129. *
  130. * IRQ raise NUM
  131. * IRQ lower NUM
  132. *
  133. * where NUM is an IRQ number. For the PC, interrupts can be intercepted
  134. * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
  135. * NUM=0 even though it is remapped to GSI 2).
  136. */
  137. static int hex2nib(char ch)
  138. {
  139. if (ch >= '0' && ch <= '9') {
  140. return ch - '0';
  141. } else if (ch >= 'a' && ch <= 'f') {
  142. return 10 + (ch - 'a');
  143. } else if (ch >= 'A' && ch <= 'F') {
  144. return 10 + (ch - 'A');
  145. } else {
  146. return -1;
  147. }
  148. }
  149. static void qtest_get_time(qemu_timeval *tv)
  150. {
  151. qemu_gettimeofday(tv);
  152. tv->tv_sec -= start_time.tv_sec;
  153. tv->tv_usec -= start_time.tv_usec;
  154. if (tv->tv_usec < 0) {
  155. tv->tv_usec += 1000000;
  156. tv->tv_sec -= 1;
  157. }
  158. }
  159. static void qtest_send_prefix(CharDriverState *chr)
  160. {
  161. qemu_timeval tv;
  162. if (!qtest_log_fp || !qtest_opened) {
  163. return;
  164. }
  165. qtest_get_time(&tv);
  166. fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
  167. (long) tv.tv_sec, (long) tv.tv_usec);
  168. }
  169. static void GCC_FMT_ATTR(2, 3) qtest_send(CharDriverState *chr,
  170. const char *fmt, ...)
  171. {
  172. va_list ap;
  173. char buffer[1024];
  174. size_t len;
  175. va_start(ap, fmt);
  176. len = vsnprintf(buffer, sizeof(buffer), fmt, ap);
  177. va_end(ap);
  178. qemu_chr_fe_write_all(chr, (uint8_t *)buffer, len);
  179. if (qtest_log_fp && qtest_opened) {
  180. fprintf(qtest_log_fp, "%s", buffer);
  181. }
  182. }
  183. static void qtest_irq_handler(void *opaque, int n, int level)
  184. {
  185. qemu_irq *old_irqs = opaque;
  186. qemu_set_irq(old_irqs[n], level);
  187. if (irq_levels[n] != level) {
  188. CharDriverState *chr = qtest_chr;
  189. irq_levels[n] = level;
  190. qtest_send_prefix(chr);
  191. qtest_send(chr, "IRQ %s %d\n",
  192. level ? "raise" : "lower", n);
  193. }
  194. }
  195. static void qtest_process_command(CharDriverState *chr, gchar **words)
  196. {
  197. const gchar *command;
  198. g_assert(words);
  199. command = words[0];
  200. if (qtest_log_fp) {
  201. qemu_timeval tv;
  202. int i;
  203. qtest_get_time(&tv);
  204. fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
  205. (long) tv.tv_sec, (long) tv.tv_usec);
  206. for (i = 0; words[i]; i++) {
  207. fprintf(qtest_log_fp, " %s", words[i]);
  208. }
  209. fprintf(qtest_log_fp, "\n");
  210. }
  211. g_assert(command);
  212. if (strcmp(words[0], "irq_intercept_out") == 0
  213. || strcmp(words[0], "irq_intercept_in") == 0) {
  214. DeviceState *dev;
  215. NamedGPIOList *ngl;
  216. g_assert(words[1]);
  217. dev = DEVICE(object_resolve_path(words[1], NULL));
  218. if (!dev) {
  219. qtest_send_prefix(chr);
  220. qtest_send(chr, "FAIL Unknown device\n");
  221. return;
  222. }
  223. if (irq_intercept_dev) {
  224. qtest_send_prefix(chr);
  225. if (irq_intercept_dev != dev) {
  226. qtest_send(chr, "FAIL IRQ intercept already enabled\n");
  227. } else {
  228. qtest_send(chr, "OK\n");
  229. }
  230. return;
  231. }
  232. QLIST_FOREACH(ngl, &dev->gpios, node) {
  233. /* We don't support intercept of named GPIOs yet */
  234. if (ngl->name) {
  235. continue;
  236. }
  237. if (words[0][14] == 'o') {
  238. qemu_irq_intercept_out(&ngl->out, qtest_irq_handler,
  239. ngl->num_out);
  240. } else {
  241. qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
  242. ngl->num_in);
  243. }
  244. }
  245. irq_intercept_dev = dev;
  246. qtest_send_prefix(chr);
  247. qtest_send(chr, "OK\n");
  248. } else if (strcmp(words[0], "outb") == 0 ||
  249. strcmp(words[0], "outw") == 0 ||
  250. strcmp(words[0], "outl") == 0) {
  251. uint16_t addr;
  252. uint32_t value;
  253. g_assert(words[1] && words[2]);
  254. addr = strtoul(words[1], NULL, 0);
  255. value = strtoul(words[2], NULL, 0);
  256. if (words[0][3] == 'b') {
  257. cpu_outb(addr, value);
  258. } else if (words[0][3] == 'w') {
  259. cpu_outw(addr, value);
  260. } else if (words[0][3] == 'l') {
  261. cpu_outl(addr, value);
  262. }
  263. qtest_send_prefix(chr);
  264. qtest_send(chr, "OK\n");
  265. } else if (strcmp(words[0], "inb") == 0 ||
  266. strcmp(words[0], "inw") == 0 ||
  267. strcmp(words[0], "inl") == 0) {
  268. uint16_t addr;
  269. uint32_t value = -1U;
  270. g_assert(words[1]);
  271. addr = strtoul(words[1], NULL, 0);
  272. if (words[0][2] == 'b') {
  273. value = cpu_inb(addr);
  274. } else if (words[0][2] == 'w') {
  275. value = cpu_inw(addr);
  276. } else if (words[0][2] == 'l') {
  277. value = cpu_inl(addr);
  278. }
  279. qtest_send_prefix(chr);
  280. qtest_send(chr, "OK 0x%04x\n", value);
  281. } else if (strcmp(words[0], "writeb") == 0 ||
  282. strcmp(words[0], "writew") == 0 ||
  283. strcmp(words[0], "writel") == 0 ||
  284. strcmp(words[0], "writeq") == 0) {
  285. uint64_t addr;
  286. uint64_t value;
  287. g_assert(words[1] && words[2]);
  288. addr = strtoull(words[1], NULL, 0);
  289. value = strtoull(words[2], NULL, 0);
  290. if (words[0][5] == 'b') {
  291. uint8_t data = value;
  292. cpu_physical_memory_write(addr, &data, 1);
  293. } else if (words[0][5] == 'w') {
  294. uint16_t data = value;
  295. tswap16s(&data);
  296. cpu_physical_memory_write(addr, &data, 2);
  297. } else if (words[0][5] == 'l') {
  298. uint32_t data = value;
  299. tswap32s(&data);
  300. cpu_physical_memory_write(addr, &data, 4);
  301. } else if (words[0][5] == 'q') {
  302. uint64_t data = value;
  303. tswap64s(&data);
  304. cpu_physical_memory_write(addr, &data, 8);
  305. }
  306. qtest_send_prefix(chr);
  307. qtest_send(chr, "OK\n");
  308. } else if (strcmp(words[0], "readb") == 0 ||
  309. strcmp(words[0], "readw") == 0 ||
  310. strcmp(words[0], "readl") == 0 ||
  311. strcmp(words[0], "readq") == 0) {
  312. uint64_t addr;
  313. uint64_t value = UINT64_C(-1);
  314. g_assert(words[1]);
  315. addr = strtoull(words[1], NULL, 0);
  316. if (words[0][4] == 'b') {
  317. uint8_t data;
  318. cpu_physical_memory_read(addr, &data, 1);
  319. value = data;
  320. } else if (words[0][4] == 'w') {
  321. uint16_t data;
  322. cpu_physical_memory_read(addr, &data, 2);
  323. value = tswap16(data);
  324. } else if (words[0][4] == 'l') {
  325. uint32_t data;
  326. cpu_physical_memory_read(addr, &data, 4);
  327. value = tswap32(data);
  328. } else if (words[0][4] == 'q') {
  329. cpu_physical_memory_read(addr, &value, 8);
  330. tswap64s(&value);
  331. }
  332. qtest_send_prefix(chr);
  333. qtest_send(chr, "OK 0x%016" PRIx64 "\n", value);
  334. } else if (strcmp(words[0], "read") == 0) {
  335. uint64_t addr, len, i;
  336. uint8_t *data;
  337. g_assert(words[1] && words[2]);
  338. addr = strtoull(words[1], NULL, 0);
  339. len = strtoull(words[2], NULL, 0);
  340. data = g_malloc(len);
  341. cpu_physical_memory_read(addr, data, len);
  342. qtest_send_prefix(chr);
  343. qtest_send(chr, "OK 0x");
  344. for (i = 0; i < len; i++) {
  345. qtest_send(chr, "%02x", data[i]);
  346. }
  347. qtest_send(chr, "\n");
  348. g_free(data);
  349. } else if (strcmp(words[0], "write") == 0) {
  350. uint64_t addr, len, i;
  351. uint8_t *data;
  352. size_t data_len;
  353. g_assert(words[1] && words[2] && words[3]);
  354. addr = strtoull(words[1], NULL, 0);
  355. len = strtoull(words[2], NULL, 0);
  356. data_len = strlen(words[3]);
  357. if (data_len < 3) {
  358. qtest_send(chr, "ERR invalid argument size\n");
  359. return;
  360. }
  361. data = g_malloc(len);
  362. for (i = 0; i < len; i++) {
  363. if ((i * 2 + 4) <= data_len) {
  364. data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
  365. data[i] |= hex2nib(words[3][i * 2 + 3]);
  366. } else {
  367. data[i] = 0;
  368. }
  369. }
  370. cpu_physical_memory_write(addr, data, len);
  371. g_free(data);
  372. qtest_send_prefix(chr);
  373. qtest_send(chr, "OK\n");
  374. } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
  375. int64_t ns;
  376. if (words[1]) {
  377. ns = strtoll(words[1], NULL, 0);
  378. } else {
  379. ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
  380. }
  381. qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
  382. qtest_send_prefix(chr);
  383. qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
  384. } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
  385. int64_t ns;
  386. g_assert(words[1]);
  387. ns = strtoll(words[1], NULL, 0);
  388. qtest_clock_warp(ns);
  389. qtest_send_prefix(chr);
  390. qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
  391. } else {
  392. qtest_send_prefix(chr);
  393. qtest_send(chr, "FAIL Unknown command `%s'\n", words[0]);
  394. }
  395. }
  396. static void qtest_process_inbuf(CharDriverState *chr, GString *inbuf)
  397. {
  398. char *end;
  399. while ((end = strchr(inbuf->str, '\n')) != NULL) {
  400. size_t offset;
  401. GString *cmd;
  402. gchar **words;
  403. offset = end - inbuf->str;
  404. cmd = g_string_new_len(inbuf->str, offset);
  405. g_string_erase(inbuf, 0, offset + 1);
  406. words = g_strsplit(cmd->str, " ", 0);
  407. qtest_process_command(chr, words);
  408. g_strfreev(words);
  409. g_string_free(cmd, TRUE);
  410. }
  411. }
  412. static void qtest_read(void *opaque, const uint8_t *buf, int size)
  413. {
  414. CharDriverState *chr = opaque;
  415. g_string_append_len(inbuf, (const gchar *)buf, size);
  416. qtest_process_inbuf(chr, inbuf);
  417. }
  418. static int qtest_can_read(void *opaque)
  419. {
  420. return 1024;
  421. }
  422. static void qtest_event(void *opaque, int event)
  423. {
  424. int i;
  425. switch (event) {
  426. case CHR_EVENT_OPENED:
  427. /*
  428. * We used to call qemu_system_reset() here, hoping we could
  429. * use the same process for multiple tests that way. Never
  430. * used. Injects an extra reset even when it's not used, and
  431. * that can mess up tests, e.g. -boot once.
  432. */
  433. for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
  434. irq_levels[i] = 0;
  435. }
  436. qemu_gettimeofday(&start_time);
  437. qtest_opened = true;
  438. if (qtest_log_fp) {
  439. fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
  440. (long) start_time.tv_sec, (long) start_time.tv_usec);
  441. }
  442. break;
  443. case CHR_EVENT_CLOSED:
  444. qtest_opened = false;
  445. if (qtest_log_fp) {
  446. qemu_timeval tv;
  447. qtest_get_time(&tv);
  448. fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
  449. (long) tv.tv_sec, (long) tv.tv_usec);
  450. }
  451. break;
  452. default:
  453. break;
  454. }
  455. }
  456. int qtest_init_accel(MachineClass *mc)
  457. {
  458. configure_icount("0");
  459. return 0;
  460. }
  461. void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
  462. {
  463. CharDriverState *chr;
  464. chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
  465. if (chr == NULL) {
  466. error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
  467. qtest_chrdev);
  468. return;
  469. }
  470. qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
  471. qemu_chr_fe_set_echo(chr, true);
  472. inbuf = g_string_new("");
  473. if (qtest_log) {
  474. if (strcmp(qtest_log, "none") != 0) {
  475. qtest_log_fp = fopen(qtest_log, "w+");
  476. }
  477. } else {
  478. qtest_log_fp = stderr;
  479. }
  480. qtest_chr = chr;
  481. }
  482. bool qtest_driver(void)
  483. {
  484. return qtest_chr;
  485. }