xen_platform.c 12 KB

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  1. /*
  2. * XEN platform pci device, formerly known as the event channel device
  3. *
  4. * Copyright (c) 2003-2004 Intel Corp.
  5. * Copyright (c) 2006 XenSource
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy
  8. * of this software and associated documentation files (the "Software"), to deal
  9. * in the Software without restriction, including without limitation the rights
  10. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11. * copies of the Software, and to permit persons to whom the Software is
  12. * furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23. * THE SOFTWARE.
  24. */
  25. #include <assert.h>
  26. #include "hw/hw.h"
  27. #include "hw/i386/pc.h"
  28. #include "hw/ide.h"
  29. #include "hw/pci/pci.h"
  30. #include "hw/irq.h"
  31. #include "hw/xen/xen_common.h"
  32. #include "hw/xen/xen_backend.h"
  33. #include "trace.h"
  34. #include "exec/address-spaces.h"
  35. #include <xenguest.h>
  36. //#define DEBUG_PLATFORM
  37. #ifdef DEBUG_PLATFORM
  38. #define DPRINTF(fmt, ...) do { \
  39. fprintf(stderr, "xen_platform: " fmt, ## __VA_ARGS__); \
  40. } while (0)
  41. #else
  42. #define DPRINTF(fmt, ...) do { } while (0)
  43. #endif
  44. #define PFFLAG_ROM_LOCK 1 /* Sets whether ROM memory area is RW or RO */
  45. typedef struct PCIXenPlatformState {
  46. /*< private >*/
  47. PCIDevice parent_obj;
  48. /*< public >*/
  49. MemoryRegion fixed_io;
  50. MemoryRegion bar;
  51. MemoryRegion mmio_bar;
  52. uint8_t flags; /* used only for version_id == 2 */
  53. int drivers_blacklisted;
  54. uint16_t driver_product_version;
  55. /* Log from guest drivers */
  56. char log_buffer[4096];
  57. int log_buffer_off;
  58. } PCIXenPlatformState;
  59. #define TYPE_XEN_PLATFORM "xen-platform"
  60. #define XEN_PLATFORM(obj) \
  61. OBJECT_CHECK(PCIXenPlatformState, (obj), TYPE_XEN_PLATFORM)
  62. #define XEN_PLATFORM_IOPORT 0x10
  63. /* Send bytes to syslog */
  64. static void log_writeb(PCIXenPlatformState *s, char val)
  65. {
  66. if (val == '\n' || s->log_buffer_off == sizeof(s->log_buffer) - 1) {
  67. /* Flush buffer */
  68. s->log_buffer[s->log_buffer_off] = 0;
  69. trace_xen_platform_log(s->log_buffer);
  70. s->log_buffer_off = 0;
  71. } else {
  72. s->log_buffer[s->log_buffer_off++] = val;
  73. }
  74. }
  75. /* Xen Platform, Fixed IOPort */
  76. #define UNPLUG_ALL_IDE_DISKS 1
  77. #define UNPLUG_ALL_NICS 2
  78. #define UNPLUG_AUX_IDE_DISKS 4
  79. static void unplug_nic(PCIBus *b, PCIDevice *d, void *o)
  80. {
  81. /* We have to ignore passthrough devices */
  82. if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
  83. PCI_CLASS_NETWORK_ETHERNET
  84. && strcmp(d->name, "xen-pci-passthrough") != 0) {
  85. object_unparent(OBJECT(d));
  86. }
  87. }
  88. static void pci_unplug_nics(PCIBus *bus)
  89. {
  90. pci_for_each_device(bus, 0, unplug_nic, NULL);
  91. }
  92. static void unplug_disks(PCIBus *b, PCIDevice *d, void *o)
  93. {
  94. /* We have to ignore passthrough devices */
  95. if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
  96. PCI_CLASS_STORAGE_IDE
  97. && strcmp(d->name, "xen-pci-passthrough") != 0) {
  98. pci_piix3_xen_ide_unplug(DEVICE(d));
  99. }
  100. }
  101. static void pci_unplug_disks(PCIBus *bus)
  102. {
  103. pci_for_each_device(bus, 0, unplug_disks, NULL);
  104. }
  105. static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
  106. {
  107. PCIXenPlatformState *s = opaque;
  108. switch (addr) {
  109. case 0: {
  110. PCIDevice *pci_dev = PCI_DEVICE(s);
  111. /* Unplug devices. Value is a bitmask of which devices to
  112. unplug, with bit 0 the IDE devices, bit 1 the network
  113. devices, and bit 2 the non-primary-master IDE devices. */
  114. if (val & UNPLUG_ALL_IDE_DISKS) {
  115. DPRINTF("unplug disks\n");
  116. bdrv_drain_all();
  117. bdrv_flush_all();
  118. pci_unplug_disks(pci_dev->bus);
  119. }
  120. if (val & UNPLUG_ALL_NICS) {
  121. DPRINTF("unplug nics\n");
  122. pci_unplug_nics(pci_dev->bus);
  123. }
  124. if (val & UNPLUG_AUX_IDE_DISKS) {
  125. DPRINTF("unplug auxiliary disks not supported\n");
  126. }
  127. break;
  128. }
  129. case 2:
  130. switch (val) {
  131. case 1:
  132. DPRINTF("Citrix Windows PV drivers loaded in guest\n");
  133. break;
  134. case 0:
  135. DPRINTF("Guest claimed to be running PV product 0?\n");
  136. break;
  137. default:
  138. DPRINTF("Unknown PV product %d loaded in guest\n", val);
  139. break;
  140. }
  141. s->driver_product_version = val;
  142. break;
  143. }
  144. }
  145. static void platform_fixed_ioport_writel(void *opaque, uint32_t addr,
  146. uint32_t val)
  147. {
  148. switch (addr) {
  149. case 0:
  150. /* PV driver version */
  151. break;
  152. }
  153. }
  154. static void platform_fixed_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
  155. {
  156. PCIXenPlatformState *s = opaque;
  157. switch (addr) {
  158. case 0: /* Platform flags */ {
  159. hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
  160. HVMMEM_ram_ro : HVMMEM_ram_rw;
  161. if (xc_hvm_set_mem_type(xen_xc, xen_domid, mem_type, 0xc0, 0x40)) {
  162. DPRINTF("unable to change ro/rw state of ROM memory area!\n");
  163. } else {
  164. s->flags = val & PFFLAG_ROM_LOCK;
  165. DPRINTF("changed ro/rw state of ROM memory area. now is %s state.\n",
  166. (mem_type == HVMMEM_ram_ro ? "ro":"rw"));
  167. }
  168. break;
  169. }
  170. case 2:
  171. log_writeb(s, val);
  172. break;
  173. }
  174. }
  175. static uint32_t platform_fixed_ioport_readw(void *opaque, uint32_t addr)
  176. {
  177. PCIXenPlatformState *s = opaque;
  178. switch (addr) {
  179. case 0:
  180. if (s->drivers_blacklisted) {
  181. /* The drivers will recognise this magic number and refuse
  182. * to do anything. */
  183. return 0xd249;
  184. } else {
  185. /* Magic value so that you can identify the interface. */
  186. return 0x49d2;
  187. }
  188. default:
  189. return 0xffff;
  190. }
  191. }
  192. static uint32_t platform_fixed_ioport_readb(void *opaque, uint32_t addr)
  193. {
  194. PCIXenPlatformState *s = opaque;
  195. switch (addr) {
  196. case 0:
  197. /* Platform flags */
  198. return s->flags;
  199. case 2:
  200. /* Version number */
  201. return 1;
  202. default:
  203. return 0xff;
  204. }
  205. }
  206. static void platform_fixed_ioport_reset(void *opaque)
  207. {
  208. PCIXenPlatformState *s = opaque;
  209. platform_fixed_ioport_writeb(s, 0, 0);
  210. }
  211. static uint64_t platform_fixed_ioport_read(void *opaque,
  212. hwaddr addr,
  213. unsigned size)
  214. {
  215. switch (size) {
  216. case 1:
  217. return platform_fixed_ioport_readb(opaque, addr);
  218. case 2:
  219. return platform_fixed_ioport_readw(opaque, addr);
  220. default:
  221. return -1;
  222. }
  223. }
  224. static void platform_fixed_ioport_write(void *opaque, hwaddr addr,
  225. uint64_t val, unsigned size)
  226. {
  227. switch (size) {
  228. case 1:
  229. platform_fixed_ioport_writeb(opaque, addr, val);
  230. break;
  231. case 2:
  232. platform_fixed_ioport_writew(opaque, addr, val);
  233. break;
  234. case 4:
  235. platform_fixed_ioport_writel(opaque, addr, val);
  236. break;
  237. }
  238. }
  239. static const MemoryRegionOps platform_fixed_io_ops = {
  240. .read = platform_fixed_ioport_read,
  241. .write = platform_fixed_ioport_write,
  242. .valid = {
  243. .unaligned = true,
  244. },
  245. .impl = {
  246. .min_access_size = 1,
  247. .max_access_size = 4,
  248. .unaligned = true,
  249. },
  250. .endianness = DEVICE_LITTLE_ENDIAN,
  251. };
  252. static void platform_fixed_ioport_init(PCIXenPlatformState* s)
  253. {
  254. memory_region_init_io(&s->fixed_io, OBJECT(s), &platform_fixed_io_ops, s,
  255. "xen-fixed", 16);
  256. memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
  257. &s->fixed_io);
  258. }
  259. /* Xen Platform PCI Device */
  260. static uint64_t xen_platform_ioport_readb(void *opaque, hwaddr addr,
  261. unsigned int size)
  262. {
  263. if (addr == 0) {
  264. return platform_fixed_ioport_readb(opaque, 0);
  265. } else {
  266. return ~0u;
  267. }
  268. }
  269. static void xen_platform_ioport_writeb(void *opaque, hwaddr addr,
  270. uint64_t val, unsigned int size)
  271. {
  272. PCIXenPlatformState *s = opaque;
  273. switch (addr) {
  274. case 0: /* Platform flags */
  275. platform_fixed_ioport_writeb(opaque, 0, (uint32_t)val);
  276. break;
  277. case 8:
  278. log_writeb(s, (uint32_t)val);
  279. break;
  280. default:
  281. break;
  282. }
  283. }
  284. static const MemoryRegionOps xen_pci_io_ops = {
  285. .read = xen_platform_ioport_readb,
  286. .write = xen_platform_ioport_writeb,
  287. .impl.min_access_size = 1,
  288. .impl.max_access_size = 1,
  289. };
  290. static void platform_ioport_bar_setup(PCIXenPlatformState *d)
  291. {
  292. memory_region_init_io(&d->bar, OBJECT(d), &xen_pci_io_ops, d,
  293. "xen-pci", 0x100);
  294. }
  295. static uint64_t platform_mmio_read(void *opaque, hwaddr addr,
  296. unsigned size)
  297. {
  298. DPRINTF("Warning: attempted read from physical address "
  299. "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
  300. return 0;
  301. }
  302. static void platform_mmio_write(void *opaque, hwaddr addr,
  303. uint64_t val, unsigned size)
  304. {
  305. DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
  306. "address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
  307. val, addr);
  308. }
  309. static const MemoryRegionOps platform_mmio_handler = {
  310. .read = &platform_mmio_read,
  311. .write = &platform_mmio_write,
  312. .endianness = DEVICE_NATIVE_ENDIAN,
  313. };
  314. static void platform_mmio_setup(PCIXenPlatformState *d)
  315. {
  316. memory_region_init_io(&d->mmio_bar, OBJECT(d), &platform_mmio_handler, d,
  317. "xen-mmio", 0x1000000);
  318. }
  319. static int xen_platform_post_load(void *opaque, int version_id)
  320. {
  321. PCIXenPlatformState *s = opaque;
  322. platform_fixed_ioport_writeb(s, 0, s->flags);
  323. return 0;
  324. }
  325. static const VMStateDescription vmstate_xen_platform = {
  326. .name = "platform",
  327. .version_id = 4,
  328. .minimum_version_id = 4,
  329. .minimum_version_id_old = 4,
  330. .post_load = xen_platform_post_load,
  331. .fields = (VMStateField []) {
  332. VMSTATE_PCI_DEVICE(parent_obj, PCIXenPlatformState),
  333. VMSTATE_UINT8(flags, PCIXenPlatformState),
  334. VMSTATE_END_OF_LIST()
  335. }
  336. };
  337. static int xen_platform_initfn(PCIDevice *dev)
  338. {
  339. PCIXenPlatformState *d = XEN_PLATFORM(dev);
  340. uint8_t *pci_conf;
  341. pci_conf = dev->config;
  342. pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
  343. pci_config_set_prog_interface(pci_conf, 0);
  344. pci_conf[PCI_INTERRUPT_PIN] = 1;
  345. platform_ioport_bar_setup(d);
  346. pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
  347. /* reserve 16MB mmio address for share memory*/
  348. platform_mmio_setup(d);
  349. pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
  350. &d->mmio_bar);
  351. platform_fixed_ioport_init(d);
  352. return 0;
  353. }
  354. static void platform_reset(DeviceState *dev)
  355. {
  356. PCIXenPlatformState *s = XEN_PLATFORM(dev);
  357. platform_fixed_ioport_reset(s);
  358. }
  359. static void xen_platform_class_init(ObjectClass *klass, void *data)
  360. {
  361. DeviceClass *dc = DEVICE_CLASS(klass);
  362. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  363. k->init = xen_platform_initfn;
  364. k->vendor_id = PCI_VENDOR_ID_XEN;
  365. k->device_id = PCI_DEVICE_ID_XEN_PLATFORM;
  366. k->class_id = PCI_CLASS_OTHERS << 8 | 0x80;
  367. k->subsystem_vendor_id = PCI_VENDOR_ID_XEN;
  368. k->subsystem_id = PCI_DEVICE_ID_XEN_PLATFORM;
  369. k->revision = 1;
  370. set_bit(DEVICE_CATEGORY_MISC, dc->categories);
  371. dc->desc = "XEN platform pci device";
  372. dc->reset = platform_reset;
  373. dc->vmsd = &vmstate_xen_platform;
  374. }
  375. static const TypeInfo xen_platform_info = {
  376. .name = TYPE_XEN_PLATFORM,
  377. .parent = TYPE_PCI_DEVICE,
  378. .instance_size = sizeof(PCIXenPlatformState),
  379. .class_init = xen_platform_class_init,
  380. };
  381. static void xen_platform_register_types(void)
  382. {
  383. type_register_static(&xen_platform_info);
  384. }
  385. type_init(xen_platform_register_types)