digic-timer.c 4.3 KB

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  1. /*
  2. * QEMU model of the Canon DIGIC timer block.
  3. *
  4. * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
  5. *
  6. * This model is based on reverse engineering efforts
  7. * made by CHDK (http://chdk.wikia.com) and
  8. * Magic Lantern (http://www.magiclantern.fm) projects
  9. * contributors.
  10. *
  11. * See "Timer/Clock Module" docs here:
  12. * http://magiclantern.wikia.com/wiki/Register_Map
  13. *
  14. * The QEMU model of the OSTimer in PKUnity SoC by Guan Xuetao
  15. * is used as a template.
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License as published by
  19. * the Free Software Foundation; either version 2 of the License, or
  20. * (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. */
  28. #include "hw/sysbus.h"
  29. #include "hw/ptimer.h"
  30. #include "qemu/main-loop.h"
  31. #include "hw/timer/digic-timer.h"
  32. static const VMStateDescription vmstate_digic_timer = {
  33. .name = "digic.timer",
  34. .version_id = 1,
  35. .minimum_version_id = 1,
  36. .minimum_version_id_old = 1,
  37. .fields = (VMStateField[]) {
  38. VMSTATE_PTIMER(ptimer, DigicTimerState),
  39. VMSTATE_UINT32(control, DigicTimerState),
  40. VMSTATE_UINT32(relvalue, DigicTimerState),
  41. VMSTATE_END_OF_LIST()
  42. }
  43. };
  44. static void digic_timer_reset(DeviceState *dev)
  45. {
  46. DigicTimerState *s = DIGIC_TIMER(dev);
  47. ptimer_stop(s->ptimer);
  48. s->control = 0;
  49. s->relvalue = 0;
  50. }
  51. static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size)
  52. {
  53. DigicTimerState *s = opaque;
  54. uint64_t ret = 0;
  55. switch (offset) {
  56. case DIGIC_TIMER_CONTROL:
  57. ret = s->control;
  58. break;
  59. case DIGIC_TIMER_RELVALUE:
  60. ret = s->relvalue;
  61. break;
  62. case DIGIC_TIMER_VALUE:
  63. ret = ptimer_get_count(s->ptimer) & 0xffff;
  64. break;
  65. default:
  66. qemu_log_mask(LOG_UNIMP,
  67. "digic-timer: read access to unknown register 0x"
  68. TARGET_FMT_plx, offset);
  69. }
  70. return ret;
  71. }
  72. static void digic_timer_write(void *opaque, hwaddr offset,
  73. uint64_t value, unsigned size)
  74. {
  75. DigicTimerState *s = opaque;
  76. switch (offset) {
  77. case DIGIC_TIMER_CONTROL:
  78. if (value & DIGIC_TIMER_CONTROL_RST) {
  79. digic_timer_reset((DeviceState *)s);
  80. break;
  81. }
  82. if (value & DIGIC_TIMER_CONTROL_EN) {
  83. ptimer_run(s->ptimer, 0);
  84. }
  85. s->control = (uint32_t)value;
  86. break;
  87. case DIGIC_TIMER_RELVALUE:
  88. s->relvalue = extract32(value, 0, 16);
  89. ptimer_set_limit(s->ptimer, s->relvalue, 1);
  90. break;
  91. case DIGIC_TIMER_VALUE:
  92. break;
  93. default:
  94. qemu_log_mask(LOG_UNIMP,
  95. "digic-timer: read access to unknown register 0x"
  96. TARGET_FMT_plx, offset);
  97. }
  98. }
  99. static const MemoryRegionOps digic_timer_ops = {
  100. .read = digic_timer_read,
  101. .write = digic_timer_write,
  102. .impl = {
  103. .min_access_size = 4,
  104. .max_access_size = 4,
  105. },
  106. .endianness = DEVICE_NATIVE_ENDIAN,
  107. };
  108. static void digic_timer_init(Object *obj)
  109. {
  110. DigicTimerState *s = DIGIC_TIMER(obj);
  111. s->ptimer = ptimer_init(NULL);
  112. /*
  113. * FIXME: there is no documentation on Digic timer
  114. * frequency setup so let it always run at 1 MHz
  115. */
  116. ptimer_set_freq(s->ptimer, 1 * 1000 * 1000);
  117. memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s,
  118. TYPE_DIGIC_TIMER, 0x100);
  119. sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
  120. }
  121. static void digic_timer_class_init(ObjectClass *klass, void *class_data)
  122. {
  123. DeviceClass *dc = DEVICE_CLASS(klass);
  124. dc->reset = digic_timer_reset;
  125. dc->vmsd = &vmstate_digic_timer;
  126. }
  127. static const TypeInfo digic_timer_info = {
  128. .name = TYPE_DIGIC_TIMER,
  129. .parent = TYPE_SYS_BUS_DEVICE,
  130. .instance_size = sizeof(DigicTimerState),
  131. .instance_init = digic_timer_init,
  132. .class_init = digic_timer_class_init,
  133. };
  134. static void digic_timer_register_type(void)
  135. {
  136. type_register_static(&digic_timer_info);
  137. }
  138. type_init(digic_timer_register_type)