vexpress.c 16 KB

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  1. /*
  2. * ARM Versatile Express emulation.
  3. *
  4. * Copyright (c) 2010 - 2011 B Labs Ltd.
  5. * Copyright (c) 2011 Linaro Limited
  6. * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, see <http://www.gnu.org/licenses/>.
  19. *
  20. * Contributions after 2012-01-13 are licensed under the terms of the
  21. * GNU GPL, version 2 or (at your option) any later version.
  22. */
  23. #include "sysbus.h"
  24. #include "arm-misc.h"
  25. #include "primecell.h"
  26. #include "devices.h"
  27. #include "net/net.h"
  28. #include "sysemu/sysemu.h"
  29. #include "boards.h"
  30. #include "exec/address-spaces.h"
  31. #include "sysemu/blockdev.h"
  32. #include "flash.h"
  33. #define VEXPRESS_BOARD_ID 0x8e0
  34. #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  35. #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  36. static struct arm_boot_info vexpress_binfo;
  37. /* Address maps for peripherals:
  38. * the Versatile Express motherboard has two possible maps,
  39. * the "legacy" one (used for A9) and the "Cortex-A Series"
  40. * map (used for newer cores).
  41. * Individual daughterboards can also have different maps for
  42. * their peripherals.
  43. */
  44. enum {
  45. VE_SYSREGS,
  46. VE_SP810,
  47. VE_SERIALPCI,
  48. VE_PL041,
  49. VE_MMCI,
  50. VE_KMI0,
  51. VE_KMI1,
  52. VE_UART0,
  53. VE_UART1,
  54. VE_UART2,
  55. VE_UART3,
  56. VE_WDT,
  57. VE_TIMER01,
  58. VE_TIMER23,
  59. VE_SERIALDVI,
  60. VE_RTC,
  61. VE_COMPACTFLASH,
  62. VE_CLCD,
  63. VE_NORFLASH0,
  64. VE_NORFLASH1,
  65. VE_SRAM,
  66. VE_VIDEORAM,
  67. VE_ETHERNET,
  68. VE_USB,
  69. VE_DAPROM,
  70. };
  71. static hwaddr motherboard_legacy_map[] = {
  72. /* CS7: 0x10000000 .. 0x10020000 */
  73. [VE_SYSREGS] = 0x10000000,
  74. [VE_SP810] = 0x10001000,
  75. [VE_SERIALPCI] = 0x10002000,
  76. [VE_PL041] = 0x10004000,
  77. [VE_MMCI] = 0x10005000,
  78. [VE_KMI0] = 0x10006000,
  79. [VE_KMI1] = 0x10007000,
  80. [VE_UART0] = 0x10009000,
  81. [VE_UART1] = 0x1000a000,
  82. [VE_UART2] = 0x1000b000,
  83. [VE_UART3] = 0x1000c000,
  84. [VE_WDT] = 0x1000f000,
  85. [VE_TIMER01] = 0x10011000,
  86. [VE_TIMER23] = 0x10012000,
  87. [VE_SERIALDVI] = 0x10016000,
  88. [VE_RTC] = 0x10017000,
  89. [VE_COMPACTFLASH] = 0x1001a000,
  90. [VE_CLCD] = 0x1001f000,
  91. /* CS0: 0x40000000 .. 0x44000000 */
  92. [VE_NORFLASH0] = 0x40000000,
  93. /* CS1: 0x44000000 .. 0x48000000 */
  94. [VE_NORFLASH1] = 0x44000000,
  95. /* CS2: 0x48000000 .. 0x4a000000 */
  96. [VE_SRAM] = 0x48000000,
  97. /* CS3: 0x4c000000 .. 0x50000000 */
  98. [VE_VIDEORAM] = 0x4c000000,
  99. [VE_ETHERNET] = 0x4e000000,
  100. [VE_USB] = 0x4f000000,
  101. };
  102. static hwaddr motherboard_aseries_map[] = {
  103. /* CS0: 0x08000000 .. 0x0c000000 */
  104. [VE_NORFLASH0] = 0x08000000,
  105. /* CS4: 0x0c000000 .. 0x10000000 */
  106. [VE_NORFLASH1] = 0x0c000000,
  107. /* CS5: 0x10000000 .. 0x14000000 */
  108. /* CS1: 0x14000000 .. 0x18000000 */
  109. [VE_SRAM] = 0x14000000,
  110. /* CS2: 0x18000000 .. 0x1c000000 */
  111. [VE_VIDEORAM] = 0x18000000,
  112. [VE_ETHERNET] = 0x1a000000,
  113. [VE_USB] = 0x1b000000,
  114. /* CS3: 0x1c000000 .. 0x20000000 */
  115. [VE_DAPROM] = 0x1c000000,
  116. [VE_SYSREGS] = 0x1c010000,
  117. [VE_SP810] = 0x1c020000,
  118. [VE_SERIALPCI] = 0x1c030000,
  119. [VE_PL041] = 0x1c040000,
  120. [VE_MMCI] = 0x1c050000,
  121. [VE_KMI0] = 0x1c060000,
  122. [VE_KMI1] = 0x1c070000,
  123. [VE_UART0] = 0x1c090000,
  124. [VE_UART1] = 0x1c0a0000,
  125. [VE_UART2] = 0x1c0b0000,
  126. [VE_UART3] = 0x1c0c0000,
  127. [VE_WDT] = 0x1c0f0000,
  128. [VE_TIMER01] = 0x1c110000,
  129. [VE_TIMER23] = 0x1c120000,
  130. [VE_SERIALDVI] = 0x1c160000,
  131. [VE_RTC] = 0x1c170000,
  132. [VE_COMPACTFLASH] = 0x1c1a0000,
  133. [VE_CLCD] = 0x1c1f0000,
  134. };
  135. /* Structure defining the peculiarities of a specific daughterboard */
  136. typedef struct VEDBoardInfo VEDBoardInfo;
  137. typedef void DBoardInitFn(const VEDBoardInfo *daughterboard,
  138. ram_addr_t ram_size,
  139. const char *cpu_model,
  140. qemu_irq *pic, uint32_t *proc_id);
  141. struct VEDBoardInfo {
  142. const hwaddr *motherboard_map;
  143. hwaddr loader_start;
  144. const hwaddr gic_cpu_if_addr;
  145. DBoardInitFn *init;
  146. };
  147. static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
  148. ram_addr_t ram_size,
  149. const char *cpu_model,
  150. qemu_irq *pic, uint32_t *proc_id)
  151. {
  152. MemoryRegion *sysmem = get_system_memory();
  153. MemoryRegion *ram = g_new(MemoryRegion, 1);
  154. MemoryRegion *lowram = g_new(MemoryRegion, 1);
  155. DeviceState *dev;
  156. SysBusDevice *busdev;
  157. qemu_irq *irqp;
  158. int n;
  159. qemu_irq cpu_irq[4];
  160. ram_addr_t low_ram_size;
  161. if (!cpu_model) {
  162. cpu_model = "cortex-a9";
  163. }
  164. *proc_id = 0x0c000191;
  165. for (n = 0; n < smp_cpus; n++) {
  166. ARMCPU *cpu = cpu_arm_init(cpu_model);
  167. if (!cpu) {
  168. fprintf(stderr, "Unable to find CPU definition\n");
  169. exit(1);
  170. }
  171. irqp = arm_pic_init_cpu(cpu);
  172. cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
  173. }
  174. if (ram_size > 0x40000000) {
  175. /* 1GB is the maximum the address space permits */
  176. fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
  177. exit(1);
  178. }
  179. memory_region_init_ram(ram, "vexpress.highmem", ram_size);
  180. vmstate_register_ram_global(ram);
  181. low_ram_size = ram_size;
  182. if (low_ram_size > 0x4000000) {
  183. low_ram_size = 0x4000000;
  184. }
  185. /* RAM is from 0x60000000 upwards. The bottom 64MB of the
  186. * address space should in theory be remappable to various
  187. * things including ROM or RAM; we always map the RAM there.
  188. */
  189. memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size);
  190. memory_region_add_subregion(sysmem, 0x0, lowram);
  191. memory_region_add_subregion(sysmem, 0x60000000, ram);
  192. /* 0x1e000000 A9MPCore (SCU) private memory region */
  193. dev = qdev_create(NULL, "a9mpcore_priv");
  194. qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
  195. qdev_init_nofail(dev);
  196. busdev = SYS_BUS_DEVICE(dev);
  197. sysbus_mmio_map(busdev, 0, 0x1e000000);
  198. for (n = 0; n < smp_cpus; n++) {
  199. sysbus_connect_irq(busdev, n, cpu_irq[n]);
  200. }
  201. /* Interrupts [42:0] are from the motherboard;
  202. * [47:43] are reserved; [63:48] are daughterboard
  203. * peripherals. Note that some documentation numbers
  204. * external interrupts starting from 32 (because the
  205. * A9MP has internal interrupts 0..31).
  206. */
  207. for (n = 0; n < 64; n++) {
  208. pic[n] = qdev_get_gpio_in(dev, n);
  209. }
  210. /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
  211. /* 0x10020000 PL111 CLCD (daughterboard) */
  212. sysbus_create_simple("pl111", 0x10020000, pic[44]);
  213. /* 0x10060000 AXI RAM */
  214. /* 0x100e0000 PL341 Dynamic Memory Controller */
  215. /* 0x100e1000 PL354 Static Memory Controller */
  216. /* 0x100e2000 System Configuration Controller */
  217. sysbus_create_simple("sp804", 0x100e4000, pic[48]);
  218. /* 0x100e5000 SP805 Watchdog module */
  219. /* 0x100e6000 BP147 TrustZone Protection Controller */
  220. /* 0x100e9000 PL301 'Fast' AXI matrix */
  221. /* 0x100ea000 PL301 'Slow' AXI matrix */
  222. /* 0x100ec000 TrustZone Address Space Controller */
  223. /* 0x10200000 CoreSight debug APB */
  224. /* 0x1e00a000 PL310 L2 Cache Controller */
  225. sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
  226. }
  227. static const VEDBoardInfo a9_daughterboard = {
  228. .motherboard_map = motherboard_legacy_map,
  229. .loader_start = 0x60000000,
  230. .gic_cpu_if_addr = 0x1e000100,
  231. .init = a9_daughterboard_init,
  232. };
  233. static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
  234. ram_addr_t ram_size,
  235. const char *cpu_model,
  236. qemu_irq *pic, uint32_t *proc_id)
  237. {
  238. int n;
  239. MemoryRegion *sysmem = get_system_memory();
  240. MemoryRegion *ram = g_new(MemoryRegion, 1);
  241. MemoryRegion *sram = g_new(MemoryRegion, 1);
  242. qemu_irq cpu_irq[4];
  243. DeviceState *dev;
  244. SysBusDevice *busdev;
  245. if (!cpu_model) {
  246. cpu_model = "cortex-a15";
  247. }
  248. *proc_id = 0x14000237;
  249. for (n = 0; n < smp_cpus; n++) {
  250. ARMCPU *cpu;
  251. qemu_irq *irqp;
  252. cpu = cpu_arm_init(cpu_model);
  253. if (!cpu) {
  254. fprintf(stderr, "Unable to find CPU definition\n");
  255. exit(1);
  256. }
  257. irqp = arm_pic_init_cpu(cpu);
  258. cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
  259. }
  260. {
  261. /* We have to use a separate 64 bit variable here to avoid the gcc
  262. * "comparison is always false due to limited range of data type"
  263. * warning if we are on a host where ram_addr_t is 32 bits.
  264. */
  265. uint64_t rsz = ram_size;
  266. if (rsz > (30ULL * 1024 * 1024 * 1024)) {
  267. fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
  268. exit(1);
  269. }
  270. }
  271. memory_region_init_ram(ram, "vexpress.highmem", ram_size);
  272. vmstate_register_ram_global(ram);
  273. /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
  274. memory_region_add_subregion(sysmem, 0x80000000, ram);
  275. /* 0x2c000000 A15MPCore private memory region (GIC) */
  276. dev = qdev_create(NULL, "a15mpcore_priv");
  277. qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
  278. qdev_init_nofail(dev);
  279. busdev = SYS_BUS_DEVICE(dev);
  280. sysbus_mmio_map(busdev, 0, 0x2c000000);
  281. for (n = 0; n < smp_cpus; n++) {
  282. sysbus_connect_irq(busdev, n, cpu_irq[n]);
  283. }
  284. /* Interrupts [42:0] are from the motherboard;
  285. * [47:43] are reserved; [63:48] are daughterboard
  286. * peripherals. Note that some documentation numbers
  287. * external interrupts starting from 32 (because there
  288. * are internal interrupts 0..31).
  289. */
  290. for (n = 0; n < 64; n++) {
  291. pic[n] = qdev_get_gpio_in(dev, n);
  292. }
  293. /* A15 daughterboard peripherals: */
  294. /* 0x20000000: CoreSight interfaces: not modelled */
  295. /* 0x2a000000: PL301 AXI interconnect: not modelled */
  296. /* 0x2a420000: SCC: not modelled */
  297. /* 0x2a430000: system counter: not modelled */
  298. /* 0x2b000000: HDLCD controller: not modelled */
  299. /* 0x2b060000: SP805 watchdog: not modelled */
  300. /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
  301. /* 0x2e000000: system SRAM */
  302. memory_region_init_ram(sram, "vexpress.a15sram", 0x10000);
  303. vmstate_register_ram_global(sram);
  304. memory_region_add_subregion(sysmem, 0x2e000000, sram);
  305. /* 0x7ffb0000: DMA330 DMA controller: not modelled */
  306. /* 0x7ffd0000: PL354 static memory controller: not modelled */
  307. }
  308. static const VEDBoardInfo a15_daughterboard = {
  309. .motherboard_map = motherboard_aseries_map,
  310. .loader_start = 0x80000000,
  311. .gic_cpu_if_addr = 0x2c002000,
  312. .init = a15_daughterboard_init,
  313. };
  314. static void vexpress_common_init(const VEDBoardInfo *daughterboard,
  315. QEMUMachineInitArgs *args)
  316. {
  317. DeviceState *dev, *sysctl, *pl041;
  318. qemu_irq pic[64];
  319. uint32_t proc_id;
  320. uint32_t sys_id;
  321. DriveInfo *dinfo;
  322. ram_addr_t vram_size, sram_size;
  323. MemoryRegion *sysmem = get_system_memory();
  324. MemoryRegion *vram = g_new(MemoryRegion, 1);
  325. MemoryRegion *sram = g_new(MemoryRegion, 1);
  326. const hwaddr *map = daughterboard->motherboard_map;
  327. daughterboard->init(daughterboard, args->ram_size, args->cpu_model,
  328. pic, &proc_id);
  329. /* Motherboard peripherals: the wiring is the same but the
  330. * addresses vary between the legacy and A-Series memory maps.
  331. */
  332. sys_id = 0x1190f500;
  333. sysctl = qdev_create(NULL, "realview_sysctl");
  334. qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
  335. qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
  336. qdev_init_nofail(sysctl);
  337. sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
  338. /* VE_SP810: not modelled */
  339. /* VE_SERIALPCI: not modelled */
  340. pl041 = qdev_create(NULL, "pl041");
  341. qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
  342. qdev_init_nofail(pl041);
  343. sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
  344. sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
  345. dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
  346. /* Wire up MMC card detect and read-only signals */
  347. qdev_connect_gpio_out(dev, 0,
  348. qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
  349. qdev_connect_gpio_out(dev, 1,
  350. qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
  351. sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
  352. sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
  353. sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
  354. sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
  355. sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
  356. sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
  357. sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
  358. sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
  359. /* VE_SERIALDVI: not modelled */
  360. sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
  361. /* VE_COMPACTFLASH: not modelled */
  362. sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
  363. dinfo = drive_get_next(IF_PFLASH);
  364. if (!pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0",
  365. VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
  366. VEXPRESS_FLASH_SECT_SIZE,
  367. VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
  368. 0x00, 0x89, 0x00, 0x18, 0)) {
  369. fprintf(stderr, "vexpress: error registering flash 0.\n");
  370. exit(1);
  371. }
  372. dinfo = drive_get_next(IF_PFLASH);
  373. if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1",
  374. VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
  375. VEXPRESS_FLASH_SECT_SIZE,
  376. VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
  377. 0x00, 0x89, 0x00, 0x18, 0)) {
  378. fprintf(stderr, "vexpress: error registering flash 1.\n");
  379. exit(1);
  380. }
  381. sram_size = 0x2000000;
  382. memory_region_init_ram(sram, "vexpress.sram", sram_size);
  383. vmstate_register_ram_global(sram);
  384. memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
  385. vram_size = 0x800000;
  386. memory_region_init_ram(vram, "vexpress.vram", vram_size);
  387. vmstate_register_ram_global(vram);
  388. memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
  389. /* 0x4e000000 LAN9118 Ethernet */
  390. if (nd_table[0].used) {
  391. lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
  392. }
  393. /* VE_USB: not modelled */
  394. /* VE_DAPROM: not modelled */
  395. vexpress_binfo.ram_size = args->ram_size;
  396. vexpress_binfo.kernel_filename = args->kernel_filename;
  397. vexpress_binfo.kernel_cmdline = args->kernel_cmdline;
  398. vexpress_binfo.initrd_filename = args->initrd_filename;
  399. vexpress_binfo.nb_cpus = smp_cpus;
  400. vexpress_binfo.board_id = VEXPRESS_BOARD_ID;
  401. vexpress_binfo.loader_start = daughterboard->loader_start;
  402. vexpress_binfo.smp_loader_start = map[VE_SRAM];
  403. vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
  404. vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
  405. arm_load_kernel(arm_env_get_cpu(first_cpu), &vexpress_binfo);
  406. }
  407. static void vexpress_a9_init(QEMUMachineInitArgs *args)
  408. {
  409. vexpress_common_init(&a9_daughterboard, args);
  410. }
  411. static void vexpress_a15_init(QEMUMachineInitArgs *args)
  412. {
  413. vexpress_common_init(&a15_daughterboard, args);
  414. }
  415. static QEMUMachine vexpress_a9_machine = {
  416. .name = "vexpress-a9",
  417. .desc = "ARM Versatile Express for Cortex-A9",
  418. .init = vexpress_a9_init,
  419. .block_default_type = IF_SCSI,
  420. .max_cpus = 4,
  421. DEFAULT_MACHINE_OPTIONS,
  422. };
  423. static QEMUMachine vexpress_a15_machine = {
  424. .name = "vexpress-a15",
  425. .desc = "ARM Versatile Express for Cortex-A15",
  426. .init = vexpress_a15_init,
  427. .block_default_type = IF_SCSI,
  428. .max_cpus = 4,
  429. DEFAULT_MACHINE_OPTIONS,
  430. };
  431. static void vexpress_machine_init(void)
  432. {
  433. qemu_register_machine(&vexpress_a9_machine);
  434. qemu_register_machine(&vexpress_a15_machine);
  435. }
  436. machine_init(vexpress_machine_init);