tpci200.c 19 KB

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  1. /*
  2. * QEMU TEWS TPCI200 IndustryPack carrier emulation
  3. *
  4. * Copyright (C) 2012 Igalia, S.L.
  5. * Author: Alberto Garcia <agarcia@igalia.com>
  6. *
  7. * This code is licensed under the GNU GPL v2 or (at your option) any
  8. * later version.
  9. */
  10. #include "ipack.h"
  11. #include "pci/pci.h"
  12. #include "qemu/bitops.h"
  13. #include <stdio.h>
  14. /* #define DEBUG_TPCI */
  15. #ifdef DEBUG_TPCI
  16. #define DPRINTF(fmt, ...) \
  17. do { fprintf(stderr, "TPCI200: " fmt, ## __VA_ARGS__); } while (0)
  18. #else
  19. #define DPRINTF(fmt, ...) do { } while (0)
  20. #endif
  21. #define N_MODULES 4
  22. #define IP_ID_SPACE 2
  23. #define IP_INT_SPACE 3
  24. #define IP_IO_SPACE_ADDR_MASK 0x7F
  25. #define IP_ID_SPACE_ADDR_MASK 0x3F
  26. #define IP_INT_SPACE_ADDR_MASK 0x3F
  27. #define STATUS_INT(IP, INTNO) BIT((IP) * 2 + (INTNO))
  28. #define STATUS_TIME(IP) BIT((IP) + 12)
  29. #define STATUS_ERR_ANY 0xF00
  30. #define CTRL_CLKRATE BIT(0)
  31. #define CTRL_RECOVER BIT(1)
  32. #define CTRL_TIME_INT BIT(2)
  33. #define CTRL_ERR_INT BIT(3)
  34. #define CTRL_INT_EDGE(INTNO) BIT(4 + (INTNO))
  35. #define CTRL_INT(INTNO) BIT(6 + (INTNO))
  36. #define REG_REV_ID 0x00
  37. #define REG_IP_A_CTRL 0x02
  38. #define REG_IP_B_CTRL 0x04
  39. #define REG_IP_C_CTRL 0x06
  40. #define REG_IP_D_CTRL 0x08
  41. #define REG_RESET 0x0A
  42. #define REG_STATUS 0x0C
  43. #define IP_N_FROM_REG(REG) ((REG) / 2 - 1)
  44. typedef struct {
  45. PCIDevice dev;
  46. IPackBus bus;
  47. MemoryRegion mmio;
  48. MemoryRegion io;
  49. MemoryRegion las0;
  50. MemoryRegion las1;
  51. MemoryRegion las2;
  52. MemoryRegion las3;
  53. bool big_endian[3];
  54. uint8_t ctrl[N_MODULES];
  55. uint16_t status;
  56. uint8_t int_set;
  57. } TPCI200State;
  58. #define TYPE_TPCI200 "tpci200"
  59. #define TPCI200(obj) \
  60. OBJECT_CHECK(TPCI200State, (obj), TYPE_TPCI200)
  61. static const uint8_t local_config_regs[] = {
  62. 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0x00,
  63. 0x0E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  64. 0x00, 0x08, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x01,
  65. 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x60, 0x41, 0xD4,
  66. 0xA2, 0x20, 0x41, 0x14, 0xA2, 0x20, 0x41, 0x14, 0xA2, 0x20, 0x01,
  67. 0x14, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x08, 0x01, 0x02,
  68. 0x00, 0x04, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02, 0x41,
  69. 0x00, 0x00, 0x00, 0x00, 0x40, 0x7A, 0x00, 0x52, 0x92, 0x24, 0x02
  70. };
  71. static void adjust_addr(bool big_endian, hwaddr *addr, unsigned size)
  72. {
  73. /* During 8 bit access in big endian mode,
  74. odd and even addresses are swapped */
  75. if (big_endian && size == 1) {
  76. *addr ^= 1;
  77. }
  78. }
  79. static uint64_t adjust_value(bool big_endian, uint64_t *val, unsigned size)
  80. {
  81. /* Local spaces only support 8/16 bit access,
  82. * so there's no need to care for sizes > 2 */
  83. if (big_endian && size == 2) {
  84. *val = bswap16(*val);
  85. }
  86. return *val;
  87. }
  88. static void tpci200_set_irq(void *opaque, int intno, int level)
  89. {
  90. IPackDevice *ip = opaque;
  91. IPackBus *bus = IPACK_BUS(qdev_get_parent_bus(DEVICE(ip)));
  92. PCIDevice *pcidev = PCI_DEVICE(BUS(bus)->parent);
  93. TPCI200State *dev = TPCI200(pcidev);
  94. unsigned ip_n = ip->slot;
  95. uint16_t prev_status = dev->status;
  96. assert(ip->slot >= 0 && ip->slot < N_MODULES);
  97. /* The requested interrupt must be enabled in the IP CONTROL
  98. * register */
  99. if (!(dev->ctrl[ip_n] & CTRL_INT(intno))) {
  100. return;
  101. }
  102. /* Update the interrupt status in the IP STATUS register */
  103. if (level) {
  104. dev->status |= STATUS_INT(ip_n, intno);
  105. } else {
  106. dev->status &= ~STATUS_INT(ip_n, intno);
  107. }
  108. /* Return if there are no changes */
  109. if (dev->status == prev_status) {
  110. return;
  111. }
  112. DPRINTF("IP %u INT%u#: %u\n", ip_n, intno, level);
  113. /* Check if the interrupt is edge sensitive */
  114. if (dev->ctrl[ip_n] & CTRL_INT_EDGE(intno)) {
  115. if (level) {
  116. qemu_set_irq(dev->dev.irq[0], !dev->int_set);
  117. qemu_set_irq(dev->dev.irq[0], dev->int_set);
  118. }
  119. } else {
  120. unsigned i, j;
  121. uint16_t level_status = dev->status;
  122. /* Check if there are any level sensitive interrupts set by
  123. removing the ones that are edge sensitive from the status
  124. register */
  125. for (i = 0; i < N_MODULES; i++) {
  126. for (j = 0; j < 2; j++) {
  127. if (dev->ctrl[i] & CTRL_INT_EDGE(j)) {
  128. level_status &= ~STATUS_INT(i, j);
  129. }
  130. }
  131. }
  132. if (level_status && !dev->int_set) {
  133. qemu_irq_raise(dev->dev.irq[0]);
  134. dev->int_set = 1;
  135. } else if (!level_status && dev->int_set) {
  136. qemu_irq_lower(dev->dev.irq[0]);
  137. dev->int_set = 0;
  138. }
  139. }
  140. }
  141. static uint64_t tpci200_read_cfg(void *opaque, hwaddr addr, unsigned size)
  142. {
  143. TPCI200State *s = opaque;
  144. uint8_t ret = 0;
  145. if (addr < ARRAY_SIZE(local_config_regs)) {
  146. ret = local_config_regs[addr];
  147. }
  148. /* Endianness is stored in the first bit of these registers */
  149. if ((addr == 0x2b && s->big_endian[0]) ||
  150. (addr == 0x2f && s->big_endian[1]) ||
  151. (addr == 0x33 && s->big_endian[2])) {
  152. ret |= 1;
  153. }
  154. DPRINTF("Read from LCR 0x%x: 0x%x\n", (unsigned) addr, (unsigned) ret);
  155. return ret;
  156. }
  157. static void tpci200_write_cfg(void *opaque, hwaddr addr, uint64_t val,
  158. unsigned size)
  159. {
  160. TPCI200State *s = opaque;
  161. /* Endianness is stored in the first bit of these registers */
  162. if (addr == 0x2b || addr == 0x2f || addr == 0x33) {
  163. unsigned las = (addr - 0x2b) / 4;
  164. s->big_endian[las] = val & 1;
  165. DPRINTF("LAS%u big endian mode: %u\n", las, (unsigned) val & 1);
  166. } else {
  167. DPRINTF("Write to LCR 0x%x: 0x%x\n", (unsigned) addr, (unsigned) val);
  168. }
  169. }
  170. static uint64_t tpci200_read_las0(void *opaque, hwaddr addr, unsigned size)
  171. {
  172. TPCI200State *s = opaque;
  173. uint64_t ret = 0;
  174. switch (addr) {
  175. case REG_REV_ID:
  176. DPRINTF("Read REVISION ID\n"); /* Current value is 0x00 */
  177. break;
  178. case REG_IP_A_CTRL:
  179. case REG_IP_B_CTRL:
  180. case REG_IP_C_CTRL:
  181. case REG_IP_D_CTRL:
  182. {
  183. unsigned ip_n = IP_N_FROM_REG(addr);
  184. ret = s->ctrl[ip_n];
  185. DPRINTF("Read IP %c CONTROL: 0x%x\n", 'A' + ip_n, (unsigned) ret);
  186. }
  187. break;
  188. case REG_RESET:
  189. DPRINTF("Read RESET\n"); /* Not implemented */
  190. break;
  191. case REG_STATUS:
  192. ret = s->status;
  193. DPRINTF("Read STATUS: 0x%x\n", (unsigned) ret);
  194. break;
  195. /* Reserved */
  196. default:
  197. DPRINTF("Unsupported read from LAS0 0x%x\n", (unsigned) addr);
  198. break;
  199. }
  200. return adjust_value(s->big_endian[0], &ret, size);
  201. }
  202. static void tpci200_write_las0(void *opaque, hwaddr addr, uint64_t val,
  203. unsigned size)
  204. {
  205. TPCI200State *s = opaque;
  206. adjust_value(s->big_endian[0], &val, size);
  207. switch (addr) {
  208. case REG_REV_ID:
  209. DPRINTF("Write Revision ID: 0x%x\n", (unsigned) val); /* No effect */
  210. break;
  211. case REG_IP_A_CTRL:
  212. case REG_IP_B_CTRL:
  213. case REG_IP_C_CTRL:
  214. case REG_IP_D_CTRL:
  215. {
  216. unsigned ip_n = IP_N_FROM_REG(addr);
  217. s->ctrl[ip_n] = val;
  218. DPRINTF("Write IP %c CONTROL: 0x%x\n", 'A' + ip_n, (unsigned) val);
  219. }
  220. break;
  221. case REG_RESET:
  222. DPRINTF("Write RESET: 0x%x\n", (unsigned) val); /* Not implemented */
  223. break;
  224. case REG_STATUS:
  225. {
  226. unsigned i;
  227. for (i = 0; i < N_MODULES; i++) {
  228. IPackDevice *ip = ipack_device_find(&s->bus, i);
  229. if (ip != NULL) {
  230. if (val & STATUS_INT(i, 0)) {
  231. DPRINTF("Clear IP %c INT0# status\n", 'A' + i);
  232. qemu_irq_lower(ip->irq[0]);
  233. }
  234. if (val & STATUS_INT(i, 1)) {
  235. DPRINTF("Clear IP %c INT1# status\n", 'A' + i);
  236. qemu_irq_lower(ip->irq[1]);
  237. }
  238. }
  239. if (val & STATUS_TIME(i)) {
  240. DPRINTF("Clear IP %c timeout\n", 'A' + i);
  241. s->status &= ~STATUS_TIME(i);
  242. }
  243. }
  244. if (val & STATUS_ERR_ANY) {
  245. DPRINTF("Unexpected write to STATUS register: 0x%x\n",
  246. (unsigned) val);
  247. }
  248. }
  249. break;
  250. /* Reserved */
  251. default:
  252. DPRINTF("Unsupported write to LAS0 0x%x: 0x%x\n",
  253. (unsigned) addr, (unsigned) val);
  254. break;
  255. }
  256. }
  257. static uint64_t tpci200_read_las1(void *opaque, hwaddr addr, unsigned size)
  258. {
  259. TPCI200State *s = opaque;
  260. IPackDevice *ip;
  261. uint64_t ret = 0;
  262. unsigned ip_n, space;
  263. uint8_t offset;
  264. adjust_addr(s->big_endian[1], &addr, size);
  265. /*
  266. * The address is divided into the IP module number (0-4), the IP
  267. * address space (I/O, ID, INT) and the offset within that space.
  268. */
  269. ip_n = addr >> 8;
  270. space = (addr >> 6) & 3;
  271. ip = ipack_device_find(&s->bus, ip_n);
  272. if (ip == NULL) {
  273. DPRINTF("Read LAS1: IP module %u not installed\n", ip_n);
  274. } else {
  275. IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
  276. switch (space) {
  277. case IP_ID_SPACE:
  278. offset = addr & IP_ID_SPACE_ADDR_MASK;
  279. if (k->id_read) {
  280. ret = k->id_read(ip, offset);
  281. }
  282. break;
  283. case IP_INT_SPACE:
  284. offset = addr & IP_INT_SPACE_ADDR_MASK;
  285. /* Read address 0 to ACK IP INT0# and address 2 to ACK IP INT1# */
  286. if (offset == 0 || offset == 2) {
  287. unsigned intno = offset / 2;
  288. bool int_set = s->status & STATUS_INT(ip_n, intno);
  289. bool int_edge_sensitive = s->ctrl[ip_n] & CTRL_INT_EDGE(intno);
  290. if (int_set && !int_edge_sensitive) {
  291. qemu_irq_lower(ip->irq[intno]);
  292. }
  293. }
  294. if (k->int_read) {
  295. ret = k->int_read(ip, offset);
  296. }
  297. break;
  298. default:
  299. offset = addr & IP_IO_SPACE_ADDR_MASK;
  300. if (k->io_read) {
  301. ret = k->io_read(ip, offset);
  302. }
  303. break;
  304. }
  305. }
  306. return adjust_value(s->big_endian[1], &ret, size);
  307. }
  308. static void tpci200_write_las1(void *opaque, hwaddr addr, uint64_t val,
  309. unsigned size)
  310. {
  311. TPCI200State *s = opaque;
  312. IPackDevice *ip;
  313. unsigned ip_n, space;
  314. uint8_t offset;
  315. adjust_addr(s->big_endian[1], &addr, size);
  316. adjust_value(s->big_endian[1], &val, size);
  317. /*
  318. * The address is divided into the IP module number, the IP
  319. * address space (I/O, ID, INT) and the offset within that space.
  320. */
  321. ip_n = addr >> 8;
  322. space = (addr >> 6) & 3;
  323. ip = ipack_device_find(&s->bus, ip_n);
  324. if (ip == NULL) {
  325. DPRINTF("Write LAS1: IP module %u not installed\n", ip_n);
  326. } else {
  327. IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
  328. switch (space) {
  329. case IP_ID_SPACE:
  330. offset = addr & IP_ID_SPACE_ADDR_MASK;
  331. if (k->id_write) {
  332. k->id_write(ip, offset, val);
  333. }
  334. break;
  335. case IP_INT_SPACE:
  336. offset = addr & IP_INT_SPACE_ADDR_MASK;
  337. if (k->int_write) {
  338. k->int_write(ip, offset, val);
  339. }
  340. break;
  341. default:
  342. offset = addr & IP_IO_SPACE_ADDR_MASK;
  343. if (k->io_write) {
  344. k->io_write(ip, offset, val);
  345. }
  346. break;
  347. }
  348. }
  349. }
  350. static uint64_t tpci200_read_las2(void *opaque, hwaddr addr, unsigned size)
  351. {
  352. TPCI200State *s = opaque;
  353. IPackDevice *ip;
  354. uint64_t ret = 0;
  355. unsigned ip_n;
  356. uint32_t offset;
  357. adjust_addr(s->big_endian[2], &addr, size);
  358. /*
  359. * The address is divided into the IP module number and the offset
  360. * within the IP module MEM space.
  361. */
  362. ip_n = addr >> 23;
  363. offset = addr & 0x7fffff;
  364. ip = ipack_device_find(&s->bus, ip_n);
  365. if (ip == NULL) {
  366. DPRINTF("Read LAS2: IP module %u not installed\n", ip_n);
  367. } else {
  368. IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
  369. if (k->mem_read16) {
  370. ret = k->mem_read16(ip, offset);
  371. }
  372. }
  373. return adjust_value(s->big_endian[2], &ret, size);
  374. }
  375. static void tpci200_write_las2(void *opaque, hwaddr addr, uint64_t val,
  376. unsigned size)
  377. {
  378. TPCI200State *s = opaque;
  379. IPackDevice *ip;
  380. unsigned ip_n;
  381. uint32_t offset;
  382. adjust_addr(s->big_endian[2], &addr, size);
  383. adjust_value(s->big_endian[2], &val, size);
  384. /*
  385. * The address is divided into the IP module number and the offset
  386. * within the IP module MEM space.
  387. */
  388. ip_n = addr >> 23;
  389. offset = addr & 0x7fffff;
  390. ip = ipack_device_find(&s->bus, ip_n);
  391. if (ip == NULL) {
  392. DPRINTF("Write LAS2: IP module %u not installed\n", ip_n);
  393. } else {
  394. IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
  395. if (k->mem_write16) {
  396. k->mem_write16(ip, offset, val);
  397. }
  398. }
  399. }
  400. static uint64_t tpci200_read_las3(void *opaque, hwaddr addr, unsigned size)
  401. {
  402. TPCI200State *s = opaque;
  403. IPackDevice *ip;
  404. uint64_t ret = 0;
  405. /*
  406. * The address is divided into the IP module number and the offset
  407. * within the IP module MEM space.
  408. */
  409. unsigned ip_n = addr >> 22;
  410. uint32_t offset = addr & 0x3fffff;
  411. ip = ipack_device_find(&s->bus, ip_n);
  412. if (ip == NULL) {
  413. DPRINTF("Read LAS3: IP module %u not installed\n", ip_n);
  414. } else {
  415. IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
  416. if (k->mem_read8) {
  417. ret = k->mem_read8(ip, offset);
  418. }
  419. }
  420. return ret;
  421. }
  422. static void tpci200_write_las3(void *opaque, hwaddr addr, uint64_t val,
  423. unsigned size)
  424. {
  425. TPCI200State *s = opaque;
  426. IPackDevice *ip;
  427. /*
  428. * The address is divided into the IP module number and the offset
  429. * within the IP module MEM space.
  430. */
  431. unsigned ip_n = addr >> 22;
  432. uint32_t offset = addr & 0x3fffff;
  433. ip = ipack_device_find(&s->bus, ip_n);
  434. if (ip == NULL) {
  435. DPRINTF("Write LAS3: IP module %u not installed\n", ip_n);
  436. } else {
  437. IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
  438. if (k->mem_write8) {
  439. k->mem_write8(ip, offset, val);
  440. }
  441. }
  442. }
  443. static const MemoryRegionOps tpci200_cfg_ops = {
  444. .read = tpci200_read_cfg,
  445. .write = tpci200_write_cfg,
  446. .endianness = DEVICE_NATIVE_ENDIAN,
  447. .valid = {
  448. .min_access_size = 1,
  449. .max_access_size = 4
  450. },
  451. .impl = {
  452. .min_access_size = 1,
  453. .max_access_size = 1
  454. }
  455. };
  456. static const MemoryRegionOps tpci200_las0_ops = {
  457. .read = tpci200_read_las0,
  458. .write = tpci200_write_las0,
  459. .endianness = DEVICE_NATIVE_ENDIAN,
  460. .valid = {
  461. .min_access_size = 2,
  462. .max_access_size = 2
  463. }
  464. };
  465. static const MemoryRegionOps tpci200_las1_ops = {
  466. .read = tpci200_read_las1,
  467. .write = tpci200_write_las1,
  468. .endianness = DEVICE_NATIVE_ENDIAN,
  469. .valid = {
  470. .min_access_size = 1,
  471. .max_access_size = 2
  472. }
  473. };
  474. static const MemoryRegionOps tpci200_las2_ops = {
  475. .read = tpci200_read_las2,
  476. .write = tpci200_write_las2,
  477. .endianness = DEVICE_NATIVE_ENDIAN,
  478. .valid = {
  479. .min_access_size = 1,
  480. .max_access_size = 2
  481. }
  482. };
  483. static const MemoryRegionOps tpci200_las3_ops = {
  484. .read = tpci200_read_las3,
  485. .write = tpci200_write_las3,
  486. .endianness = DEVICE_NATIVE_ENDIAN,
  487. .valid = {
  488. .min_access_size = 1,
  489. .max_access_size = 1
  490. }
  491. };
  492. static int tpci200_initfn(PCIDevice *pci_dev)
  493. {
  494. TPCI200State *s = TPCI200(pci_dev);
  495. uint8_t *c = s->dev.config;
  496. pci_set_word(c + PCI_COMMAND, 0x0003);
  497. pci_set_word(c + PCI_STATUS, 0x0280);
  498. pci_set_byte(c + PCI_INTERRUPT_PIN, 0x01); /* Interrupt pin A */
  499. pci_set_byte(c + PCI_CAPABILITY_LIST, 0x40);
  500. pci_set_long(c + 0x40, 0x48014801);
  501. pci_set_long(c + 0x48, 0x00024C06);
  502. pci_set_long(c + 0x4C, 0x00000003);
  503. memory_region_init_io(&s->mmio, &tpci200_cfg_ops,
  504. s, "tpci200_mmio", 128);
  505. memory_region_init_io(&s->io, &tpci200_cfg_ops,
  506. s, "tpci200_io", 128);
  507. memory_region_init_io(&s->las0, &tpci200_las0_ops,
  508. s, "tpci200_las0", 256);
  509. memory_region_init_io(&s->las1, &tpci200_las1_ops,
  510. s, "tpci200_las1", 1024);
  511. memory_region_init_io(&s->las2, &tpci200_las2_ops,
  512. s, "tpci200_las2", 1024*1024*32);
  513. memory_region_init_io(&s->las3, &tpci200_las3_ops,
  514. s, "tpci200_las3", 1024*1024*16);
  515. pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
  516. pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
  517. pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las0);
  518. pci_register_bar(&s->dev, 3, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las1);
  519. pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las2);
  520. pci_register_bar(&s->dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las3);
  521. ipack_bus_new_inplace(&s->bus, DEVICE(&s->dev), NULL,
  522. N_MODULES, tpci200_set_irq);
  523. return 0;
  524. }
  525. static void tpci200_exitfn(PCIDevice *pci_dev)
  526. {
  527. TPCI200State *s = TPCI200(pci_dev);
  528. memory_region_destroy(&s->mmio);
  529. memory_region_destroy(&s->io);
  530. memory_region_destroy(&s->las0);
  531. memory_region_destroy(&s->las1);
  532. memory_region_destroy(&s->las2);
  533. memory_region_destroy(&s->las3);
  534. }
  535. static const VMStateDescription vmstate_tpci200 = {
  536. .name = "tpci200",
  537. .version_id = 1,
  538. .minimum_version_id = 1,
  539. .minimum_version_id_old = 1,
  540. .fields = (VMStateField[]) {
  541. VMSTATE_PCI_DEVICE(dev, TPCI200State),
  542. VMSTATE_BOOL_ARRAY(big_endian, TPCI200State, 3),
  543. VMSTATE_UINT8_ARRAY(ctrl, TPCI200State, N_MODULES),
  544. VMSTATE_UINT16(status, TPCI200State),
  545. VMSTATE_UINT8(int_set, TPCI200State),
  546. VMSTATE_END_OF_LIST()
  547. }
  548. };
  549. static void tpci200_class_init(ObjectClass *klass, void *data)
  550. {
  551. DeviceClass *dc = DEVICE_CLASS(klass);
  552. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  553. k->init = tpci200_initfn;
  554. k->exit = tpci200_exitfn;
  555. k->vendor_id = PCI_VENDOR_ID_TEWS;
  556. k->device_id = PCI_DEVICE_ID_TEWS_TPCI200;
  557. k->class_id = PCI_CLASS_BRIDGE_OTHER;
  558. k->subsystem_vendor_id = PCI_VENDOR_ID_TEWS;
  559. k->subsystem_id = 0x300A;
  560. dc->desc = "TEWS TPCI200 IndustryPack carrier";
  561. dc->vmsd = &vmstate_tpci200;
  562. }
  563. static const TypeInfo tpci200_info = {
  564. .name = TYPE_TPCI200,
  565. .parent = TYPE_PCI_DEVICE,
  566. .instance_size = sizeof(TPCI200State),
  567. .class_init = tpci200_class_init,
  568. };
  569. static void tpci200_register_types(void)
  570. {
  571. type_register_static(&tpci200_info);
  572. }
  573. type_init(tpci200_register_types)