tc58128.c 4.2 KB

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  1. #include "hw.h"
  2. #include "sh.h"
  3. #include "loader.h"
  4. #define CE1 0x0100
  5. #define CE2 0x0200
  6. #define RE 0x0400
  7. #define WE 0x0800
  8. #define ALE 0x1000
  9. #define CLE 0x2000
  10. #define RDY1 0x4000
  11. #define RDY2 0x8000
  12. #define RDY(n) ((n) == 0 ? RDY1 : RDY2)
  13. typedef enum { WAIT, READ1, READ2, READ3 } state_t;
  14. typedef struct {
  15. uint8_t *flash_contents;
  16. state_t state;
  17. uint32_t address;
  18. uint8_t address_cycle;
  19. } tc58128_dev;
  20. static tc58128_dev tc58128_devs[2];
  21. #define FLASH_SIZE (16*1024*1024)
  22. static void init_dev(tc58128_dev * dev, const char *filename)
  23. {
  24. int ret, blocks;
  25. dev->state = WAIT;
  26. dev->flash_contents = g_malloc(FLASH_SIZE);
  27. memset(dev->flash_contents, 0xff, FLASH_SIZE);
  28. if (filename) {
  29. /* Load flash image skipping the first block */
  30. ret = load_image(filename, dev->flash_contents + 528 * 32);
  31. if (ret < 0) {
  32. fprintf(stderr, "ret=%d\n", ret);
  33. fprintf(stderr, "qemu: could not load flash image %s\n",
  34. filename);
  35. exit(1);
  36. } else {
  37. /* Build first block with number of blocks */
  38. blocks = (ret + 528 * 32 - 1) / (528 * 32);
  39. dev->flash_contents[0] = blocks & 0xff;
  40. dev->flash_contents[1] = (blocks >> 8) & 0xff;
  41. dev->flash_contents[2] = (blocks >> 16) & 0xff;
  42. dev->flash_contents[3] = (blocks >> 24) & 0xff;
  43. fprintf(stderr, "loaded %d bytes for %s into flash\n", ret,
  44. filename);
  45. }
  46. }
  47. }
  48. static void handle_command(tc58128_dev * dev, uint8_t command)
  49. {
  50. switch (command) {
  51. case 0xff:
  52. fprintf(stderr, "reset flash device\n");
  53. dev->state = WAIT;
  54. break;
  55. case 0x00:
  56. fprintf(stderr, "read mode 1\n");
  57. dev->state = READ1;
  58. dev->address_cycle = 0;
  59. break;
  60. case 0x01:
  61. fprintf(stderr, "read mode 2\n");
  62. dev->state = READ2;
  63. dev->address_cycle = 0;
  64. break;
  65. case 0x50:
  66. fprintf(stderr, "read mode 3\n");
  67. dev->state = READ3;
  68. dev->address_cycle = 0;
  69. break;
  70. default:
  71. fprintf(stderr, "unknown flash command 0x%02x\n", command);
  72. abort();
  73. }
  74. }
  75. static void handle_address(tc58128_dev * dev, uint8_t data)
  76. {
  77. switch (dev->state) {
  78. case READ1:
  79. case READ2:
  80. case READ3:
  81. switch (dev->address_cycle) {
  82. case 0:
  83. dev->address = data;
  84. if (dev->state == READ2)
  85. dev->address |= 0x100;
  86. else if (dev->state == READ3)
  87. dev->address |= 0x200;
  88. break;
  89. case 1:
  90. dev->address += data * 528 * 0x100;
  91. break;
  92. case 2:
  93. dev->address += data * 528;
  94. fprintf(stderr, "address pointer in flash: 0x%08x\n",
  95. dev->address);
  96. break;
  97. default:
  98. /* Invalid data */
  99. abort();
  100. }
  101. dev->address_cycle++;
  102. break;
  103. default:
  104. abort();
  105. }
  106. }
  107. static uint8_t handle_read(tc58128_dev * dev)
  108. {
  109. #if 0
  110. if (dev->address % 0x100000 == 0)
  111. fprintf(stderr, "reading flash at address 0x%08x\n", dev->address);
  112. #endif
  113. return dev->flash_contents[dev->address++];
  114. }
  115. /* We never mark the device as busy, so interrupts cannot be triggered
  116. XXXXX */
  117. static int tc58128_cb(uint16_t porta, uint16_t portb,
  118. uint16_t * periph_pdtra, uint16_t * periph_portadir,
  119. uint16_t * periph_pdtrb, uint16_t * periph_portbdir)
  120. {
  121. int dev;
  122. if ((porta & CE1) == 0)
  123. dev = 0;
  124. else if ((porta & CE2) == 0)
  125. dev = 1;
  126. else
  127. return 0; /* No device selected */
  128. if ((porta & RE) && (porta & WE)) {
  129. /* Nothing to do, assert ready and return to input state */
  130. *periph_portadir &= 0xff00;
  131. *periph_portadir |= RDY(dev);
  132. *periph_pdtra |= RDY(dev);
  133. return 1;
  134. }
  135. if (porta & CLE) {
  136. /* Command */
  137. assert((porta & WE) == 0);
  138. handle_command(&tc58128_devs[dev], porta & 0x00ff);
  139. } else if (porta & ALE) {
  140. assert((porta & WE) == 0);
  141. handle_address(&tc58128_devs[dev], porta & 0x00ff);
  142. } else if ((porta & RE) == 0) {
  143. *periph_portadir |= 0x00ff;
  144. *periph_pdtra &= 0xff00;
  145. *periph_pdtra |= handle_read(&tc58128_devs[dev]);
  146. } else {
  147. abort();
  148. }
  149. return 1;
  150. }
  151. static sh7750_io_device tc58128 = {
  152. RE | WE, /* Port A triggers */
  153. 0, /* Port B triggers */
  154. tc58128_cb /* Callback */
  155. };
  156. int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
  157. {
  158. init_dev(&tc58128_devs[0], zone1);
  159. init_dev(&tc58128_devs[1], zone2);
  160. return sh7750_register_io_device(s, &tc58128);
  161. }