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spitz.c 32 KB

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  1. /*
  2. * PXA270-based Clamshell PDA platforms.
  3. *
  4. * Copyright (c) 2006 Openedhand Ltd.
  5. * Written by Andrzej Zaborowski <balrog@zabor.org>
  6. *
  7. * This code is licensed under the GNU GPL v2.
  8. *
  9. * Contributions after 2012-01-13 are licensed under the terms of the
  10. * GNU GPL, version 2 or (at your option) any later version.
  11. */
  12. #include "hw.h"
  13. #include "pxa.h"
  14. #include "arm-misc.h"
  15. #include "sysemu/sysemu.h"
  16. #include "pcmcia.h"
  17. #include "i2c.h"
  18. #include "ssi.h"
  19. #include "flash.h"
  20. #include "qemu/timer.h"
  21. #include "devices.h"
  22. #include "sharpsl.h"
  23. #include "ui/console.h"
  24. #include "block/block.h"
  25. #include "audio/audio.h"
  26. #include "boards.h"
  27. #include "sysemu/blockdev.h"
  28. #include "sysbus.h"
  29. #include "exec/address-spaces.h"
  30. #undef REG_FMT
  31. #define REG_FMT "0x%02lx"
  32. /* Spitz Flash */
  33. #define FLASH_BASE 0x0c000000
  34. #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
  35. #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
  36. #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
  37. #define FLASH_ECCCNTR 0x0c /* ECC byte counter */
  38. #define FLASH_ECCCLRR 0x10 /* Clear ECC */
  39. #define FLASH_FLASHIO 0x14 /* Flash I/O */
  40. #define FLASH_FLASHCTL 0x18 /* Flash Control */
  41. #define FLASHCTL_CE0 (1 << 0)
  42. #define FLASHCTL_CLE (1 << 1)
  43. #define FLASHCTL_ALE (1 << 2)
  44. #define FLASHCTL_WP (1 << 3)
  45. #define FLASHCTL_CE1 (1 << 4)
  46. #define FLASHCTL_RYBY (1 << 5)
  47. #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
  48. typedef struct {
  49. SysBusDevice busdev;
  50. MemoryRegion iomem;
  51. DeviceState *nand;
  52. uint8_t ctl;
  53. uint8_t manf_id;
  54. uint8_t chip_id;
  55. ECCState ecc;
  56. } SLNANDState;
  57. static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
  58. {
  59. SLNANDState *s = (SLNANDState *) opaque;
  60. int ryby;
  61. switch (addr) {
  62. #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
  63. case FLASH_ECCLPLB:
  64. return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
  65. BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
  66. #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
  67. case FLASH_ECCLPUB:
  68. return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
  69. BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
  70. case FLASH_ECCCP:
  71. return s->ecc.cp;
  72. case FLASH_ECCCNTR:
  73. return s->ecc.count & 0xff;
  74. case FLASH_FLASHCTL:
  75. nand_getpins(s->nand, &ryby);
  76. if (ryby)
  77. return s->ctl | FLASHCTL_RYBY;
  78. else
  79. return s->ctl;
  80. case FLASH_FLASHIO:
  81. if (size == 4) {
  82. return ecc_digest(&s->ecc, nand_getio(s->nand)) |
  83. (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
  84. }
  85. return ecc_digest(&s->ecc, nand_getio(s->nand));
  86. default:
  87. zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
  88. }
  89. return 0;
  90. }
  91. static void sl_write(void *opaque, hwaddr addr,
  92. uint64_t value, unsigned size)
  93. {
  94. SLNANDState *s = (SLNANDState *) opaque;
  95. switch (addr) {
  96. case FLASH_ECCCLRR:
  97. /* Value is ignored. */
  98. ecc_reset(&s->ecc);
  99. break;
  100. case FLASH_FLASHCTL:
  101. s->ctl = value & 0xff & ~FLASHCTL_RYBY;
  102. nand_setpins(s->nand,
  103. s->ctl & FLASHCTL_CLE,
  104. s->ctl & FLASHCTL_ALE,
  105. s->ctl & FLASHCTL_NCE,
  106. s->ctl & FLASHCTL_WP,
  107. 0);
  108. break;
  109. case FLASH_FLASHIO:
  110. nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
  111. break;
  112. default:
  113. zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
  114. }
  115. }
  116. enum {
  117. FLASH_128M,
  118. FLASH_1024M,
  119. };
  120. static const MemoryRegionOps sl_ops = {
  121. .read = sl_read,
  122. .write = sl_write,
  123. .endianness = DEVICE_NATIVE_ENDIAN,
  124. };
  125. static void sl_flash_register(PXA2xxState *cpu, int size)
  126. {
  127. DeviceState *dev;
  128. dev = qdev_create(NULL, "sl-nand");
  129. qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
  130. if (size == FLASH_128M)
  131. qdev_prop_set_uint8(dev, "chip_id", 0x73);
  132. else if (size == FLASH_1024M)
  133. qdev_prop_set_uint8(dev, "chip_id", 0xf1);
  134. qdev_init_nofail(dev);
  135. sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE);
  136. }
  137. static int sl_nand_init(SysBusDevice *dev) {
  138. SLNANDState *s;
  139. DriveInfo *nand;
  140. s = FROM_SYSBUS(SLNANDState, dev);
  141. s->ctl = 0;
  142. nand = drive_get(IF_MTD, 0, 0);
  143. s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id);
  144. memory_region_init_io(&s->iomem, &sl_ops, s, "sl", 0x40);
  145. sysbus_init_mmio(dev, &s->iomem);
  146. return 0;
  147. }
  148. /* Spitz Keyboard */
  149. #define SPITZ_KEY_STROBE_NUM 11
  150. #define SPITZ_KEY_SENSE_NUM 7
  151. static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
  152. 12, 17, 91, 34, 36, 38, 39
  153. };
  154. static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
  155. 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
  156. };
  157. /* Eighth additional row maps the special keys */
  158. static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
  159. { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
  160. { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
  161. { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
  162. { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
  163. { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
  164. { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
  165. { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
  166. { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
  167. };
  168. #define SPITZ_GPIO_AK_INT 13 /* Remote control */
  169. #define SPITZ_GPIO_SYNC 16 /* Sync button */
  170. #define SPITZ_GPIO_ON_KEY 95 /* Power button */
  171. #define SPITZ_GPIO_SWA 97 /* Lid */
  172. #define SPITZ_GPIO_SWB 96 /* Tablet mode */
  173. /* The special buttons are mapped to unused keys */
  174. static const int spitz_gpiomap[5] = {
  175. SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
  176. SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
  177. };
  178. typedef struct {
  179. SysBusDevice busdev;
  180. qemu_irq sense[SPITZ_KEY_SENSE_NUM];
  181. qemu_irq gpiomap[5];
  182. int keymap[0x80];
  183. uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
  184. uint16_t strobe_state;
  185. uint16_t sense_state;
  186. uint16_t pre_map[0x100];
  187. uint16_t modifiers;
  188. uint16_t imodifiers;
  189. uint8_t fifo[16];
  190. int fifopos, fifolen;
  191. QEMUTimer *kbdtimer;
  192. } SpitzKeyboardState;
  193. static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
  194. {
  195. int i;
  196. uint16_t strobe, sense = 0;
  197. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
  198. strobe = s->keyrow[i] & s->strobe_state;
  199. if (strobe) {
  200. sense |= 1 << i;
  201. if (!(s->sense_state & (1 << i)))
  202. qemu_irq_raise(s->sense[i]);
  203. } else if (s->sense_state & (1 << i))
  204. qemu_irq_lower(s->sense[i]);
  205. }
  206. s->sense_state = sense;
  207. }
  208. static void spitz_keyboard_strobe(void *opaque, int line, int level)
  209. {
  210. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  211. if (level)
  212. s->strobe_state |= 1 << line;
  213. else
  214. s->strobe_state &= ~(1 << line);
  215. spitz_keyboard_sense_update(s);
  216. }
  217. static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
  218. {
  219. int spitz_keycode = s->keymap[keycode & 0x7f];
  220. if (spitz_keycode == -1)
  221. return;
  222. /* Handle the additional keys */
  223. if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
  224. qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80));
  225. return;
  226. }
  227. if (keycode & 0x80)
  228. s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
  229. else
  230. s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
  231. spitz_keyboard_sense_update(s);
  232. }
  233. #define SHIFT (1 << 7)
  234. #define CTRL (1 << 8)
  235. #define FN (1 << 9)
  236. #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
  237. static void spitz_keyboard_handler(void *opaque, int keycode)
  238. {
  239. SpitzKeyboardState *s = opaque;
  240. uint16_t code;
  241. int mapcode;
  242. switch (keycode) {
  243. case 0x2a: /* Left Shift */
  244. s->modifiers |= 1;
  245. break;
  246. case 0xaa:
  247. s->modifiers &= ~1;
  248. break;
  249. case 0x36: /* Right Shift */
  250. s->modifiers |= 2;
  251. break;
  252. case 0xb6:
  253. s->modifiers &= ~2;
  254. break;
  255. case 0x1d: /* Control */
  256. s->modifiers |= 4;
  257. break;
  258. case 0x9d:
  259. s->modifiers &= ~4;
  260. break;
  261. case 0x38: /* Alt */
  262. s->modifiers |= 8;
  263. break;
  264. case 0xb8:
  265. s->modifiers &= ~8;
  266. break;
  267. }
  268. code = s->pre_map[mapcode = ((s->modifiers & 3) ?
  269. (keycode | SHIFT) :
  270. (keycode & ~SHIFT))];
  271. if (code != mapcode) {
  272. #if 0
  273. if ((code & SHIFT) && !(s->modifiers & 1))
  274. QUEUE_KEY(0x2a | (keycode & 0x80));
  275. if ((code & CTRL ) && !(s->modifiers & 4))
  276. QUEUE_KEY(0x1d | (keycode & 0x80));
  277. if ((code & FN ) && !(s->modifiers & 8))
  278. QUEUE_KEY(0x38 | (keycode & 0x80));
  279. if ((code & FN ) && (s->modifiers & 1))
  280. QUEUE_KEY(0x2a | (~keycode & 0x80));
  281. if ((code & FN ) && (s->modifiers & 2))
  282. QUEUE_KEY(0x36 | (~keycode & 0x80));
  283. #else
  284. if (keycode & 0x80) {
  285. if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
  286. QUEUE_KEY(0x2a | 0x80);
  287. if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
  288. QUEUE_KEY(0x1d | 0x80);
  289. if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
  290. QUEUE_KEY(0x38 | 0x80);
  291. if ((s->imodifiers & 0x10) && (s->modifiers & 1))
  292. QUEUE_KEY(0x2a);
  293. if ((s->imodifiers & 0x20) && (s->modifiers & 2))
  294. QUEUE_KEY(0x36);
  295. s->imodifiers = 0;
  296. } else {
  297. if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
  298. QUEUE_KEY(0x2a);
  299. s->imodifiers |= 1;
  300. }
  301. if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
  302. QUEUE_KEY(0x1d);
  303. s->imodifiers |= 4;
  304. }
  305. if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
  306. QUEUE_KEY(0x38);
  307. s->imodifiers |= 8;
  308. }
  309. if ((code & FN ) && (s->modifiers & 1) &&
  310. !(s->imodifiers & 0x10)) {
  311. QUEUE_KEY(0x2a | 0x80);
  312. s->imodifiers |= 0x10;
  313. }
  314. if ((code & FN ) && (s->modifiers & 2) &&
  315. !(s->imodifiers & 0x20)) {
  316. QUEUE_KEY(0x36 | 0x80);
  317. s->imodifiers |= 0x20;
  318. }
  319. }
  320. #endif
  321. }
  322. QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
  323. }
  324. static void spitz_keyboard_tick(void *opaque)
  325. {
  326. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  327. if (s->fifolen) {
  328. spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
  329. s->fifolen --;
  330. if (s->fifopos >= 16)
  331. s->fifopos = 0;
  332. }
  333. qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock) +
  334. get_ticks_per_sec() / 32);
  335. }
  336. static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
  337. {
  338. int i;
  339. for (i = 0; i < 0x100; i ++)
  340. s->pre_map[i] = i;
  341. s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
  342. s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
  343. s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
  344. s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
  345. s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
  346. s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
  347. s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
  348. s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
  349. s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
  350. s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
  351. s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
  352. s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
  353. s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
  354. s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
  355. s->pre_map[0x0d ] = 0x12 | FN; /* equal */
  356. s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
  357. s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
  358. s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
  359. s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
  360. s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
  361. s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
  362. s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
  363. s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
  364. s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
  365. s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
  366. s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
  367. s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
  368. s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
  369. s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
  370. s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
  371. s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
  372. s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
  373. s->modifiers = 0;
  374. s->imodifiers = 0;
  375. s->fifopos = 0;
  376. s->fifolen = 0;
  377. }
  378. #undef SHIFT
  379. #undef CTRL
  380. #undef FN
  381. static int spitz_keyboard_post_load(void *opaque, int version_id)
  382. {
  383. SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
  384. /* Release all pressed keys */
  385. memset(s->keyrow, 0, sizeof(s->keyrow));
  386. spitz_keyboard_sense_update(s);
  387. s->modifiers = 0;
  388. s->imodifiers = 0;
  389. s->fifopos = 0;
  390. s->fifolen = 0;
  391. return 0;
  392. }
  393. static void spitz_keyboard_register(PXA2xxState *cpu)
  394. {
  395. int i;
  396. DeviceState *dev;
  397. SpitzKeyboardState *s;
  398. dev = sysbus_create_simple("spitz-keyboard", -1, NULL);
  399. s = FROM_SYSBUS(SpitzKeyboardState, SYS_BUS_DEVICE(dev));
  400. for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
  401. qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(cpu->gpio, spitz_gpio_key_sense[i]));
  402. for (i = 0; i < 5; i ++)
  403. s->gpiomap[i] = qdev_get_gpio_in(cpu->gpio, spitz_gpiomap[i]);
  404. if (!graphic_rotate)
  405. s->gpiomap[4] = qemu_irq_invert(s->gpiomap[4]);
  406. for (i = 0; i < 5; i++)
  407. qemu_set_irq(s->gpiomap[i], 0);
  408. for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
  409. qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
  410. qdev_get_gpio_in(dev, i));
  411. qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock));
  412. qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
  413. }
  414. static int spitz_keyboard_init(SysBusDevice *dev)
  415. {
  416. SpitzKeyboardState *s;
  417. int i, j;
  418. s = FROM_SYSBUS(SpitzKeyboardState, dev);
  419. for (i = 0; i < 0x80; i ++)
  420. s->keymap[i] = -1;
  421. for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
  422. for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
  423. if (spitz_keymap[i][j] != -1)
  424. s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
  425. spitz_keyboard_pre_map(s);
  426. s->kbdtimer = qemu_new_timer_ns(vm_clock, spitz_keyboard_tick, s);
  427. qdev_init_gpio_in(&dev->qdev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
  428. qdev_init_gpio_out(&dev->qdev, s->sense, SPITZ_KEY_SENSE_NUM);
  429. return 0;
  430. }
  431. /* LCD backlight controller */
  432. #define LCDTG_RESCTL 0x00
  433. #define LCDTG_PHACTRL 0x01
  434. #define LCDTG_DUTYCTRL 0x02
  435. #define LCDTG_POWERREG0 0x03
  436. #define LCDTG_POWERREG1 0x04
  437. #define LCDTG_GPOR3 0x05
  438. #define LCDTG_PICTRL 0x06
  439. #define LCDTG_POLCTRL 0x07
  440. typedef struct {
  441. SSISlave ssidev;
  442. uint32_t bl_intensity;
  443. uint32_t bl_power;
  444. } SpitzLCDTG;
  445. static void spitz_bl_update(SpitzLCDTG *s)
  446. {
  447. if (s->bl_power && s->bl_intensity)
  448. zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
  449. else
  450. zaurus_printf("LCD Backlight now off\n");
  451. }
  452. /* FIXME: Implement GPIO properly and remove this hack. */
  453. static SpitzLCDTG *spitz_lcdtg;
  454. static inline void spitz_bl_bit5(void *opaque, int line, int level)
  455. {
  456. SpitzLCDTG *s = spitz_lcdtg;
  457. int prev = s->bl_intensity;
  458. if (level)
  459. s->bl_intensity &= ~0x20;
  460. else
  461. s->bl_intensity |= 0x20;
  462. if (s->bl_power && prev != s->bl_intensity)
  463. spitz_bl_update(s);
  464. }
  465. static inline void spitz_bl_power(void *opaque, int line, int level)
  466. {
  467. SpitzLCDTG *s = spitz_lcdtg;
  468. s->bl_power = !!level;
  469. spitz_bl_update(s);
  470. }
  471. static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
  472. {
  473. SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
  474. int addr;
  475. addr = value >> 5;
  476. value &= 0x1f;
  477. switch (addr) {
  478. case LCDTG_RESCTL:
  479. if (value)
  480. zaurus_printf("LCD in QVGA mode\n");
  481. else
  482. zaurus_printf("LCD in VGA mode\n");
  483. break;
  484. case LCDTG_DUTYCTRL:
  485. s->bl_intensity &= ~0x1f;
  486. s->bl_intensity |= value;
  487. if (s->bl_power)
  488. spitz_bl_update(s);
  489. break;
  490. case LCDTG_POWERREG0:
  491. /* Set common voltage to M62332FP */
  492. break;
  493. }
  494. return 0;
  495. }
  496. static int spitz_lcdtg_init(SSISlave *dev)
  497. {
  498. SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
  499. spitz_lcdtg = s;
  500. s->bl_power = 0;
  501. s->bl_intensity = 0x20;
  502. return 0;
  503. }
  504. /* SSP devices */
  505. #define CORGI_SSP_PORT 2
  506. #define SPITZ_GPIO_LCDCON_CS 53
  507. #define SPITZ_GPIO_ADS7846_CS 14
  508. #define SPITZ_GPIO_MAX1111_CS 20
  509. #define SPITZ_GPIO_TP_INT 11
  510. static DeviceState *max1111;
  511. /* "Demux" the signal based on current chipselect */
  512. typedef struct {
  513. SSISlave ssidev;
  514. SSIBus *bus[3];
  515. uint32_t enable[3];
  516. } CorgiSSPState;
  517. static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
  518. {
  519. CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
  520. int i;
  521. for (i = 0; i < 3; i++) {
  522. if (s->enable[i]) {
  523. return ssi_transfer(s->bus[i], value);
  524. }
  525. }
  526. return 0;
  527. }
  528. static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
  529. {
  530. CorgiSSPState *s = (CorgiSSPState *)opaque;
  531. assert(line >= 0 && line < 3);
  532. s->enable[line] = !level;
  533. }
  534. #define MAX1111_BATT_VOLT 1
  535. #define MAX1111_BATT_TEMP 2
  536. #define MAX1111_ACIN_VOLT 3
  537. #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
  538. #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
  539. #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
  540. static void spitz_adc_temp_on(void *opaque, int line, int level)
  541. {
  542. if (!max1111)
  543. return;
  544. if (level)
  545. max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
  546. else
  547. max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
  548. }
  549. static int corgi_ssp_init(SSISlave *dev)
  550. {
  551. CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
  552. qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);
  553. s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
  554. s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
  555. s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
  556. return 0;
  557. }
  558. static void spitz_ssp_attach(PXA2xxState *cpu)
  559. {
  560. DeviceState *mux;
  561. DeviceState *dev;
  562. void *bus;
  563. mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
  564. bus = qdev_get_child_bus(mux, "ssi0");
  565. ssi_create_slave(bus, "spitz-lcdtg");
  566. bus = qdev_get_child_bus(mux, "ssi1");
  567. dev = ssi_create_slave(bus, "ads7846");
  568. qdev_connect_gpio_out(dev, 0,
  569. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
  570. bus = qdev_get_child_bus(mux, "ssi2");
  571. max1111 = ssi_create_slave(bus, "max1111");
  572. max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
  573. max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
  574. max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
  575. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
  576. qdev_get_gpio_in(mux, 0));
  577. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
  578. qdev_get_gpio_in(mux, 1));
  579. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
  580. qdev_get_gpio_in(mux, 2));
  581. }
  582. /* CF Microdrive */
  583. static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
  584. {
  585. PCMCIACardState *md;
  586. DriveInfo *dinfo;
  587. dinfo = drive_get(IF_IDE, 0, 0);
  588. if (!dinfo || dinfo->media_cd)
  589. return;
  590. md = dscm1xxxx_init(dinfo);
  591. pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
  592. }
  593. /* Wm8750 and Max7310 on I2C */
  594. #define AKITA_MAX_ADDR 0x18
  595. #define SPITZ_WM_ADDRL 0x1b
  596. #define SPITZ_WM_ADDRH 0x1a
  597. #define SPITZ_GPIO_WM 5
  598. static void spitz_wm8750_addr(void *opaque, int line, int level)
  599. {
  600. I2CSlave *wm = (I2CSlave *) opaque;
  601. if (level)
  602. i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
  603. else
  604. i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
  605. }
  606. static void spitz_i2c_setup(PXA2xxState *cpu)
  607. {
  608. /* Attach the CPU on one end of our I2C bus. */
  609. i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
  610. DeviceState *wm;
  611. /* Attach a WM8750 to the bus */
  612. wm = i2c_create_slave(bus, "wm8750", 0);
  613. spitz_wm8750_addr(wm, 0, 0);
  614. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_WM,
  615. qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
  616. /* .. and to the sound interface. */
  617. cpu->i2s->opaque = wm;
  618. cpu->i2s->codec_out = wm8750_dac_dat;
  619. cpu->i2s->codec_in = wm8750_adc_dat;
  620. wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
  621. }
  622. static void spitz_akita_i2c_setup(PXA2xxState *cpu)
  623. {
  624. /* Attach a Max7310 to Akita I2C bus. */
  625. i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
  626. AKITA_MAX_ADDR);
  627. }
  628. /* Other peripherals */
  629. static void spitz_out_switch(void *opaque, int line, int level)
  630. {
  631. switch (line) {
  632. case 0:
  633. zaurus_printf("Charging %s.\n", level ? "off" : "on");
  634. break;
  635. case 1:
  636. zaurus_printf("Discharging %s.\n", level ? "on" : "off");
  637. break;
  638. case 2:
  639. zaurus_printf("Green LED %s.\n", level ? "on" : "off");
  640. break;
  641. case 3:
  642. zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
  643. break;
  644. case 4:
  645. spitz_bl_bit5(opaque, line, level);
  646. break;
  647. case 5:
  648. spitz_bl_power(opaque, line, level);
  649. break;
  650. case 6:
  651. spitz_adc_temp_on(opaque, line, level);
  652. break;
  653. }
  654. }
  655. #define SPITZ_SCP_LED_GREEN 1
  656. #define SPITZ_SCP_JK_B 2
  657. #define SPITZ_SCP_CHRG_ON 3
  658. #define SPITZ_SCP_MUTE_L 4
  659. #define SPITZ_SCP_MUTE_R 5
  660. #define SPITZ_SCP_CF_POWER 6
  661. #define SPITZ_SCP_LED_ORANGE 7
  662. #define SPITZ_SCP_JK_A 8
  663. #define SPITZ_SCP_ADC_TEMP_ON 9
  664. #define SPITZ_SCP2_IR_ON 1
  665. #define SPITZ_SCP2_AKIN_PULLUP 2
  666. #define SPITZ_SCP2_BACKLIGHT_CONT 7
  667. #define SPITZ_SCP2_BACKLIGHT_ON 8
  668. #define SPITZ_SCP2_MIC_BIAS 9
  669. static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
  670. DeviceState *scp0, DeviceState *scp1)
  671. {
  672. qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
  673. qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
  674. qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
  675. qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
  676. qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
  677. if (scp1) {
  678. qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
  679. qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
  680. }
  681. qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
  682. }
  683. #define SPITZ_GPIO_HSYNC 22
  684. #define SPITZ_GPIO_SD_DETECT 9
  685. #define SPITZ_GPIO_SD_WP 81
  686. #define SPITZ_GPIO_ON_RESET 89
  687. #define SPITZ_GPIO_BAT_COVER 90
  688. #define SPITZ_GPIO_CF1_IRQ 105
  689. #define SPITZ_GPIO_CF1_CD 94
  690. #define SPITZ_GPIO_CF2_IRQ 106
  691. #define SPITZ_GPIO_CF2_CD 93
  692. static int spitz_hsync;
  693. static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
  694. {
  695. PXA2xxState *cpu = (PXA2xxState *) opaque;
  696. qemu_set_irq(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_HSYNC), spitz_hsync);
  697. spitz_hsync ^= 1;
  698. }
  699. static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
  700. {
  701. qemu_irq lcd_hsync;
  702. /*
  703. * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
  704. * read to satisfy broken guests that poll-wait for hsync.
  705. * Simulating a real hsync event would be less practical and
  706. * wouldn't guarantee that a guest ever exits the loop.
  707. */
  708. spitz_hsync = 0;
  709. lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
  710. pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
  711. pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
  712. /* MMC/SD host */
  713. pxa2xx_mmci_handlers(cpu->mmc,
  714. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_WP),
  715. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_DETECT));
  716. /* Battery lock always closed */
  717. qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
  718. /* Handle reset */
  719. qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
  720. /* PCMCIA signals: card's IRQ and Card-Detect */
  721. if (slots >= 1)
  722. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
  723. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_IRQ),
  724. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_CD));
  725. if (slots >= 2)
  726. pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
  727. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_IRQ),
  728. qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_CD));
  729. }
  730. /* Board init. */
  731. enum spitz_model_e { spitz, akita, borzoi, terrier };
  732. #define SPITZ_RAM 0x04000000
  733. #define SPITZ_ROM 0x00800000
  734. static struct arm_boot_info spitz_binfo = {
  735. .loader_start = PXA2XX_SDRAM_BASE,
  736. .ram_size = 0x04000000,
  737. };
  738. static void spitz_common_init(QEMUMachineInitArgs *args,
  739. enum spitz_model_e model, int arm_id)
  740. {
  741. PXA2xxState *mpu;
  742. DeviceState *scp0, *scp1 = NULL;
  743. MemoryRegion *address_space_mem = get_system_memory();
  744. MemoryRegion *rom = g_new(MemoryRegion, 1);
  745. const char *cpu_model = args->cpu_model;
  746. if (!cpu_model)
  747. cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
  748. /* Setup CPU & memory */
  749. mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
  750. sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
  751. memory_region_init_ram(rom, "spitz.rom", SPITZ_ROM);
  752. vmstate_register_ram_global(rom);
  753. memory_region_set_readonly(rom, true);
  754. memory_region_add_subregion(address_space_mem, 0, rom);
  755. /* Setup peripherals */
  756. spitz_keyboard_register(mpu);
  757. spitz_ssp_attach(mpu);
  758. scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
  759. if (model != akita) {
  760. scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
  761. }
  762. spitz_scoop_gpio_setup(mpu, scp0, scp1);
  763. spitz_gpio_setup(mpu, (model == akita) ? 1 : 2);
  764. spitz_i2c_setup(mpu);
  765. if (model == akita)
  766. spitz_akita_i2c_setup(mpu);
  767. if (model == terrier)
  768. /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
  769. spitz_microdrive_attach(mpu, 1);
  770. else if (model != akita)
  771. /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
  772. spitz_microdrive_attach(mpu, 0);
  773. spitz_binfo.kernel_filename = args->kernel_filename;
  774. spitz_binfo.kernel_cmdline = args->kernel_cmdline;
  775. spitz_binfo.initrd_filename = args->initrd_filename;
  776. spitz_binfo.board_id = arm_id;
  777. arm_load_kernel(mpu->cpu, &spitz_binfo);
  778. sl_bootparam_write(SL_PXA_PARAM_BASE);
  779. }
  780. static void spitz_init(QEMUMachineInitArgs *args)
  781. {
  782. spitz_common_init(args, spitz, 0x2c9);
  783. }
  784. static void borzoi_init(QEMUMachineInitArgs *args)
  785. {
  786. spitz_common_init(args, borzoi, 0x33f);
  787. }
  788. static void akita_init(QEMUMachineInitArgs *args)
  789. {
  790. spitz_common_init(args, akita, 0x2e8);
  791. }
  792. static void terrier_init(QEMUMachineInitArgs *args)
  793. {
  794. spitz_common_init(args, terrier, 0x33f);
  795. }
  796. static QEMUMachine akitapda_machine = {
  797. .name = "akita",
  798. .desc = "Akita PDA (PXA270)",
  799. .init = akita_init,
  800. DEFAULT_MACHINE_OPTIONS,
  801. };
  802. static QEMUMachine spitzpda_machine = {
  803. .name = "spitz",
  804. .desc = "Spitz PDA (PXA270)",
  805. .init = spitz_init,
  806. DEFAULT_MACHINE_OPTIONS,
  807. };
  808. static QEMUMachine borzoipda_machine = {
  809. .name = "borzoi",
  810. .desc = "Borzoi PDA (PXA270)",
  811. .init = borzoi_init,
  812. DEFAULT_MACHINE_OPTIONS,
  813. };
  814. static QEMUMachine terrierpda_machine = {
  815. .name = "terrier",
  816. .desc = "Terrier PDA (PXA270)",
  817. .init = terrier_init,
  818. DEFAULT_MACHINE_OPTIONS,
  819. };
  820. static void spitz_machine_init(void)
  821. {
  822. qemu_register_machine(&akitapda_machine);
  823. qemu_register_machine(&spitzpda_machine);
  824. qemu_register_machine(&borzoipda_machine);
  825. qemu_register_machine(&terrierpda_machine);
  826. }
  827. machine_init(spitz_machine_init);
  828. static bool is_version_0(void *opaque, int version_id)
  829. {
  830. return version_id == 0;
  831. }
  832. static VMStateDescription vmstate_sl_nand_info = {
  833. .name = "sl-nand",
  834. .version_id = 0,
  835. .minimum_version_id = 0,
  836. .minimum_version_id_old = 0,
  837. .fields = (VMStateField []) {
  838. VMSTATE_UINT8(ctl, SLNANDState),
  839. VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
  840. VMSTATE_END_OF_LIST(),
  841. },
  842. };
  843. static Property sl_nand_properties[] = {
  844. DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG),
  845. DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1),
  846. DEFINE_PROP_END_OF_LIST(),
  847. };
  848. static void sl_nand_class_init(ObjectClass *klass, void *data)
  849. {
  850. DeviceClass *dc = DEVICE_CLASS(klass);
  851. SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
  852. k->init = sl_nand_init;
  853. dc->vmsd = &vmstate_sl_nand_info;
  854. dc->props = sl_nand_properties;
  855. }
  856. static const TypeInfo sl_nand_info = {
  857. .name = "sl-nand",
  858. .parent = TYPE_SYS_BUS_DEVICE,
  859. .instance_size = sizeof(SLNANDState),
  860. .class_init = sl_nand_class_init,
  861. };
  862. static VMStateDescription vmstate_spitz_kbd = {
  863. .name = "spitz-keyboard",
  864. .version_id = 1,
  865. .minimum_version_id = 0,
  866. .minimum_version_id_old = 0,
  867. .post_load = spitz_keyboard_post_load,
  868. .fields = (VMStateField []) {
  869. VMSTATE_UINT16(sense_state, SpitzKeyboardState),
  870. VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
  871. VMSTATE_UNUSED_TEST(is_version_0, 5),
  872. VMSTATE_END_OF_LIST(),
  873. },
  874. };
  875. static Property spitz_keyboard_properties[] = {
  876. DEFINE_PROP_END_OF_LIST(),
  877. };
  878. static void spitz_keyboard_class_init(ObjectClass *klass, void *data)
  879. {
  880. DeviceClass *dc = DEVICE_CLASS(klass);
  881. SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
  882. k->init = spitz_keyboard_init;
  883. dc->vmsd = &vmstate_spitz_kbd;
  884. dc->props = spitz_keyboard_properties;
  885. }
  886. static const TypeInfo spitz_keyboard_info = {
  887. .name = "spitz-keyboard",
  888. .parent = TYPE_SYS_BUS_DEVICE,
  889. .instance_size = sizeof(SpitzKeyboardState),
  890. .class_init = spitz_keyboard_class_init,
  891. };
  892. static const VMStateDescription vmstate_corgi_ssp_regs = {
  893. .name = "corgi-ssp",
  894. .version_id = 2,
  895. .minimum_version_id = 2,
  896. .minimum_version_id_old = 2,
  897. .fields = (VMStateField []) {
  898. VMSTATE_SSI_SLAVE(ssidev, CorgiSSPState),
  899. VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
  900. VMSTATE_END_OF_LIST(),
  901. }
  902. };
  903. static void corgi_ssp_class_init(ObjectClass *klass, void *data)
  904. {
  905. DeviceClass *dc = DEVICE_CLASS(klass);
  906. SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
  907. k->init = corgi_ssp_init;
  908. k->transfer = corgi_ssp_transfer;
  909. dc->vmsd = &vmstate_corgi_ssp_regs;
  910. }
  911. static const TypeInfo corgi_ssp_info = {
  912. .name = "corgi-ssp",
  913. .parent = TYPE_SSI_SLAVE,
  914. .instance_size = sizeof(CorgiSSPState),
  915. .class_init = corgi_ssp_class_init,
  916. };
  917. static const VMStateDescription vmstate_spitz_lcdtg_regs = {
  918. .name = "spitz-lcdtg",
  919. .version_id = 1,
  920. .minimum_version_id = 1,
  921. .minimum_version_id_old = 1,
  922. .fields = (VMStateField []) {
  923. VMSTATE_SSI_SLAVE(ssidev, SpitzLCDTG),
  924. VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
  925. VMSTATE_UINT32(bl_power, SpitzLCDTG),
  926. VMSTATE_END_OF_LIST(),
  927. }
  928. };
  929. static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
  930. {
  931. DeviceClass *dc = DEVICE_CLASS(klass);
  932. SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
  933. k->init = spitz_lcdtg_init;
  934. k->transfer = spitz_lcdtg_transfer;
  935. dc->vmsd = &vmstate_spitz_lcdtg_regs;
  936. }
  937. static const TypeInfo spitz_lcdtg_info = {
  938. .name = "spitz-lcdtg",
  939. .parent = TYPE_SSI_SLAVE,
  940. .instance_size = sizeof(SpitzLCDTG),
  941. .class_init = spitz_lcdtg_class_init,
  942. };
  943. static void spitz_register_types(void)
  944. {
  945. type_register_static(&corgi_ssp_info);
  946. type_register_static(&spitz_lcdtg_info);
  947. type_register_static(&spitz_keyboard_info);
  948. type_register_static(&sl_nand_info);
  949. }
  950. type_init(spitz_register_types)