pckbd.c 16 KB

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  1. /*
  2. * QEMU PC keyboard emulation
  3. *
  4. * Copyright (c) 2003 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "hw.h"
  25. #include "isa.h"
  26. #include "pc.h"
  27. #include "ps2.h"
  28. #include "sysemu/sysemu.h"
  29. /* debug PC keyboard */
  30. //#define DEBUG_KBD
  31. #ifdef DEBUG_KBD
  32. #define DPRINTF(fmt, ...) \
  33. do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0)
  34. #else
  35. #define DPRINTF(fmt, ...)
  36. #endif
  37. /* Keyboard Controller Commands */
  38. #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
  39. #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
  40. #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
  41. #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
  42. #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
  43. #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
  44. #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
  45. #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
  46. #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
  47. #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
  48. #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
  49. #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
  50. #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
  51. #define KBD_CCMD_WRITE_OBUF 0xD2
  52. #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
  53. initiated by the auxiliary device */
  54. #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
  55. #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
  56. #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
  57. #define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */
  58. #define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */
  59. #define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */
  60. /* Keyboard Commands */
  61. #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
  62. #define KBD_CMD_ECHO 0xEE
  63. #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
  64. #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
  65. #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
  66. #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
  67. #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
  68. #define KBD_CMD_RESET 0xFF /* Reset */
  69. /* Keyboard Replies */
  70. #define KBD_REPLY_POR 0xAA /* Power on reset */
  71. #define KBD_REPLY_ACK 0xFA /* Command ACK */
  72. #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
  73. /* Status Register Bits */
  74. #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
  75. #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
  76. #define KBD_STAT_SELFTEST 0x04 /* Self test successful */
  77. #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
  78. #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
  79. #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
  80. #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
  81. #define KBD_STAT_PERR 0x80 /* Parity error */
  82. /* Controller Mode Register Bits */
  83. #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
  84. #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
  85. #define KBD_MODE_SYS 0x04 /* The system flag (?) */
  86. #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
  87. #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
  88. #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
  89. #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
  90. #define KBD_MODE_RFU 0x80
  91. /* Output Port Bits */
  92. #define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
  93. #define KBD_OUT_A20 0x02 /* x86 only */
  94. #define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
  95. #define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
  96. /* Mouse Commands */
  97. #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
  98. #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
  99. #define AUX_SET_RES 0xE8 /* Set resolution */
  100. #define AUX_GET_SCALE 0xE9 /* Get scaling factor */
  101. #define AUX_SET_STREAM 0xEA /* Set stream mode */
  102. #define AUX_POLL 0xEB /* Poll */
  103. #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
  104. #define AUX_SET_WRAP 0xEE /* Set wrap mode */
  105. #define AUX_SET_REMOTE 0xF0 /* Set remote mode */
  106. #define AUX_GET_TYPE 0xF2 /* Get type */
  107. #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
  108. #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
  109. #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
  110. #define AUX_SET_DEFAULT 0xF6
  111. #define AUX_RESET 0xFF /* Reset aux device */
  112. #define AUX_ACK 0xFA /* Command byte ACK. */
  113. #define MOUSE_STATUS_REMOTE 0x40
  114. #define MOUSE_STATUS_ENABLED 0x20
  115. #define MOUSE_STATUS_SCALE21 0x10
  116. #define KBD_PENDING_KBD 1
  117. #define KBD_PENDING_AUX 2
  118. typedef struct KBDState {
  119. uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
  120. uint8_t status;
  121. uint8_t mode;
  122. uint8_t outport;
  123. /* Bitmask of devices with data available. */
  124. uint8_t pending;
  125. void *kbd;
  126. void *mouse;
  127. qemu_irq irq_kbd;
  128. qemu_irq irq_mouse;
  129. qemu_irq *a20_out;
  130. hwaddr mask;
  131. } KBDState;
  132. /* update irq and KBD_STAT_[MOUSE_]OBF */
  133. /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
  134. incorrect, but it avoids having to simulate exact delays */
  135. static void kbd_update_irq(KBDState *s)
  136. {
  137. int irq_kbd_level, irq_mouse_level;
  138. irq_kbd_level = 0;
  139. irq_mouse_level = 0;
  140. s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
  141. s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
  142. if (s->pending) {
  143. s->status |= KBD_STAT_OBF;
  144. s->outport |= KBD_OUT_OBF;
  145. /* kbd data takes priority over aux data. */
  146. if (s->pending == KBD_PENDING_AUX) {
  147. s->status |= KBD_STAT_MOUSE_OBF;
  148. s->outport |= KBD_OUT_MOUSE_OBF;
  149. if (s->mode & KBD_MODE_MOUSE_INT)
  150. irq_mouse_level = 1;
  151. } else {
  152. if ((s->mode & KBD_MODE_KBD_INT) &&
  153. !(s->mode & KBD_MODE_DISABLE_KBD))
  154. irq_kbd_level = 1;
  155. }
  156. }
  157. qemu_set_irq(s->irq_kbd, irq_kbd_level);
  158. qemu_set_irq(s->irq_mouse, irq_mouse_level);
  159. }
  160. static void kbd_update_kbd_irq(void *opaque, int level)
  161. {
  162. KBDState *s = (KBDState *)opaque;
  163. if (level)
  164. s->pending |= KBD_PENDING_KBD;
  165. else
  166. s->pending &= ~KBD_PENDING_KBD;
  167. kbd_update_irq(s);
  168. }
  169. static void kbd_update_aux_irq(void *opaque, int level)
  170. {
  171. KBDState *s = (KBDState *)opaque;
  172. if (level)
  173. s->pending |= KBD_PENDING_AUX;
  174. else
  175. s->pending &= ~KBD_PENDING_AUX;
  176. kbd_update_irq(s);
  177. }
  178. static uint64_t kbd_read_status(void *opaque, hwaddr addr,
  179. unsigned size)
  180. {
  181. KBDState *s = opaque;
  182. int val;
  183. val = s->status;
  184. DPRINTF("kbd: read status=0x%02x\n", val);
  185. return val;
  186. }
  187. static void kbd_queue(KBDState *s, int b, int aux)
  188. {
  189. if (aux)
  190. ps2_queue(s->mouse, b);
  191. else
  192. ps2_queue(s->kbd, b);
  193. }
  194. static void outport_write(KBDState *s, uint32_t val)
  195. {
  196. DPRINTF("kbd: write outport=0x%02x\n", val);
  197. s->outport = val;
  198. if (s->a20_out) {
  199. qemu_set_irq(*s->a20_out, (val >> 1) & 1);
  200. }
  201. if (!(val & 1)) {
  202. qemu_system_reset_request();
  203. }
  204. }
  205. static void kbd_write_command(void *opaque, hwaddr addr,
  206. uint64_t val, unsigned size)
  207. {
  208. KBDState *s = opaque;
  209. DPRINTF("kbd: write cmd=0x%02x\n", val);
  210. /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
  211. * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
  212. * command specify the output port bits to be pulsed.
  213. * 0: Bit should be pulsed. 1: Bit should not be modified.
  214. * The only useful version of this command is pulsing bit 0,
  215. * which does a CPU reset.
  216. */
  217. if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
  218. if(!(val & 1))
  219. val = KBD_CCMD_RESET;
  220. else
  221. val = KBD_CCMD_NO_OP;
  222. }
  223. switch(val) {
  224. case KBD_CCMD_READ_MODE:
  225. kbd_queue(s, s->mode, 0);
  226. break;
  227. case KBD_CCMD_WRITE_MODE:
  228. case KBD_CCMD_WRITE_OBUF:
  229. case KBD_CCMD_WRITE_AUX_OBUF:
  230. case KBD_CCMD_WRITE_MOUSE:
  231. case KBD_CCMD_WRITE_OUTPORT:
  232. s->write_cmd = val;
  233. break;
  234. case KBD_CCMD_MOUSE_DISABLE:
  235. s->mode |= KBD_MODE_DISABLE_MOUSE;
  236. break;
  237. case KBD_CCMD_MOUSE_ENABLE:
  238. s->mode &= ~KBD_MODE_DISABLE_MOUSE;
  239. break;
  240. case KBD_CCMD_TEST_MOUSE:
  241. kbd_queue(s, 0x00, 0);
  242. break;
  243. case KBD_CCMD_SELF_TEST:
  244. s->status |= KBD_STAT_SELFTEST;
  245. kbd_queue(s, 0x55, 0);
  246. break;
  247. case KBD_CCMD_KBD_TEST:
  248. kbd_queue(s, 0x00, 0);
  249. break;
  250. case KBD_CCMD_KBD_DISABLE:
  251. s->mode |= KBD_MODE_DISABLE_KBD;
  252. kbd_update_irq(s);
  253. break;
  254. case KBD_CCMD_KBD_ENABLE:
  255. s->mode &= ~KBD_MODE_DISABLE_KBD;
  256. kbd_update_irq(s);
  257. break;
  258. case KBD_CCMD_READ_INPORT:
  259. kbd_queue(s, 0x00, 0);
  260. break;
  261. case KBD_CCMD_READ_OUTPORT:
  262. kbd_queue(s, s->outport, 0);
  263. break;
  264. case KBD_CCMD_ENABLE_A20:
  265. if (s->a20_out) {
  266. qemu_irq_raise(*s->a20_out);
  267. }
  268. s->outport |= KBD_OUT_A20;
  269. break;
  270. case KBD_CCMD_DISABLE_A20:
  271. if (s->a20_out) {
  272. qemu_irq_lower(*s->a20_out);
  273. }
  274. s->outport &= ~KBD_OUT_A20;
  275. break;
  276. case KBD_CCMD_RESET:
  277. qemu_system_reset_request();
  278. break;
  279. case KBD_CCMD_NO_OP:
  280. /* ignore that */
  281. break;
  282. default:
  283. fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", (int)val);
  284. break;
  285. }
  286. }
  287. static uint64_t kbd_read_data(void *opaque, hwaddr addr,
  288. unsigned size)
  289. {
  290. KBDState *s = opaque;
  291. uint32_t val;
  292. if (s->pending == KBD_PENDING_AUX)
  293. val = ps2_read_data(s->mouse);
  294. else
  295. val = ps2_read_data(s->kbd);
  296. DPRINTF("kbd: read data=0x%02x\n", val);
  297. return val;
  298. }
  299. static void kbd_write_data(void *opaque, hwaddr addr,
  300. uint64_t val, unsigned size)
  301. {
  302. KBDState *s = opaque;
  303. DPRINTF("kbd: write data=0x%02x\n", val);
  304. switch(s->write_cmd) {
  305. case 0:
  306. ps2_write_keyboard(s->kbd, val);
  307. break;
  308. case KBD_CCMD_WRITE_MODE:
  309. s->mode = val;
  310. ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
  311. /* ??? */
  312. kbd_update_irq(s);
  313. break;
  314. case KBD_CCMD_WRITE_OBUF:
  315. kbd_queue(s, val, 0);
  316. break;
  317. case KBD_CCMD_WRITE_AUX_OBUF:
  318. kbd_queue(s, val, 1);
  319. break;
  320. case KBD_CCMD_WRITE_OUTPORT:
  321. outport_write(s, val);
  322. break;
  323. case KBD_CCMD_WRITE_MOUSE:
  324. ps2_write_mouse(s->mouse, val);
  325. break;
  326. default:
  327. break;
  328. }
  329. s->write_cmd = 0;
  330. }
  331. static void kbd_reset(void *opaque)
  332. {
  333. KBDState *s = opaque;
  334. s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
  335. s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
  336. s->outport = KBD_OUT_RESET | KBD_OUT_A20;
  337. }
  338. static const VMStateDescription vmstate_kbd = {
  339. .name = "pckbd",
  340. .version_id = 3,
  341. .minimum_version_id = 3,
  342. .minimum_version_id_old = 3,
  343. .fields = (VMStateField []) {
  344. VMSTATE_UINT8(write_cmd, KBDState),
  345. VMSTATE_UINT8(status, KBDState),
  346. VMSTATE_UINT8(mode, KBDState),
  347. VMSTATE_UINT8(pending, KBDState),
  348. VMSTATE_END_OF_LIST()
  349. }
  350. };
  351. /* Memory mapped interface */
  352. static uint32_t kbd_mm_readb (void *opaque, hwaddr addr)
  353. {
  354. KBDState *s = opaque;
  355. if (addr & s->mask)
  356. return kbd_read_status(s, 0, 1) & 0xff;
  357. else
  358. return kbd_read_data(s, 0, 1) & 0xff;
  359. }
  360. static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value)
  361. {
  362. KBDState *s = opaque;
  363. if (addr & s->mask)
  364. kbd_write_command(s, 0, value & 0xff, 1);
  365. else
  366. kbd_write_data(s, 0, value & 0xff, 1);
  367. }
  368. static const MemoryRegionOps i8042_mmio_ops = {
  369. .endianness = DEVICE_NATIVE_ENDIAN,
  370. .old_mmio = {
  371. .read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb },
  372. .write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb },
  373. },
  374. };
  375. void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
  376. MemoryRegion *region, ram_addr_t size,
  377. hwaddr mask)
  378. {
  379. KBDState *s = g_malloc0(sizeof(KBDState));
  380. s->irq_kbd = kbd_irq;
  381. s->irq_mouse = mouse_irq;
  382. s->mask = mask;
  383. vmstate_register(NULL, 0, &vmstate_kbd, s);
  384. memory_region_init_io(region, &i8042_mmio_ops, s, "i8042", size);
  385. s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
  386. s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
  387. qemu_register_reset(kbd_reset, s);
  388. }
  389. typedef struct ISAKBDState {
  390. ISADevice dev;
  391. KBDState kbd;
  392. MemoryRegion io[2];
  393. } ISAKBDState;
  394. void i8042_isa_mouse_fake_event(void *opaque)
  395. {
  396. ISADevice *dev = opaque;
  397. KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
  398. ps2_mouse_fake_event(s->mouse);
  399. }
  400. void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out)
  401. {
  402. KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
  403. s->a20_out = a20_out;
  404. }
  405. static const VMStateDescription vmstate_kbd_isa = {
  406. .name = "pckbd",
  407. .version_id = 3,
  408. .minimum_version_id = 3,
  409. .minimum_version_id_old = 3,
  410. .fields = (VMStateField []) {
  411. VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
  412. VMSTATE_END_OF_LIST()
  413. }
  414. };
  415. static const MemoryRegionOps i8042_data_ops = {
  416. .read = kbd_read_data,
  417. .write = kbd_write_data,
  418. .impl = {
  419. .min_access_size = 1,
  420. .max_access_size = 1,
  421. },
  422. .endianness = DEVICE_LITTLE_ENDIAN,
  423. };
  424. static const MemoryRegionOps i8042_cmd_ops = {
  425. .read = kbd_read_status,
  426. .write = kbd_write_command,
  427. .impl = {
  428. .min_access_size = 1,
  429. .max_access_size = 1,
  430. },
  431. .endianness = DEVICE_LITTLE_ENDIAN,
  432. };
  433. static int i8042_initfn(ISADevice *dev)
  434. {
  435. ISAKBDState *isa_s = DO_UPCAST(ISAKBDState, dev, dev);
  436. KBDState *s = &isa_s->kbd;
  437. isa_init_irq(dev, &s->irq_kbd, 1);
  438. isa_init_irq(dev, &s->irq_mouse, 12);
  439. memory_region_init_io(isa_s->io + 0, &i8042_data_ops, s, "i8042-data", 1);
  440. isa_register_ioport(dev, isa_s->io + 0, 0x60);
  441. memory_region_init_io(isa_s->io + 1, &i8042_cmd_ops, s, "i8042-cmd", 1);
  442. isa_register_ioport(dev, isa_s->io + 1, 0x64);
  443. s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
  444. s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
  445. qemu_register_reset(kbd_reset, s);
  446. return 0;
  447. }
  448. static void i8042_class_initfn(ObjectClass *klass, void *data)
  449. {
  450. DeviceClass *dc = DEVICE_CLASS(klass);
  451. ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
  452. ic->init = i8042_initfn;
  453. dc->no_user = 1;
  454. dc->vmsd = &vmstate_kbd_isa;
  455. }
  456. static const TypeInfo i8042_info = {
  457. .name = "i8042",
  458. .parent = TYPE_ISA_DEVICE,
  459. .instance_size = sizeof(ISAKBDState),
  460. .class_init = i8042_class_initfn,
  461. };
  462. static void i8042_register_types(void)
  463. {
  464. type_register_static(&i8042_info);
  465. }
  466. type_init(i8042_register_types)