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mips_jazz.c 10 KB

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  1. /*
  2. * QEMU MIPS Jazz support
  3. *
  4. * Copyright (c) 2007-2008 Hervé Poussineau
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "hw.h"
  25. #include "mips.h"
  26. #include "mips_cpudevs.h"
  27. #include "pc.h"
  28. #include "serial.h"
  29. #include "isa.h"
  30. #include "fdc.h"
  31. #include "sysemu/sysemu.h"
  32. #include "sysemu/arch_init.h"
  33. #include "boards.h"
  34. #include "net/net.h"
  35. #include "esp.h"
  36. #include "mips-bios.h"
  37. #include "loader.h"
  38. #include "mc146818rtc.h"
  39. #include "i8254.h"
  40. #include "pcspk.h"
  41. #include "sysemu/blockdev.h"
  42. #include "sysbus.h"
  43. #include "exec/address-spaces.h"
  44. enum jazz_model_e
  45. {
  46. JAZZ_MAGNUM,
  47. JAZZ_PICA61,
  48. };
  49. static void main_cpu_reset(void *opaque)
  50. {
  51. MIPSCPU *cpu = opaque;
  52. cpu_reset(CPU(cpu));
  53. }
  54. static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
  55. {
  56. return cpu_inw(0x71);
  57. }
  58. static void rtc_write(void *opaque, hwaddr addr,
  59. uint64_t val, unsigned size)
  60. {
  61. cpu_outw(0x71, val & 0xff);
  62. }
  63. static const MemoryRegionOps rtc_ops = {
  64. .read = rtc_read,
  65. .write = rtc_write,
  66. .endianness = DEVICE_NATIVE_ENDIAN,
  67. };
  68. static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
  69. unsigned size)
  70. {
  71. /* Nothing to do. That is only to ensure that
  72. * the current DMA acknowledge cycle is completed. */
  73. return 0xff;
  74. }
  75. static void dma_dummy_write(void *opaque, hwaddr addr,
  76. uint64_t val, unsigned size)
  77. {
  78. /* Nothing to do. That is only to ensure that
  79. * the current DMA acknowledge cycle is completed. */
  80. }
  81. static const MemoryRegionOps dma_dummy_ops = {
  82. .read = dma_dummy_read,
  83. .write = dma_dummy_write,
  84. .endianness = DEVICE_NATIVE_ENDIAN,
  85. };
  86. #define MAGNUM_BIOS_SIZE_MAX 0x7e000
  87. #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
  88. static void cpu_request_exit(void *opaque, int irq, int level)
  89. {
  90. CPUMIPSState *env = cpu_single_env;
  91. if (env && level) {
  92. cpu_exit(env);
  93. }
  94. }
  95. static void mips_jazz_init(MemoryRegion *address_space,
  96. MemoryRegion *address_space_io,
  97. ram_addr_t ram_size,
  98. const char *cpu_model,
  99. enum jazz_model_e jazz_model)
  100. {
  101. char *filename;
  102. int bios_size, n;
  103. MIPSCPU *cpu;
  104. CPUMIPSState *env;
  105. qemu_irq *rc4030, *i8259;
  106. rc4030_dma *dmas;
  107. void* rc4030_opaque;
  108. MemoryRegion *rtc = g_new(MemoryRegion, 1);
  109. MemoryRegion *i8042 = g_new(MemoryRegion, 1);
  110. MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
  111. NICInfo *nd;
  112. DeviceState *dev;
  113. SysBusDevice *sysbus;
  114. ISABus *isa_bus;
  115. ISADevice *pit;
  116. DriveInfo *fds[MAX_FD];
  117. qemu_irq esp_reset, dma_enable;
  118. qemu_irq *cpu_exit_irq;
  119. MemoryRegion *ram = g_new(MemoryRegion, 1);
  120. MemoryRegion *bios = g_new(MemoryRegion, 1);
  121. MemoryRegion *bios2 = g_new(MemoryRegion, 1);
  122. /* init CPUs */
  123. if (cpu_model == NULL) {
  124. #ifdef TARGET_MIPS64
  125. cpu_model = "R4000";
  126. #else
  127. /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
  128. cpu_model = "24Kf";
  129. #endif
  130. }
  131. cpu = cpu_mips_init(cpu_model);
  132. if (cpu == NULL) {
  133. fprintf(stderr, "Unable to find CPU definition\n");
  134. exit(1);
  135. }
  136. env = &cpu->env;
  137. qemu_register_reset(main_cpu_reset, cpu);
  138. /* allocate RAM */
  139. memory_region_init_ram(ram, "mips_jazz.ram", ram_size);
  140. vmstate_register_ram_global(ram);
  141. memory_region_add_subregion(address_space, 0, ram);
  142. memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
  143. vmstate_register_ram_global(bios);
  144. memory_region_set_readonly(bios, true);
  145. memory_region_init_alias(bios2, "mips_jazz.bios", bios,
  146. 0, MAGNUM_BIOS_SIZE);
  147. memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
  148. memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
  149. /* load the BIOS image. */
  150. if (bios_name == NULL)
  151. bios_name = BIOS_FILENAME;
  152. filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
  153. if (filename) {
  154. bios_size = load_image_targphys(filename, 0xfff00000LL,
  155. MAGNUM_BIOS_SIZE);
  156. g_free(filename);
  157. } else {
  158. bios_size = -1;
  159. }
  160. if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
  161. fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
  162. bios_name);
  163. exit(1);
  164. }
  165. /* Init CPU internal devices */
  166. cpu_mips_irq_init_cpu(env);
  167. cpu_mips_clock_init(env);
  168. /* Chipset */
  169. rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
  170. address_space);
  171. memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
  172. memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
  173. /* ISA devices */
  174. isa_bus = isa_bus_new(NULL, address_space_io);
  175. i8259 = i8259_init(isa_bus, env->irq[4]);
  176. isa_bus_irqs(isa_bus, i8259);
  177. cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
  178. DMA_init(0, cpu_exit_irq);
  179. pit = pit_init(isa_bus, 0x40, 0, NULL);
  180. pcspk_init(isa_bus, pit);
  181. /* ISA IO space at 0x90000000 */
  182. isa_mmio_init(0x90000000, 0x01000000);
  183. isa_mem_base = 0x11000000;
  184. /* Video card */
  185. switch (jazz_model) {
  186. case JAZZ_MAGNUM:
  187. dev = qdev_create(NULL, "sysbus-g364");
  188. qdev_init_nofail(dev);
  189. sysbus = SYS_BUS_DEVICE(dev);
  190. sysbus_mmio_map(sysbus, 0, 0x60080000);
  191. sysbus_mmio_map(sysbus, 1, 0x40000000);
  192. sysbus_connect_irq(sysbus, 0, rc4030[3]);
  193. {
  194. /* Simple ROM, so user doesn't have to provide one */
  195. MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
  196. memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000);
  197. vmstate_register_ram_global(rom_mr);
  198. memory_region_set_readonly(rom_mr, true);
  199. uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
  200. memory_region_add_subregion(address_space, 0x60000000, rom_mr);
  201. rom[0] = 0x10; /* Mips G364 */
  202. }
  203. break;
  204. case JAZZ_PICA61:
  205. isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
  206. break;
  207. default:
  208. break;
  209. }
  210. /* Network controller */
  211. for (n = 0; n < nb_nics; n++) {
  212. nd = &nd_table[n];
  213. if (!nd->model)
  214. nd->model = g_strdup("dp83932");
  215. if (strcmp(nd->model, "dp83932") == 0) {
  216. dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
  217. rc4030_opaque, rc4030_dma_memory_rw);
  218. break;
  219. } else if (is_help_option(nd->model)) {
  220. fprintf(stderr, "qemu: Supported NICs: dp83932\n");
  221. exit(1);
  222. } else {
  223. fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
  224. exit(1);
  225. }
  226. }
  227. /* SCSI adapter */
  228. esp_init(0x80002000, 0,
  229. rc4030_dma_read, rc4030_dma_write, dmas[0],
  230. rc4030[5], &esp_reset, &dma_enable);
  231. /* Floppy */
  232. if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
  233. fprintf(stderr, "qemu: too many floppy drives\n");
  234. exit(1);
  235. }
  236. for (n = 0; n < MAX_FD; n++) {
  237. fds[n] = drive_get(IF_FLOPPY, 0, n);
  238. }
  239. fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
  240. /* Real time clock */
  241. rtc_init(isa_bus, 1980, NULL);
  242. memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
  243. memory_region_add_subregion(address_space, 0x80004000, rtc);
  244. /* Keyboard (i8042) */
  245. i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
  246. memory_region_add_subregion(address_space, 0x80005000, i8042);
  247. /* Serial ports */
  248. if (serial_hds[0]) {
  249. serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
  250. serial_hds[0], DEVICE_NATIVE_ENDIAN);
  251. }
  252. if (serial_hds[1]) {
  253. serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
  254. serial_hds[1], DEVICE_NATIVE_ENDIAN);
  255. }
  256. /* Parallel port */
  257. if (parallel_hds[0])
  258. parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
  259. parallel_hds[0]);
  260. /* Sound card */
  261. /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
  262. audio_init(isa_bus, NULL);
  263. /* NVRAM */
  264. dev = qdev_create(NULL, "ds1225y");
  265. qdev_init_nofail(dev);
  266. sysbus = SYS_BUS_DEVICE(dev);
  267. sysbus_mmio_map(sysbus, 0, 0x80009000);
  268. /* LED indicator */
  269. sysbus_create_simple("jazz-led", 0x8000f000, NULL);
  270. }
  271. static
  272. void mips_magnum_init(QEMUMachineInitArgs *args)
  273. {
  274. ram_addr_t ram_size = args->ram_size;
  275. const char *cpu_model = args->cpu_model;
  276. mips_jazz_init(get_system_memory(), get_system_io(),
  277. ram_size, cpu_model, JAZZ_MAGNUM);
  278. }
  279. static
  280. void mips_pica61_init(QEMUMachineInitArgs *args)
  281. {
  282. ram_addr_t ram_size = args->ram_size;
  283. const char *cpu_model = args->cpu_model;
  284. mips_jazz_init(get_system_memory(), get_system_io(),
  285. ram_size, cpu_model, JAZZ_PICA61);
  286. }
  287. static QEMUMachine mips_magnum_machine = {
  288. .name = "magnum",
  289. .desc = "MIPS Magnum",
  290. .init = mips_magnum_init,
  291. .block_default_type = IF_SCSI,
  292. DEFAULT_MACHINE_OPTIONS,
  293. };
  294. static QEMUMachine mips_pica61_machine = {
  295. .name = "pica61",
  296. .desc = "Acer Pica 61",
  297. .init = mips_pica61_init,
  298. .block_default_type = IF_SCSI,
  299. DEFAULT_MACHINE_OPTIONS,
  300. };
  301. static void mips_jazz_machine_init(void)
  302. {
  303. qemu_register_machine(&mips_magnum_machine);
  304. qemu_register_machine(&mips_pica61_machine);
  305. }
  306. machine_init(mips_jazz_machine_init);