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cs4231a.c 20 KB

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  1. /*
  2. * QEMU Crystal CS4231 audio chip emulation
  3. *
  4. * Copyright (c) 2006 Fabrice Bellard
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "hw.h"
  25. #include "audiodev.h"
  26. #include "audio/audio.h"
  27. #include "isa.h"
  28. #include "qdev.h"
  29. #include "qemu/timer.h"
  30. /*
  31. Missing features:
  32. ADC
  33. Loopback
  34. Timer
  35. ADPCM
  36. More...
  37. */
  38. /* #define DEBUG */
  39. /* #define DEBUG_XLAW */
  40. static struct {
  41. int aci_counter;
  42. } conf = {1};
  43. #ifdef DEBUG
  44. #define dolog(...) AUD_log ("cs4231a", __VA_ARGS__)
  45. #else
  46. #define dolog(...)
  47. #endif
  48. #define lwarn(...) AUD_log ("cs4231a", "warning: " __VA_ARGS__)
  49. #define lerr(...) AUD_log ("cs4231a", "error: " __VA_ARGS__)
  50. #define CS_REGS 16
  51. #define CS_DREGS 32
  52. typedef struct CSState {
  53. ISADevice dev;
  54. QEMUSoundCard card;
  55. MemoryRegion ioports;
  56. qemu_irq pic;
  57. uint32_t regs[CS_REGS];
  58. uint8_t dregs[CS_DREGS];
  59. uint32_t irq;
  60. uint32_t dma;
  61. uint32_t port;
  62. int shift;
  63. int dma_running;
  64. int audio_free;
  65. int transferred;
  66. int aci_counter;
  67. SWVoiceOut *voice;
  68. int16_t *tab;
  69. } CSState;
  70. #define MODE2 (1 << 6)
  71. #define MCE (1 << 6)
  72. #define PMCE (1 << 4)
  73. #define CMCE (1 << 5)
  74. #define TE (1 << 6)
  75. #define PEN (1 << 0)
  76. #define INT (1 << 0)
  77. #define IEN (1 << 1)
  78. #define PPIO (1 << 6)
  79. #define PI (1 << 4)
  80. #define CI (1 << 5)
  81. #define TI (1 << 6)
  82. enum {
  83. Index_Address,
  84. Index_Data,
  85. Status,
  86. PIO_Data
  87. };
  88. enum {
  89. Left_ADC_Input_Control,
  90. Right_ADC_Input_Control,
  91. Left_AUX1_Input_Control,
  92. Right_AUX1_Input_Control,
  93. Left_AUX2_Input_Control,
  94. Right_AUX2_Input_Control,
  95. Left_DAC_Output_Control,
  96. Right_DAC_Output_Control,
  97. FS_And_Playback_Data_Format,
  98. Interface_Configuration,
  99. Pin_Control,
  100. Error_Status_And_Initialization,
  101. MODE_And_ID,
  102. Loopback_Control,
  103. Playback_Upper_Base_Count,
  104. Playback_Lower_Base_Count,
  105. Alternate_Feature_Enable_I,
  106. Alternate_Feature_Enable_II,
  107. Left_Line_Input_Control,
  108. Right_Line_Input_Control,
  109. Timer_Low_Base,
  110. Timer_High_Base,
  111. RESERVED,
  112. Alternate_Feature_Enable_III,
  113. Alternate_Feature_Status,
  114. Version_Chip_ID,
  115. Mono_Input_And_Output_Control,
  116. RESERVED_2,
  117. Capture_Data_Format,
  118. RESERVED_3,
  119. Capture_Upper_Base_Count,
  120. Capture_Lower_Base_Count
  121. };
  122. static int freqs[2][8] = {
  123. { 8000, 16000, 27420, 32000, -1, -1, 48000, 9000 },
  124. { 5510, 11025, 18900, 22050, 37800, 44100, 33075, 6620 }
  125. };
  126. /* Tables courtesy http://hazelware.luggle.com/tutorials/mulawcompression.html */
  127. static int16_t MuLawDecompressTable[256] =
  128. {
  129. -32124,-31100,-30076,-29052,-28028,-27004,-25980,-24956,
  130. -23932,-22908,-21884,-20860,-19836,-18812,-17788,-16764,
  131. -15996,-15484,-14972,-14460,-13948,-13436,-12924,-12412,
  132. -11900,-11388,-10876,-10364, -9852, -9340, -8828, -8316,
  133. -7932, -7676, -7420, -7164, -6908, -6652, -6396, -6140,
  134. -5884, -5628, -5372, -5116, -4860, -4604, -4348, -4092,
  135. -3900, -3772, -3644, -3516, -3388, -3260, -3132, -3004,
  136. -2876, -2748, -2620, -2492, -2364, -2236, -2108, -1980,
  137. -1884, -1820, -1756, -1692, -1628, -1564, -1500, -1436,
  138. -1372, -1308, -1244, -1180, -1116, -1052, -988, -924,
  139. -876, -844, -812, -780, -748, -716, -684, -652,
  140. -620, -588, -556, -524, -492, -460, -428, -396,
  141. -372, -356, -340, -324, -308, -292, -276, -260,
  142. -244, -228, -212, -196, -180, -164, -148, -132,
  143. -120, -112, -104, -96, -88, -80, -72, -64,
  144. -56, -48, -40, -32, -24, -16, -8, 0,
  145. 32124, 31100, 30076, 29052, 28028, 27004, 25980, 24956,
  146. 23932, 22908, 21884, 20860, 19836, 18812, 17788, 16764,
  147. 15996, 15484, 14972, 14460, 13948, 13436, 12924, 12412,
  148. 11900, 11388, 10876, 10364, 9852, 9340, 8828, 8316,
  149. 7932, 7676, 7420, 7164, 6908, 6652, 6396, 6140,
  150. 5884, 5628, 5372, 5116, 4860, 4604, 4348, 4092,
  151. 3900, 3772, 3644, 3516, 3388, 3260, 3132, 3004,
  152. 2876, 2748, 2620, 2492, 2364, 2236, 2108, 1980,
  153. 1884, 1820, 1756, 1692, 1628, 1564, 1500, 1436,
  154. 1372, 1308, 1244, 1180, 1116, 1052, 988, 924,
  155. 876, 844, 812, 780, 748, 716, 684, 652,
  156. 620, 588, 556, 524, 492, 460, 428, 396,
  157. 372, 356, 340, 324, 308, 292, 276, 260,
  158. 244, 228, 212, 196, 180, 164, 148, 132,
  159. 120, 112, 104, 96, 88, 80, 72, 64,
  160. 56, 48, 40, 32, 24, 16, 8, 0
  161. };
  162. static int16_t ALawDecompressTable[256] =
  163. {
  164. -5504, -5248, -6016, -5760, -4480, -4224, -4992, -4736,
  165. -7552, -7296, -8064, -7808, -6528, -6272, -7040, -6784,
  166. -2752, -2624, -3008, -2880, -2240, -2112, -2496, -2368,
  167. -3776, -3648, -4032, -3904, -3264, -3136, -3520, -3392,
  168. -22016,-20992,-24064,-23040,-17920,-16896,-19968,-18944,
  169. -30208,-29184,-32256,-31232,-26112,-25088,-28160,-27136,
  170. -11008,-10496,-12032,-11520,-8960, -8448, -9984, -9472,
  171. -15104,-14592,-16128,-15616,-13056,-12544,-14080,-13568,
  172. -344, -328, -376, -360, -280, -264, -312, -296,
  173. -472, -456, -504, -488, -408, -392, -440, -424,
  174. -88, -72, -120, -104, -24, -8, -56, -40,
  175. -216, -200, -248, -232, -152, -136, -184, -168,
  176. -1376, -1312, -1504, -1440, -1120, -1056, -1248, -1184,
  177. -1888, -1824, -2016, -1952, -1632, -1568, -1760, -1696,
  178. -688, -656, -752, -720, -560, -528, -624, -592,
  179. -944, -912, -1008, -976, -816, -784, -880, -848,
  180. 5504, 5248, 6016, 5760, 4480, 4224, 4992, 4736,
  181. 7552, 7296, 8064, 7808, 6528, 6272, 7040, 6784,
  182. 2752, 2624, 3008, 2880, 2240, 2112, 2496, 2368,
  183. 3776, 3648, 4032, 3904, 3264, 3136, 3520, 3392,
  184. 22016, 20992, 24064, 23040, 17920, 16896, 19968, 18944,
  185. 30208, 29184, 32256, 31232, 26112, 25088, 28160, 27136,
  186. 11008, 10496, 12032, 11520, 8960, 8448, 9984, 9472,
  187. 15104, 14592, 16128, 15616, 13056, 12544, 14080, 13568,
  188. 344, 328, 376, 360, 280, 264, 312, 296,
  189. 472, 456, 504, 488, 408, 392, 440, 424,
  190. 88, 72, 120, 104, 24, 8, 56, 40,
  191. 216, 200, 248, 232, 152, 136, 184, 168,
  192. 1376, 1312, 1504, 1440, 1120, 1056, 1248, 1184,
  193. 1888, 1824, 2016, 1952, 1632, 1568, 1760, 1696,
  194. 688, 656, 752, 720, 560, 528, 624, 592,
  195. 944, 912, 1008, 976, 816, 784, 880, 848
  196. };
  197. static void cs_reset (void *opaque)
  198. {
  199. CSState *s = opaque;
  200. s->regs[Index_Address] = 0x40;
  201. s->regs[Index_Data] = 0x00;
  202. s->regs[Status] = 0x00;
  203. s->regs[PIO_Data] = 0x00;
  204. s->dregs[Left_ADC_Input_Control] = 0x00;
  205. s->dregs[Right_ADC_Input_Control] = 0x00;
  206. s->dregs[Left_AUX1_Input_Control] = 0x88;
  207. s->dregs[Right_AUX1_Input_Control] = 0x88;
  208. s->dregs[Left_AUX2_Input_Control] = 0x88;
  209. s->dregs[Right_AUX2_Input_Control] = 0x88;
  210. s->dregs[Left_DAC_Output_Control] = 0x80;
  211. s->dregs[Right_DAC_Output_Control] = 0x80;
  212. s->dregs[FS_And_Playback_Data_Format] = 0x00;
  213. s->dregs[Interface_Configuration] = 0x08;
  214. s->dregs[Pin_Control] = 0x00;
  215. s->dregs[Error_Status_And_Initialization] = 0x00;
  216. s->dregs[MODE_And_ID] = 0x8a;
  217. s->dregs[Loopback_Control] = 0x00;
  218. s->dregs[Playback_Upper_Base_Count] = 0x00;
  219. s->dregs[Playback_Lower_Base_Count] = 0x00;
  220. s->dregs[Alternate_Feature_Enable_I] = 0x00;
  221. s->dregs[Alternate_Feature_Enable_II] = 0x00;
  222. s->dregs[Left_Line_Input_Control] = 0x88;
  223. s->dregs[Right_Line_Input_Control] = 0x88;
  224. s->dregs[Timer_Low_Base] = 0x00;
  225. s->dregs[Timer_High_Base] = 0x00;
  226. s->dregs[RESERVED] = 0x00;
  227. s->dregs[Alternate_Feature_Enable_III] = 0x00;
  228. s->dregs[Alternate_Feature_Status] = 0x00;
  229. s->dregs[Version_Chip_ID] = 0xa0;
  230. s->dregs[Mono_Input_And_Output_Control] = 0xa0;
  231. s->dregs[RESERVED_2] = 0x00;
  232. s->dregs[Capture_Data_Format] = 0x00;
  233. s->dregs[RESERVED_3] = 0x00;
  234. s->dregs[Capture_Upper_Base_Count] = 0x00;
  235. s->dregs[Capture_Lower_Base_Count] = 0x00;
  236. }
  237. static void cs_audio_callback (void *opaque, int free)
  238. {
  239. CSState *s = opaque;
  240. s->audio_free = free;
  241. }
  242. static void cs_reset_voices (CSState *s, uint32_t val)
  243. {
  244. int xtal;
  245. struct audsettings as;
  246. #ifdef DEBUG_XLAW
  247. if (val == 0 || val == 32)
  248. val = (1 << 4) | (1 << 5);
  249. #endif
  250. xtal = val & 1;
  251. as.freq = freqs[xtal][(val >> 1) & 7];
  252. if (as.freq == -1) {
  253. lerr ("unsupported frequency (val=%#x)\n", val);
  254. goto error;
  255. }
  256. as.nchannels = (val & (1 << 4)) ? 2 : 1;
  257. as.endianness = 0;
  258. s->tab = NULL;
  259. switch ((val >> 5) & ((s->dregs[MODE_And_ID] & MODE2) ? 7 : 3)) {
  260. case 0:
  261. as.fmt = AUD_FMT_U8;
  262. s->shift = as.nchannels == 2;
  263. break;
  264. case 1:
  265. s->tab = MuLawDecompressTable;
  266. goto x_law;
  267. case 3:
  268. s->tab = ALawDecompressTable;
  269. x_law:
  270. as.fmt = AUD_FMT_S16;
  271. as.endianness = AUDIO_HOST_ENDIANNESS;
  272. s->shift = as.nchannels == 2;
  273. break;
  274. case 6:
  275. as.endianness = 1;
  276. case 2:
  277. as.fmt = AUD_FMT_S16;
  278. s->shift = as.nchannels;
  279. break;
  280. case 7:
  281. case 4:
  282. lerr ("attempt to use reserved format value (%#x)\n", val);
  283. goto error;
  284. case 5:
  285. lerr ("ADPCM 4 bit IMA compatible format is not supported\n");
  286. goto error;
  287. }
  288. s->voice = AUD_open_out (
  289. &s->card,
  290. s->voice,
  291. "cs4231a",
  292. s,
  293. cs_audio_callback,
  294. &as
  295. );
  296. if (s->dregs[Interface_Configuration] & PEN) {
  297. if (!s->dma_running) {
  298. DMA_hold_DREQ (s->dma);
  299. AUD_set_active_out (s->voice, 1);
  300. s->transferred = 0;
  301. }
  302. s->dma_running = 1;
  303. }
  304. else {
  305. if (s->dma_running) {
  306. DMA_release_DREQ (s->dma);
  307. AUD_set_active_out (s->voice, 0);
  308. }
  309. s->dma_running = 0;
  310. }
  311. return;
  312. error:
  313. if (s->dma_running) {
  314. DMA_release_DREQ (s->dma);
  315. AUD_set_active_out (s->voice, 0);
  316. }
  317. }
  318. static uint64_t cs_read (void *opaque, hwaddr addr, unsigned size)
  319. {
  320. CSState *s = opaque;
  321. uint32_t saddr, iaddr, ret;
  322. saddr = addr;
  323. iaddr = ~0U;
  324. switch (saddr) {
  325. case Index_Address:
  326. ret = s->regs[saddr] & ~0x80;
  327. break;
  328. case Index_Data:
  329. if (!(s->dregs[MODE_And_ID] & MODE2))
  330. iaddr = s->regs[Index_Address] & 0x0f;
  331. else
  332. iaddr = s->regs[Index_Address] & 0x1f;
  333. ret = s->dregs[iaddr];
  334. if (iaddr == Error_Status_And_Initialization) {
  335. /* keep SEAL happy */
  336. if (s->aci_counter) {
  337. ret |= 1 << 5;
  338. s->aci_counter -= 1;
  339. }
  340. }
  341. break;
  342. default:
  343. ret = s->regs[saddr];
  344. break;
  345. }
  346. dolog ("read %d:%d -> %d\n", saddr, iaddr, ret);
  347. return ret;
  348. }
  349. static void cs_write (void *opaque, hwaddr addr,
  350. uint64_t val64, unsigned size)
  351. {
  352. CSState *s = opaque;
  353. uint32_t saddr, iaddr, val;
  354. saddr = addr;
  355. val = val64;
  356. switch (saddr) {
  357. case Index_Address:
  358. if (!(s->regs[Index_Address] & MCE) && (val & MCE)
  359. && (s->dregs[Interface_Configuration] & (3 << 3)))
  360. s->aci_counter = conf.aci_counter;
  361. s->regs[Index_Address] = val & ~(1 << 7);
  362. break;
  363. case Index_Data:
  364. if (!(s->dregs[MODE_And_ID] & MODE2))
  365. iaddr = s->regs[Index_Address] & 0x0f;
  366. else
  367. iaddr = s->regs[Index_Address] & 0x1f;
  368. switch (iaddr) {
  369. case RESERVED:
  370. case RESERVED_2:
  371. case RESERVED_3:
  372. lwarn ("attempt to write %#x to reserved indirect register %d\n",
  373. val, iaddr);
  374. break;
  375. case FS_And_Playback_Data_Format:
  376. if (s->regs[Index_Address] & MCE) {
  377. cs_reset_voices (s, val);
  378. }
  379. else {
  380. if (s->dregs[Alternate_Feature_Status] & PMCE) {
  381. val = (val & ~0x0f) | (s->dregs[iaddr] & 0x0f);
  382. cs_reset_voices (s, val);
  383. }
  384. else {
  385. lwarn ("[P]MCE(%#x, %#x) is not set, val=%#x\n",
  386. s->regs[Index_Address],
  387. s->dregs[Alternate_Feature_Status],
  388. val);
  389. break;
  390. }
  391. }
  392. s->dregs[iaddr] = val;
  393. break;
  394. case Interface_Configuration:
  395. val &= ~(1 << 5); /* D5 is reserved */
  396. s->dregs[iaddr] = val;
  397. if (val & PPIO) {
  398. lwarn ("PIO is not supported (%#x)\n", val);
  399. break;
  400. }
  401. if (val & PEN) {
  402. if (!s->dma_running) {
  403. cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]);
  404. }
  405. }
  406. else {
  407. if (s->dma_running) {
  408. DMA_release_DREQ (s->dma);
  409. AUD_set_active_out (s->voice, 0);
  410. s->dma_running = 0;
  411. }
  412. }
  413. break;
  414. case Error_Status_And_Initialization:
  415. lwarn ("attempt to write to read only register %d\n", iaddr);
  416. break;
  417. case MODE_And_ID:
  418. dolog ("val=%#x\n", val);
  419. if (val & MODE2)
  420. s->dregs[iaddr] |= MODE2;
  421. else
  422. s->dregs[iaddr] &= ~MODE2;
  423. break;
  424. case Alternate_Feature_Enable_I:
  425. if (val & TE)
  426. lerr ("timer is not yet supported\n");
  427. s->dregs[iaddr] = val;
  428. break;
  429. case Alternate_Feature_Status:
  430. if ((s->dregs[iaddr] & PI) && !(val & PI)) {
  431. /* XXX: TI CI */
  432. qemu_irq_lower (s->pic);
  433. s->regs[Status] &= ~INT;
  434. }
  435. s->dregs[iaddr] = val;
  436. break;
  437. case Version_Chip_ID:
  438. lwarn ("write to Version_Chip_ID register %#x\n", val);
  439. s->dregs[iaddr] = val;
  440. break;
  441. default:
  442. s->dregs[iaddr] = val;
  443. break;
  444. }
  445. dolog ("written value %#x to indirect register %d\n", val, iaddr);
  446. break;
  447. case Status:
  448. if (s->regs[Status] & INT) {
  449. qemu_irq_lower (s->pic);
  450. }
  451. s->regs[Status] &= ~INT;
  452. s->dregs[Alternate_Feature_Status] &= ~(PI | CI | TI);
  453. break;
  454. case PIO_Data:
  455. lwarn ("attempt to write value %#x to PIO register\n", val);
  456. break;
  457. }
  458. }
  459. static int cs_write_audio (CSState *s, int nchan, int dma_pos,
  460. int dma_len, int len)
  461. {
  462. int temp, net;
  463. uint8_t tmpbuf[4096];
  464. temp = len;
  465. net = 0;
  466. while (temp) {
  467. int left = dma_len - dma_pos;
  468. int copied;
  469. size_t to_copy;
  470. to_copy = audio_MIN (temp, left);
  471. if (to_copy > sizeof (tmpbuf)) {
  472. to_copy = sizeof (tmpbuf);
  473. }
  474. copied = DMA_read_memory (nchan, tmpbuf, dma_pos, to_copy);
  475. if (s->tab) {
  476. int i;
  477. int16_t linbuf[4096];
  478. for (i = 0; i < copied; ++i)
  479. linbuf[i] = s->tab[tmpbuf[i]];
  480. copied = AUD_write (s->voice, linbuf, copied << 1);
  481. copied >>= 1;
  482. }
  483. else {
  484. copied = AUD_write (s->voice, tmpbuf, copied);
  485. }
  486. temp -= copied;
  487. dma_pos = (dma_pos + copied) % dma_len;
  488. net += copied;
  489. if (!copied) {
  490. break;
  491. }
  492. }
  493. return net;
  494. }
  495. static int cs_dma_read (void *opaque, int nchan, int dma_pos, int dma_len)
  496. {
  497. CSState *s = opaque;
  498. int copy, written;
  499. int till = -1;
  500. copy = s->voice ? (s->audio_free >> (s->tab != NULL)) : dma_len;
  501. if (s->dregs[Pin_Control] & IEN) {
  502. till = (s->dregs[Playback_Lower_Base_Count]
  503. | (s->dregs[Playback_Upper_Base_Count] << 8)) << s->shift;
  504. till -= s->transferred;
  505. copy = audio_MIN (till, copy);
  506. }
  507. if ((copy <= 0) || (dma_len <= 0)) {
  508. return dma_pos;
  509. }
  510. written = cs_write_audio (s, nchan, dma_pos, dma_len, copy);
  511. dma_pos = (dma_pos + written) % dma_len;
  512. s->audio_free -= (written << (s->tab != NULL));
  513. if (written == till) {
  514. s->regs[Status] |= INT;
  515. s->dregs[Alternate_Feature_Status] |= PI;
  516. s->transferred = 0;
  517. qemu_irq_raise (s->pic);
  518. }
  519. else {
  520. s->transferred += written;
  521. }
  522. return dma_pos;
  523. }
  524. static int cs4231a_pre_load (void *opaque)
  525. {
  526. CSState *s = opaque;
  527. if (s->dma_running) {
  528. DMA_release_DREQ (s->dma);
  529. AUD_set_active_out (s->voice, 0);
  530. }
  531. s->dma_running = 0;
  532. return 0;
  533. }
  534. static int cs4231a_post_load (void *opaque, int version_id)
  535. {
  536. CSState *s = opaque;
  537. if (s->dma_running && (s->dregs[Interface_Configuration] & PEN)) {
  538. s->dma_running = 0;
  539. cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]);
  540. }
  541. return 0;
  542. }
  543. static const VMStateDescription vmstate_cs4231a = {
  544. .name = "cs4231a",
  545. .version_id = 1,
  546. .minimum_version_id = 1,
  547. .minimum_version_id_old = 1,
  548. .pre_load = cs4231a_pre_load,
  549. .post_load = cs4231a_post_load,
  550. .fields = (VMStateField []) {
  551. VMSTATE_UINT32_ARRAY (regs, CSState, CS_REGS),
  552. VMSTATE_BUFFER (dregs, CSState),
  553. VMSTATE_INT32 (dma_running, CSState),
  554. VMSTATE_INT32 (audio_free, CSState),
  555. VMSTATE_INT32 (transferred, CSState),
  556. VMSTATE_INT32 (aci_counter, CSState),
  557. VMSTATE_END_OF_LIST ()
  558. }
  559. };
  560. static const MemoryRegionOps cs_ioport_ops = {
  561. .read = cs_read,
  562. .write = cs_write,
  563. .impl = {
  564. .min_access_size = 1,
  565. .max_access_size = 1,
  566. }
  567. };
  568. static int cs4231a_initfn (ISADevice *dev)
  569. {
  570. CSState *s = DO_UPCAST (CSState, dev, dev);
  571. isa_init_irq (dev, &s->pic, s->irq);
  572. memory_region_init_io (&s->ioports, &cs_ioport_ops, s, "cs4231a", 4);
  573. isa_register_ioport (dev, &s->ioports, s->port);
  574. DMA_register_channel (s->dma, cs_dma_read, s);
  575. qemu_register_reset (cs_reset, s);
  576. cs_reset (s);
  577. AUD_register_card ("cs4231a", &s->card);
  578. return 0;
  579. }
  580. int cs4231a_init (ISABus *bus)
  581. {
  582. isa_create_simple (bus, "cs4231a");
  583. return 0;
  584. }
  585. static Property cs4231a_properties[] = {
  586. DEFINE_PROP_HEX32 ("iobase", CSState, port, 0x534),
  587. DEFINE_PROP_UINT32 ("irq", CSState, irq, 9),
  588. DEFINE_PROP_UINT32 ("dma", CSState, dma, 3),
  589. DEFINE_PROP_END_OF_LIST (),
  590. };
  591. static void cs4231a_class_initfn (ObjectClass *klass, void *data)
  592. {
  593. DeviceClass *dc = DEVICE_CLASS (klass);
  594. ISADeviceClass *ic = ISA_DEVICE_CLASS (klass);
  595. ic->init = cs4231a_initfn;
  596. dc->desc = "Crystal Semiconductor CS4231A";
  597. dc->vmsd = &vmstate_cs4231a;
  598. dc->props = cs4231a_properties;
  599. }
  600. static const TypeInfo cs4231a_info = {
  601. .name = "cs4231a",
  602. .parent = TYPE_ISA_DEVICE,
  603. .instance_size = sizeof (CSState),
  604. .class_init = cs4231a_class_initfn,
  605. };
  606. static void cs4231a_register_types (void)
  607. {
  608. type_register_static (&cs4231a_info);
  609. }
  610. type_init (cs4231a_register_types)