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sparc-dis.c 172 KB

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  1. /*
  2. * These files from binutils are concatenated:
  3. * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
  4. */
  5. /* include/opcode/sparc.h */
  6. /* Definitions for opcode table for the sparc.
  7. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
  8. 2003, 2005 Free Software Foundation, Inc.
  9. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
  10. the GNU Binutils.
  11. GAS/GDB is free software; you can redistribute it and/or modify
  12. it under the terms of the GNU General Public License as published by
  13. the Free Software Foundation; either version 2, or (at your option)
  14. any later version.
  15. GAS/GDB is distributed in the hope that it will be useful,
  16. but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. GNU General Public License for more details.
  19. You should have received a copy of the GNU General Public License
  20. along with GAS or GDB; see the file COPYING. If not,
  21. see <http://www.gnu.org/licenses/>. */
  22. #include <stdlib.h>
  23. #include "dis-asm.h"
  24. /* The SPARC opcode table (and other related data) is defined in
  25. the opcodes library in sparc-opc.c. If you change anything here, make
  26. sure you fix up that file, and vice versa. */
  27. /* FIXME-someday: perhaps the ,a's and such should be embedded in the
  28. instruction's name rather than the args. This would make gas faster, pinsn
  29. slower, but would mess up some macros a bit. xoxorich. */
  30. /* List of instruction sets variations.
  31. These values are such that each element is either a superset of a
  32. preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
  33. returns non-zero.
  34. The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
  35. Don't change this without updating sparc-opc.c. */
  36. enum sparc_opcode_arch_val
  37. {
  38. SPARC_OPCODE_ARCH_V6 = 0,
  39. SPARC_OPCODE_ARCH_V7,
  40. SPARC_OPCODE_ARCH_V8,
  41. SPARC_OPCODE_ARCH_SPARCLET,
  42. SPARC_OPCODE_ARCH_SPARCLITE,
  43. /* V9 variants must appear last. */
  44. SPARC_OPCODE_ARCH_V9,
  45. SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
  46. SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
  47. SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
  48. };
  49. /* The highest architecture in the table. */
  50. #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
  51. /* Given an enum sparc_opcode_arch_val, return the bitmask to use in
  52. insn encoding/decoding. */
  53. #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
  54. /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
  55. #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
  56. /* Table of cpu variants. */
  57. typedef struct sparc_opcode_arch
  58. {
  59. const char *name;
  60. /* Mask of sparc_opcode_arch_val's supported.
  61. EG: For v7 this would be
  62. (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
  63. These are short's because sparc_opcode.architecture is. */
  64. short supported;
  65. } sparc_opcode_arch;
  66. static const struct sparc_opcode_arch sparc_opcode_archs[];
  67. /* Return the bitmask of supported architectures for ARCH. */
  68. #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
  69. /* Non-zero if ARCH1 conflicts with ARCH2.
  70. IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
  71. #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
  72. (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
  73. != SPARC_OPCODE_SUPPORTED (ARCH1)) \
  74. && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
  75. != SPARC_OPCODE_SUPPORTED (ARCH2)))
  76. /* Structure of an opcode table entry. */
  77. typedef struct sparc_opcode
  78. {
  79. const char *name;
  80. unsigned long match; /* Bits that must be set. */
  81. unsigned long lose; /* Bits that must not be set. */
  82. const char *args;
  83. /* This was called "delayed" in versions before the flags. */
  84. char flags;
  85. short architecture; /* Bitmask of sparc_opcode_arch_val's. */
  86. } sparc_opcode;
  87. #define F_DELAYED 1 /* Delayed branch. */
  88. #define F_ALIAS 2 /* Alias for a "real" instruction. */
  89. #define F_UNBR 4 /* Unconditional branch. */
  90. #define F_CONDBR 8 /* Conditional branch. */
  91. #define F_JSR 16 /* Subroutine call. */
  92. #define F_FLOAT 32 /* Floating point instruction (not a branch). */
  93. #define F_FBR 64 /* Floating point branch. */
  94. /* FIXME: Add F_ANACHRONISTIC flag for v9. */
  95. /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
  96. macro), which is 64 bits. It is handled as a special case.
  97. The match component is a mask saying which bits must match a particular
  98. opcode in order for an instruction to be an instance of that opcode.
  99. The args component is a string containing one character for each operand of the
  100. instruction.
  101. Kinds of operands:
  102. # Number used by optimizer. It is ignored.
  103. 1 rs1 register.
  104. 2 rs2 register.
  105. d rd register.
  106. e frs1 floating point register.
  107. v frs1 floating point register (double/even).
  108. V frs1 floating point register (quad/multiple of 4).
  109. f frs2 floating point register.
  110. B frs2 floating point register (double/even).
  111. R frs2 floating point register (quad/multiple of 4).
  112. g frsd floating point register.
  113. H frsd floating point register (double/even).
  114. J frsd floating point register (quad/multiple of 4).
  115. b crs1 coprocessor register
  116. c crs2 coprocessor register
  117. D crsd coprocessor register
  118. m alternate space register (asr) in rd
  119. M alternate space register (asr) in rs1
  120. h 22 high bits.
  121. X 5 bit unsigned immediate
  122. Y 6 bit unsigned immediate
  123. 3 SIAM mode (3 bits). (v9b)
  124. K MEMBAR mask (7 bits). (v9)
  125. j 10 bit Immediate. (v9)
  126. I 11 bit Immediate. (v9)
  127. i 13 bit Immediate.
  128. n 22 bit immediate.
  129. k 2+14 bit PC relative immediate. (v9)
  130. G 19 bit PC relative immediate. (v9)
  131. l 22 bit PC relative immediate.
  132. L 30 bit PC relative immediate.
  133. a Annul. The annul bit is set.
  134. A Alternate address space. Stored as 8 bits.
  135. C Coprocessor state register.
  136. F floating point state register.
  137. p Processor state register.
  138. N Branch predict clear ",pn" (v9)
  139. T Branch predict set ",pt" (v9)
  140. z %icc. (v9)
  141. Z %xcc. (v9)
  142. q Floating point queue.
  143. r Single register that is both rs1 and rd.
  144. O Single register that is both rs2 and rd.
  145. Q Coprocessor queue.
  146. S Special case.
  147. t Trap base register.
  148. w Window invalid mask register.
  149. y Y register.
  150. u sparclet coprocessor registers in rd position
  151. U sparclet coprocessor registers in rs1 position
  152. E %ccr. (v9)
  153. s %fprs. (v9)
  154. P %pc. (v9)
  155. W %tick. (v9)
  156. o %asi. (v9)
  157. 6 %fcc0. (v9)
  158. 7 %fcc1. (v9)
  159. 8 %fcc2. (v9)
  160. 9 %fcc3. (v9)
  161. ! Privileged Register in rd (v9)
  162. ? Privileged Register in rs1 (v9)
  163. * Prefetch function constant. (v9)
  164. x OPF field (v9 impdep).
  165. 0 32/64 bit immediate for set or setx (v9) insns
  166. _ Ancillary state register in rd (v9a)
  167. / Ancillary state register in rs1 (v9a)
  168. The following chars are unused: (note: ,[] are used as punctuation)
  169. [45]. */
  170. #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
  171. #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
  172. #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
  173. #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
  174. #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
  175. #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
  176. #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
  177. #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
  178. #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
  179. #define F1(x) (OP (x))
  180. #define DISP30(x) ((x) & 0x3fffffff)
  181. #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
  182. #define RS2(x) ((x) & 0x1f) /* Rs2 field. */
  183. #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
  184. #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
  185. #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
  186. #define ASI_RS2(x) (SIMM13 (x))
  187. #define MEMBAR(x) ((x) & 0x7f)
  188. #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
  189. #define ANNUL (1 << 29)
  190. #define BPRED (1 << 19) /* V9. */
  191. #define IMMED F3I (1)
  192. #define RD_G0 RD (~0)
  193. #define RS1_G0 RS1 (~0)
  194. #define RS2_G0 RS2 (~0)
  195. static const struct sparc_opcode sparc_opcodes[];
  196. static const char *sparc_decode_asi_v8 (int);
  197. static const char *sparc_decode_asi_v9 (int);
  198. static const char *sparc_decode_membar (int);
  199. static const char *sparc_decode_prefetch (int);
  200. static const char *sparc_decode_sparclet_cpreg (int);
  201. /* Local Variables:
  202. fill-column: 131
  203. comment-column: 0
  204. End: */
  205. /* opcodes/sparc-opc.c */
  206. /* Table of opcodes for the sparc.
  207. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
  208. 2000, 2002, 2004, 2005
  209. Free Software Foundation, Inc.
  210. This file is part of the BFD library.
  211. BFD is free software; you can redistribute it and/or modify it under
  212. the terms of the GNU General Public License as published by the Free
  213. Software Foundation; either version 2, or (at your option) any later
  214. version.
  215. BFD is distributed in the hope that it will be useful, but WITHOUT ANY
  216. WARRANTY; without even the implied warranty of MERCHANTABILITY or
  217. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  218. for more details.
  219. You should have received a copy of the GNU General Public License
  220. along with this software; see the file COPYING. If not,
  221. see <http://www.gnu.org/licenses/>. */
  222. /* FIXME-someday: perhaps the ,a's and such should be embedded in the
  223. instruction's name rather than the args. This would make gas faster, pinsn
  224. slower, but would mess up some macros a bit. xoxorich. */
  225. /* Some defines to make life easy. */
  226. #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
  227. #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
  228. #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
  229. #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
  230. #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
  231. #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
  232. #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
  233. #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
  234. /* Bit masks of architectures supporting the insn. */
  235. #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
  236. | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
  237. /* v6 insns not supported on the sparclet. */
  238. #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
  239. | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
  240. #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
  241. | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
  242. /* Although not all insns are implemented in hardware, sparclite is defined
  243. to be a superset of v8. Unimplemented insns trap and are then theoretically
  244. implemented in software.
  245. It's not clear that the same is true for sparclet, although the docs
  246. suggest it is. Rather than complicating things, the sparclet assembler
  247. recognizes all v8 insns. */
  248. #define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
  249. | MASK_V9 | MASK_V9A | MASK_V9B)
  250. #define sparclet (MASK_SPARCLET)
  251. #define sparclite (MASK_SPARCLITE)
  252. #define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
  253. #define v9a (MASK_V9A | MASK_V9B)
  254. #define v9b (MASK_V9B)
  255. /* v6 insns not supported by v9. */
  256. #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
  257. | MASK_SPARCLET | MASK_SPARCLITE)
  258. /* v9a instructions which would appear to be aliases to v9's impdep's
  259. otherwise. */
  260. #define v9notv9a (MASK_V9)
  261. /* Table of opcode architectures.
  262. The order is defined in opcode/sparc.h. */
  263. static const struct sparc_opcode_arch sparc_opcode_archs[] =
  264. {
  265. { "v6", MASK_V6 },
  266. { "v7", MASK_V6 | MASK_V7 },
  267. { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
  268. { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
  269. { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
  270. /* ??? Don't some v8 privileged insns conflict with v9? */
  271. { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
  272. /* v9 with ultrasparc additions */
  273. { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
  274. /* v9 with cheetah additions */
  275. { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
  276. { NULL, 0 }
  277. };
  278. /* Branch condition field. */
  279. #define COND(x) (((x) & 0xf) << 25)
  280. /* v9: Move (MOVcc and FMOVcc) condition field. */
  281. #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
  282. /* v9: Move register (MOVRcc and FMOVRcc) condition field. */
  283. #define RCOND(x) (((x) & 0x7) << 10) /* v9 */
  284. #define CONDA (COND (0x8))
  285. #define CONDCC (COND (0xd))
  286. #define CONDCS (COND (0x5))
  287. #define CONDE (COND (0x1))
  288. #define CONDG (COND (0xa))
  289. #define CONDGE (COND (0xb))
  290. #define CONDGU (COND (0xc))
  291. #define CONDL (COND (0x3))
  292. #define CONDLE (COND (0x2))
  293. #define CONDLEU (COND (0x4))
  294. #define CONDN (COND (0x0))
  295. #define CONDNE (COND (0x9))
  296. #define CONDNEG (COND (0x6))
  297. #define CONDPOS (COND (0xe))
  298. #define CONDVC (COND (0xf))
  299. #define CONDVS (COND (0x7))
  300. #define CONDNZ CONDNE
  301. #define CONDZ CONDE
  302. #define CONDGEU CONDCC
  303. #define CONDLU CONDCS
  304. #define FCONDA (COND (0x8))
  305. #define FCONDE (COND (0x9))
  306. #define FCONDG (COND (0x6))
  307. #define FCONDGE (COND (0xb))
  308. #define FCONDL (COND (0x4))
  309. #define FCONDLE (COND (0xd))
  310. #define FCONDLG (COND (0x2))
  311. #define FCONDN (COND (0x0))
  312. #define FCONDNE (COND (0x1))
  313. #define FCONDO (COND (0xf))
  314. #define FCONDU (COND (0x7))
  315. #define FCONDUE (COND (0xa))
  316. #define FCONDUG (COND (0x5))
  317. #define FCONDUGE (COND (0xc))
  318. #define FCONDUL (COND (0x3))
  319. #define FCONDULE (COND (0xe))
  320. #define FCONDNZ FCONDNE
  321. #define FCONDZ FCONDE
  322. #define ICC (0) /* v9 */
  323. #define XCC (1 << 12) /* v9 */
  324. #define FCC(x) (((x) & 0x3) << 11) /* v9 */
  325. #define FBFCC(x) (((x) & 0x3) << 20) /* v9 */
  326. /* The order of the opcodes in the table is significant:
  327. * The assembler requires that all instances of the same mnemonic must
  328. be consecutive. If they aren't, the assembler will bomb at runtime.
  329. * The disassembler should not care about the order of the opcodes. */
  330. /* Entries for commutative arithmetic operations. */
  331. /* ??? More entries can make use of this. */
  332. #define COMMUTEOP(opcode, op3, arch_mask) \
  333. { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \
  334. { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \
  335. { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask }
  336. static const struct sparc_opcode sparc_opcodes[] = {
  337. { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 },
  338. { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
  339. { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 },
  340. { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 },
  341. { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 },
  342. { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */
  343. { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 },
  344. { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
  345. { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 },
  346. { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 },
  347. { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 },
  348. { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */
  349. { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 },
  350. { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
  351. { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 },
  352. { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 },
  353. { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
  354. { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
  355. { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 },
  356. { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */
  357. { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 },
  358. { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 },
  359. { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
  360. { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */
  361. { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 },
  362. { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */
  363. { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 },
  364. { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 },
  365. { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 },
  366. { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */
  367. /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
  368. 'ld' pseudo-op in v9. */
  369. { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 },
  370. { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */
  371. { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 },
  372. { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 },
  373. { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 },
  374. { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */
  375. { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 },
  376. { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
  377. { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 },
  378. { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 },
  379. { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 },
  380. { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */
  381. { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 },
  382. { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */
  383. { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 },
  384. { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 },
  385. { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 },
  386. { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */
  387. { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 },
  388. { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */
  389. { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 },
  390. { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 },
  391. { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
  392. { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */
  393. { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 },
  394. { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */
  395. { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 },
  396. { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 },
  397. { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 },
  398. { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */
  399. { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 },
  400. { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
  401. { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 },
  402. { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 },
  403. { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 },
  404. { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */
  405. { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
  406. { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 },
  407. { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 },
  408. { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 },
  409. { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 },
  410. { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */
  411. { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 },
  412. { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
  413. { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 },
  414. { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 },
  415. { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 },
  416. { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */
  417. { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 },
  418. { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */
  419. { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 },
  420. { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 },
  421. { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 },
  422. { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */
  423. { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 },
  424. { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
  425. { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 },
  426. { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 },
  427. { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 },
  428. { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */
  429. { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 },
  430. { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
  431. { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 },
  432. { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 },
  433. { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 },
  434. { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */
  435. { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 },
  436. { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */
  437. { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 },
  438. { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 },
  439. { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 },
  440. { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */
  441. { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 },
  442. { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */
  443. { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 },
  444. { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 },
  445. { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 },
  446. { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
  447. { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 },
  448. { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
  449. { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 },
  450. { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 },
  451. { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  452. { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  453. { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 },
  454. { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */
  455. { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 },
  456. { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 },
  457. { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 },
  458. { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */
  459. { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 },
  460. { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
  461. { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 },
  462. { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 },
  463. { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  464. { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  465. { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 },
  466. { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */
  467. { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 },
  468. { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 },
  469. { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 },
  470. { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */
  471. { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 },
  472. { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */
  473. { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 },
  474. { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 },
  475. { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 },
  476. { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */
  477. { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 },
  478. { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
  479. { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 },
  480. { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 },
  481. { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  482. { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  483. { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 },
  484. { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
  485. { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 },
  486. { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 },
  487. { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  488. { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  489. { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 },
  490. { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
  491. { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 },
  492. { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 },
  493. { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  494. { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  495. { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 },
  496. { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
  497. { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 },
  498. { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 },
  499. { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  500. { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  501. { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 },
  502. { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
  503. { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 },
  504. { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 },
  505. { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  506. { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  507. { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 },
  508. { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
  509. { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 },
  510. { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 },
  511. { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  512. { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  513. { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */
  514. { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */
  515. { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 },
  516. { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 },
  517. { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 },
  518. { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */
  519. { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 },
  520. { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
  521. { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 },
  522. { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 },
  523. { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  524. { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  525. { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
  526. { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
  527. { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 },
  528. { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 },
  529. { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 },
  530. { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */
  531. { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 },
  532. { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
  533. { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 },
  534. { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 },
  535. { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 },
  536. { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */
  537. { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
  538. { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
  539. { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 },
  540. { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 },
  541. { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
  542. { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
  543. { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 },
  544. { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
  545. { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 },
  546. { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 },
  547. { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 },
  548. { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
  549. { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 },
  550. { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
  551. { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 },
  552. { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 },
  553. { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 },
  554. { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */
  555. { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
  556. { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
  557. { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
  558. { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
  559. { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
  560. { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
  561. { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
  562. { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
  563. { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
  564. { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
  565. { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
  566. { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
  567. { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
  568. { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
  569. { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
  570. { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
  571. { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
  572. { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
  573. { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
  574. { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */
  575. { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 },
  576. { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 },
  577. { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
  578. { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */
  579. { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 },
  580. { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
  581. { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 },
  582. { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 },
  583. { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 },
  584. { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */
  585. { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 },
  586. { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */
  587. { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 },
  588. { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 },
  589. { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 },
  590. { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */
  591. { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
  592. { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
  593. { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
  594. { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
  595. { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
  596. { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
  597. { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
  598. { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
  599. { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
  600. { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
  601. { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
  602. { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
  603. { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
  604. { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
  605. { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
  606. { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
  607. { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
  608. { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
  609. { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
  610. { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
  611. { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 },
  612. { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 },
  613. { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 },
  614. { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */
  615. { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
  616. { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
  617. { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
  618. { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
  619. { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
  620. { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
  621. { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
  622. { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
  623. { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
  624. { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
  625. { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
  626. { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
  627. { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 },
  628. { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
  629. { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 },
  630. { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 },
  631. { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 },
  632. { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */
  633. { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
  634. { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
  635. { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
  636. { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
  637. { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
  638. { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
  639. { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
  640. { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
  641. { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
  642. { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
  643. { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
  644. { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
  645. { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
  646. { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
  647. { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 },
  648. { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 },
  649. { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 },
  650. { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */
  651. { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 },
  652. { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
  653. { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 },
  654. { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 },
  655. { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 },
  656. { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
  657. { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 },
  658. { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */
  659. { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 },
  660. { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 },
  661. { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 },
  662. { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */
  663. { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 },
  664. { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
  665. { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 },
  666. { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 },
  667. { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 },
  668. { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
  669. { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
  670. { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
  671. { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 },
  672. { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 },
  673. { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
  674. { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
  675. { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
  676. { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
  677. { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 },
  678. { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 },
  679. { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
  680. { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
  681. { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 },
  682. { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
  683. { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 },
  684. { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 },
  685. { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 },
  686. { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */
  687. { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 },
  688. { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */
  689. { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 },
  690. { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 },
  691. { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 },
  692. { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */
  693. { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
  694. { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
  695. { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 },
  696. { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 },
  697. { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 },
  698. { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */
  699. { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
  700. { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
  701. { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
  702. { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
  703. { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
  704. { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
  705. { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
  706. { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
  707. { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
  708. { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
  709. { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
  710. { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
  711. { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 },
  712. { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */
  713. { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 },
  714. { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 },
  715. { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 },
  716. { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */
  717. { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
  718. { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
  719. { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
  720. { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
  721. { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
  722. { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
  723. { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
  724. { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
  725. { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
  726. { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
  727. { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
  728. { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
  729. { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 },
  730. { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
  731. { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 },
  732. { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 },
  733. { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 },
  734. { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */
  735. { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 },
  736. { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
  737. { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 },
  738. { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 },
  739. { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 },
  740. { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
  741. { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 },
  742. { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */
  743. { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 },
  744. { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 },
  745. { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 },
  746. { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */
  747. { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 },
  748. { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */
  749. { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 },
  750. { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 },
  751. { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 },
  752. { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */
  753. { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 },
  754. { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */
  755. { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 },
  756. { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 },
  757. { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 },
  758. { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */
  759. { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 },
  760. { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
  761. { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 },
  762. { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 },
  763. { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 },
  764. { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */
  765. { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 },
  766. { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
  767. { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 },
  768. { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 },
  769. { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 },
  770. { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */
  771. { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 },
  772. { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */
  773. { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 },
  774. { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */
  775. { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
  776. { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */
  777. { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
  778. { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
  779. { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
  780. { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */
  781. { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */
  782. { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 },
  783. { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 },
  784. { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 },
  785. { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
  786. { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
  787. { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 },
  788. { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
  789. { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
  790. { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
  791. { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 },
  792. { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 },
  793. { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
  794. { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
  795. { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
  796. { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
  797. { "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, v9 },
  798. { "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, v9 },
  799. { "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, v9 },
  800. { "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, v9 },
  801. { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 },
  802. { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
  803. { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */
  804. { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */
  805. { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */
  806. { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 },
  807. { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 },
  808. /* IFLUSH was renamed to FLUSH in v8. */
  809. { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 },
  810. { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */
  811. { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */
  812. { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 },
  813. { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 },
  814. { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 },
  815. { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 },
  816. { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */
  817. { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */
  818. { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */
  819. { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 },
  820. { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 },
  821. { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 },
  822. { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
  823. { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
  824. { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 },
  825. { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
  826. { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 },
  827. { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 },
  828. { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 },
  829. { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
  830. { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 },
  831. { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
  832. { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 },
  833. { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 },
  834. { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 },
  835. { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */
  836. { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
  837. { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
  838. { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
  839. { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
  840. { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
  841. { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
  842. { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
  843. { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
  844. { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
  845. { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
  846. { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
  847. { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
  848. { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 },
  849. { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 },
  850. { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite },
  851. { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite },
  852. { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite },
  853. { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite },
  854. { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
  855. { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 },
  856. { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
  857. { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */
  858. { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
  859. { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
  860. { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
  861. { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
  862. { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
  863. { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
  864. { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
  865. { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
  866. { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
  867. { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
  868. { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
  869. { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
  870. { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
  871. { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
  872. { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
  873. { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
  874. { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
  875. { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
  876. { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 },
  877. { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
  878. { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 },
  879. { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 },
  880. { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 },
  881. { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
  882. { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 },
  883. { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 },
  884. { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 },
  885. /* This is not a commutative instruction. */
  886. { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 },
  887. { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 },
  888. /* This is not a commutative instruction. */
  889. { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 },
  890. { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 },
  891. { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */
  892. { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */
  893. { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */
  894. { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */
  895. { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */
  896. { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
  897. { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */
  898. { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */
  899. { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
  900. { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
  901. { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
  902. { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
  903. { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
  904. { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
  905. { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
  906. { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
  907. { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
  908. { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
  909. { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */
  910. { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */
  911. { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */
  912. { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */
  913. { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */
  914. { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */
  915. { "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */
  916. { "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */
  917. { "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */
  918. { "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */
  919. { "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */
  920. { "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */
  921. { "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */
  922. { "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */
  923. { "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */
  924. { "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */
  925. { "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */
  926. { "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */
  927. { "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */
  928. { "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */
  929. { "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
  930. { "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
  931. { "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
  932. { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
  933. { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
  934. { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
  935. { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */
  936. { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */
  937. { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */
  938. { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */
  939. { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */
  940. { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */
  941. { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */
  942. { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */
  943. { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */
  944. { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */
  945. { "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */
  946. { "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */
  947. { "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */
  948. { "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */
  949. { "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */
  950. { "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */
  951. { "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */
  952. { "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
  953. { "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */
  954. { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
  955. { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */
  956. { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */
  957. { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
  958. { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */
  959. { "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, v9 }, /* rdhpr %hpriv,r */
  960. { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */
  961. { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, v9 }, /* wrhpr r1,%hpriv */
  962. { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */
  963. { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */
  964. { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, v9 }, /* wrhpr i,%hpriv */
  965. /* ??? This group seems wrong. A three operand move? */
  966. { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
  967. { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
  968. { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
  969. { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
  970. { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
  971. { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
  972. { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
  973. { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
  974. { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
  975. { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
  976. { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
  977. { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */
  978. { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
  979. { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
  980. { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
  981. { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
  982. { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
  983. { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */
  984. { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
  985. { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
  986. { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
  987. { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
  988. { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
  989. { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */
  990. { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
  991. { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
  992. { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */
  993. { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
  994. { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
  995. { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */
  996. { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */
  997. { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */
  998. { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */
  999. { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */
  1000. { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1001. { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 },
  1002. { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 },
  1003. { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */
  1004. { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */
  1005. /* This is not a commutative instruction. */
  1006. { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1007. { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 },
  1008. /* This is not a commutative instruction. */
  1009. { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1010. { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 },
  1011. { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */
  1012. { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */
  1013. { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */
  1014. { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */
  1015. { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1016. { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 },
  1017. { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1018. { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 },
  1019. { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
  1020. { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 },
  1021. { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 },
  1022. { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 },
  1023. { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
  1024. { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 },
  1025. { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 },
  1026. { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 },
  1027. { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1028. { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 },
  1029. { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 },
  1030. { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1031. { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 },
  1032. { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 },
  1033. { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */
  1034. { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */
  1035. { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */
  1036. { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */
  1037. { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */
  1038. { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */
  1039. { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */
  1040. { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */
  1041. { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */
  1042. { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */
  1043. { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
  1044. { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */
  1045. { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1046. { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 },
  1047. { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 },
  1048. { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1049. { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 },
  1050. { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 },
  1051. { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
  1052. { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 },
  1053. { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 },
  1054. { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 },
  1055. { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 },
  1056. { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 },
  1057. { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
  1058. { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 },
  1059. { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 },
  1060. { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 },
  1061. { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 },
  1062. { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 },
  1063. { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 },
  1064. { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 },
  1065. { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 },
  1066. { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 },
  1067. { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 },
  1068. { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 },
  1069. { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 },
  1070. { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 },
  1071. { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 },
  1072. { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 },
  1073. { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 },
  1074. { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 },
  1075. { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 },
  1076. { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 },
  1077. { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 },
  1078. { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 },
  1079. { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 },
  1080. { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 },
  1081. { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 },
  1082. { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 },
  1083. { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 },
  1084. { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 },
  1085. { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 },
  1086. { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 },
  1087. { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 },
  1088. { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 },
  1089. { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 },
  1090. { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 },
  1091. { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 },
  1092. { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 },
  1093. { "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
  1094. { "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
  1095. { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
  1096. { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 },
  1097. { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
  1098. { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 },
  1099. { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
  1100. { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 },
  1101. { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
  1102. { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 },
  1103. { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
  1104. { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 },
  1105. { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
  1106. { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 },
  1107. /* Conditional instructions.
  1108. Because this part of the table was such a mess earlier, I have
  1109. macrofied it so that all the branches and traps are generated from
  1110. a single-line description of each condition value. John Gilmore. */
  1111. /* Define branches -- one annulled, one without, etc. */
  1112. #define br(opcode, mask, lose, flags) \
  1113. { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \
  1114. { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 }
  1115. #define brx(opcode, mask, lose, flags) /* v9 */ \
  1116. { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \
  1117. { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \
  1118. { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \
  1119. { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
  1120. { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \
  1121. { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
  1122. { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \
  1123. { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \
  1124. { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \
  1125. { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
  1126. { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \
  1127. { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
  1128. /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
  1129. #define tr(opcode, mask, lose, flags) \
  1130. { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \
  1131. { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \
  1132. { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \
  1133. { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \
  1134. { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \
  1135. { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \
  1136. { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \
  1137. { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
  1138. { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \
  1139. { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \
  1140. { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \
  1141. { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */
  1142. /* v9: We must put `brx' before `br', to ensure that we never match something
  1143. v9: against an expression unless it is an expression. Otherwise, we end
  1144. v9: up with undefined symbol tables entries, because they get added, but
  1145. v9: are not deleted if the pattern fails to match. */
  1146. /* Define both branches and traps based on condition mask */
  1147. #define cond(bop, top, mask, flags) \
  1148. brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
  1149. br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
  1150. tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
  1151. /* Define all the conditions, all the branches, all the traps. */
  1152. /* Standard branch, trap mnemonics */
  1153. cond ("b", "ta", CONDA, F_UNBR),
  1154. /* Alternative form (just for assembly, not for disassembly) */
  1155. cond ("ba", "t", CONDA, F_UNBR|F_ALIAS),
  1156. cond ("bcc", "tcc", CONDCC, F_CONDBR),
  1157. cond ("bcs", "tcs", CONDCS, F_CONDBR),
  1158. cond ("be", "te", CONDE, F_CONDBR),
  1159. cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS),
  1160. cond ("bg", "tg", CONDG, F_CONDBR),
  1161. cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
  1162. cond ("bge", "tge", CONDGE, F_CONDBR),
  1163. cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
  1164. cond ("bgu", "tgu", CONDGU, F_CONDBR),
  1165. cond ("bl", "tl", CONDL, F_CONDBR),
  1166. cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
  1167. cond ("ble", "tle", CONDLE, F_CONDBR),
  1168. cond ("bleu", "tleu", CONDLEU, F_CONDBR),
  1169. cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */
  1170. cond ("bn", "tn", CONDN, F_CONDBR),
  1171. cond ("bne", "tne", CONDNE, F_CONDBR),
  1172. cond ("bneg", "tneg", CONDNEG, F_CONDBR),
  1173. cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
  1174. cond ("bpos", "tpos", CONDPOS, F_CONDBR),
  1175. cond ("bvc", "tvc", CONDVC, F_CONDBR),
  1176. cond ("bvs", "tvs", CONDVS, F_CONDBR),
  1177. cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
  1178. #undef cond
  1179. #undef br
  1180. #undef brr /* v9 */
  1181. #undef tr
  1182. #define brr(opcode, mask, lose, flags) /* v9 */ \
  1183. { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \
  1184. { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \
  1185. { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \
  1186. { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
  1187. { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \
  1188. { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
  1189. #define condr(bop, mask, flags) /* v9 */ \
  1190. brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
  1191. /* v9 */ condr("brnz", 0x5, F_CONDBR),
  1192. /* v9 */ condr("brz", 0x1, F_CONDBR),
  1193. /* v9 */ condr("brgez", 0x7, F_CONDBR),
  1194. /* v9 */ condr("brlz", 0x3, F_CONDBR),
  1195. /* v9 */ condr("brlez", 0x2, F_CONDBR),
  1196. /* v9 */ condr("brgz", 0x6, F_CONDBR),
  1197. #undef condr /* v9 */
  1198. #undef brr /* v9 */
  1199. #define movr(opcode, mask, flags) /* v9 */ \
  1200. { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \
  1201. { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 }
  1202. #define fmrrs(opcode, mask, lose, flags) /* v9 */ \
  1203. { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
  1204. #define fmrrd(opcode, mask, lose, flags) /* v9 */ \
  1205. { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
  1206. #define fmrrq(opcode, mask, lose, flags) /* v9 */ \
  1207. { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
  1208. #define fmovrs(mop, mask, flags) /* v9 */ \
  1209. fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
  1210. #define fmovrd(mop, mask, flags) /* v9 */ \
  1211. fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
  1212. #define fmovrq(mop, mask, flags) /* v9 */ \
  1213. fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
  1214. /* v9 */ movr("movrne", 0x5, 0),
  1215. /* v9 */ movr("movre", 0x1, 0),
  1216. /* v9 */ movr("movrgez", 0x7, 0),
  1217. /* v9 */ movr("movrlz", 0x3, 0),
  1218. /* v9 */ movr("movrlez", 0x2, 0),
  1219. /* v9 */ movr("movrgz", 0x6, 0),
  1220. /* v9 */ movr("movrnz", 0x5, F_ALIAS),
  1221. /* v9 */ movr("movrz", 0x1, F_ALIAS),
  1222. /* v9 */ fmovrs("fmovrsne", 0x5, 0),
  1223. /* v9 */ fmovrs("fmovrse", 0x1, 0),
  1224. /* v9 */ fmovrs("fmovrsgez", 0x7, 0),
  1225. /* v9 */ fmovrs("fmovrslz", 0x3, 0),
  1226. /* v9 */ fmovrs("fmovrslez", 0x2, 0),
  1227. /* v9 */ fmovrs("fmovrsgz", 0x6, 0),
  1228. /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
  1229. /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
  1230. /* v9 */ fmovrd("fmovrdne", 0x5, 0),
  1231. /* v9 */ fmovrd("fmovrde", 0x1, 0),
  1232. /* v9 */ fmovrd("fmovrdgez", 0x7, 0),
  1233. /* v9 */ fmovrd("fmovrdlz", 0x3, 0),
  1234. /* v9 */ fmovrd("fmovrdlez", 0x2, 0),
  1235. /* v9 */ fmovrd("fmovrdgz", 0x6, 0),
  1236. /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
  1237. /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
  1238. /* v9 */ fmovrq("fmovrqne", 0x5, 0),
  1239. /* v9 */ fmovrq("fmovrqe", 0x1, 0),
  1240. /* v9 */ fmovrq("fmovrqgez", 0x7, 0),
  1241. /* v9 */ fmovrq("fmovrqlz", 0x3, 0),
  1242. /* v9 */ fmovrq("fmovrqlez", 0x2, 0),
  1243. /* v9 */ fmovrq("fmovrqgz", 0x6, 0),
  1244. /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
  1245. /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
  1246. #undef movr /* v9 */
  1247. #undef fmovr /* v9 */
  1248. #undef fmrr /* v9 */
  1249. #define movicc(opcode, cond, flags) /* v9 */ \
  1250. { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
  1251. { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
  1252. { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \
  1253. { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 }
  1254. #define movfcc(opcode, fcond, flags) /* v9 */ \
  1255. { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
  1256. { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
  1257. { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
  1258. { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
  1259. { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
  1260. { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
  1261. { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
  1262. { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
  1263. #define movcc(opcode, cond, fcond, flags) /* v9 */ \
  1264. movfcc (opcode, fcond, flags), /* v9 */ \
  1265. movicc (opcode, cond, flags) /* v9 */
  1266. /* v9 */ movcc ("mova", CONDA, FCONDA, 0),
  1267. /* v9 */ movicc ("movcc", CONDCC, 0),
  1268. /* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS),
  1269. /* v9 */ movicc ("movcs", CONDCS, 0),
  1270. /* v9 */ movicc ("movlu", CONDLU, F_ALIAS),
  1271. /* v9 */ movcc ("move", CONDE, FCONDE, 0),
  1272. /* v9 */ movcc ("movg", CONDG, FCONDG, 0),
  1273. /* v9 */ movcc ("movge", CONDGE, FCONDGE, 0),
  1274. /* v9 */ movicc ("movgu", CONDGU, 0),
  1275. /* v9 */ movcc ("movl", CONDL, FCONDL, 0),
  1276. /* v9 */ movcc ("movle", CONDLE, FCONDLE, 0),
  1277. /* v9 */ movicc ("movleu", CONDLEU, 0),
  1278. /* v9 */ movfcc ("movlg", FCONDLG, 0),
  1279. /* v9 */ movcc ("movn", CONDN, FCONDN, 0),
  1280. /* v9 */ movcc ("movne", CONDNE, FCONDNE, 0),
  1281. /* v9 */ movicc ("movneg", CONDNEG, 0),
  1282. /* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS),
  1283. /* v9 */ movfcc ("movo", FCONDO, 0),
  1284. /* v9 */ movicc ("movpos", CONDPOS, 0),
  1285. /* v9 */ movfcc ("movu", FCONDU, 0),
  1286. /* v9 */ movfcc ("movue", FCONDUE, 0),
  1287. /* v9 */ movfcc ("movug", FCONDUG, 0),
  1288. /* v9 */ movfcc ("movuge", FCONDUGE, 0),
  1289. /* v9 */ movfcc ("movul", FCONDUL, 0),
  1290. /* v9 */ movfcc ("movule", FCONDULE, 0),
  1291. /* v9 */ movicc ("movvc", CONDVC, 0),
  1292. /* v9 */ movicc ("movvs", CONDVS, 0),
  1293. /* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS),
  1294. #undef movicc /* v9 */
  1295. #undef movfcc /* v9 */
  1296. #undef movcc /* v9 */
  1297. #define FM_SF 1 /* v9 - values for fpsize */
  1298. #define FM_DF 2 /* v9 */
  1299. #define FM_QF 3 /* v9 */
  1300. #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
  1301. { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \
  1302. { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 }
  1303. #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
  1304. { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \
  1305. { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \
  1306. { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \
  1307. { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 }
  1308. /* FIXME: use fmovicc/fmovfcc? */ /* v9 */
  1309. #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
  1310. { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \
  1311. { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \
  1312. { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \
  1313. { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \
  1314. { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \
  1315. { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 }
  1316. #define fmovicc(suffix, cond, flags) /* v9 */ \
  1317. fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \
  1318. fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
  1319. fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
  1320. #define fmovfcc(suffix, fcond, flags) /* v9 */ \
  1321. fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \
  1322. fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
  1323. fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
  1324. #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
  1325. fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \
  1326. fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
  1327. fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
  1328. /* v9 */ fmovcc ("a", CONDA, FCONDA, 0),
  1329. /* v9 */ fmovicc ("cc", CONDCC, 0),
  1330. /* v9 */ fmovicc ("cs", CONDCS, 0),
  1331. /* v9 */ fmovcc ("e", CONDE, FCONDE, 0),
  1332. /* v9 */ fmovcc ("g", CONDG, FCONDG, 0),
  1333. /* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0),
  1334. /* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
  1335. /* v9 */ fmovicc ("gu", CONDGU, 0),
  1336. /* v9 */ fmovcc ("l", CONDL, FCONDL, 0),
  1337. /* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0),
  1338. /* v9 */ fmovicc ("leu", CONDLEU, 0),
  1339. /* v9 */ fmovfcc ("lg", FCONDLG, 0),
  1340. /* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
  1341. /* v9 */ fmovcc ("n", CONDN, FCONDN, 0),
  1342. /* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0),
  1343. /* v9 */ fmovicc ("neg", CONDNEG, 0),
  1344. /* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS),
  1345. /* v9 */ fmovfcc ("o", FCONDO, 0),
  1346. /* v9 */ fmovicc ("pos", CONDPOS, 0),
  1347. /* v9 */ fmovfcc ("u", FCONDU, 0),
  1348. /* v9 */ fmovfcc ("ue", FCONDUE, 0),
  1349. /* v9 */ fmovfcc ("ug", FCONDUG, 0),
  1350. /* v9 */ fmovfcc ("uge", FCONDUGE, 0),
  1351. /* v9 */ fmovfcc ("ul", FCONDUL, 0),
  1352. /* v9 */ fmovfcc ("ule", FCONDULE, 0),
  1353. /* v9 */ fmovicc ("vc", CONDVC, 0),
  1354. /* v9 */ fmovicc ("vs", CONDVS, 0),
  1355. /* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS),
  1356. #undef fmoviccx /* v9 */
  1357. #undef fmovfccx /* v9 */
  1358. #undef fmovccx /* v9 */
  1359. #undef fmovicc /* v9 */
  1360. #undef fmovfcc /* v9 */
  1361. #undef fmovcc /* v9 */
  1362. #undef FM_DF /* v9 */
  1363. #undef FM_QF /* v9 */
  1364. #undef FM_SF /* v9 */
  1365. /* Coprocessor branches. */
  1366. #define CBR(opcode, mask, lose, flags, arch) \
  1367. { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \
  1368. { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch }
  1369. /* Floating point branches. */
  1370. #define FBR(opcode, mask, lose, flags) \
  1371. { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \
  1372. { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 }
  1373. /* V9 extended floating point branches. */
  1374. #define FBRX(opcode, mask, lose, flags) /* v9 */ \
  1375. { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \
  1376. { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
  1377. { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \
  1378. { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
  1379. { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
  1380. { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
  1381. { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \
  1382. { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
  1383. { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \
  1384. { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
  1385. { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
  1386. { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
  1387. { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \
  1388. { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
  1389. { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \
  1390. { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
  1391. { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
  1392. { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
  1393. { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \
  1394. { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
  1395. { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \
  1396. { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
  1397. { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \
  1398. { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 }
  1399. /* v9: We must put `FBRX' before `FBR', to ensure that we never match
  1400. v9: something against an expression unless it is an expression. Otherwise,
  1401. v9: we end up with undefined symbol tables entries, because they get added,
  1402. v9: but are not deleted if the pattern fails to match. */
  1403. #define CONDFC(fop, cop, mask, flags) \
  1404. FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
  1405. FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
  1406. CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
  1407. #define CONDFCL(fop, cop, mask, flags) \
  1408. FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
  1409. FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
  1410. CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
  1411. #define CONDF(fop, mask, flags) \
  1412. FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
  1413. FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
  1414. CONDFC ("fb", "cb", 0x8, F_UNBR),
  1415. CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS),
  1416. CONDFC ("fbe", "cb0", 0x9, F_CONDBR),
  1417. CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS),
  1418. CONDFC ("fbg", "cb2", 0x6, F_CONDBR),
  1419. CONDFC ("fbge", "cb02", 0xb, F_CONDBR),
  1420. CONDFC ("fbl", "cb1", 0x4, F_CONDBR),
  1421. CONDFC ("fble", "cb01", 0xd, F_CONDBR),
  1422. CONDFC ("fblg", "cb12", 0x2, F_CONDBR),
  1423. CONDFCL ("fbn", "cbn", 0x0, F_UNBR),
  1424. CONDFC ("fbne", "cb123", 0x1, F_CONDBR),
  1425. CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS),
  1426. CONDFC ("fbo", "cb012", 0xf, F_CONDBR),
  1427. CONDFC ("fbu", "cb3", 0x7, F_CONDBR),
  1428. CONDFC ("fbue", "cb03", 0xa, F_CONDBR),
  1429. CONDFC ("fbug", "cb23", 0x5, F_CONDBR),
  1430. CONDFC ("fbuge", "cb023", 0xc, F_CONDBR),
  1431. CONDFC ("fbul", "cb13", 0x3, F_CONDBR),
  1432. CONDFC ("fbule", "cb013", 0xe, F_CONDBR),
  1433. #undef CONDFC
  1434. #undef CONDFCL
  1435. #undef CONDF
  1436. #undef CBR
  1437. #undef FBR
  1438. #undef FBRX /* v9 */
  1439. { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
  1440. { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
  1441. { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
  1442. { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
  1443. { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
  1444. { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
  1445. { "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
  1446. { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 },
  1447. { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
  1448. { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
  1449. { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 },
  1450. { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
  1451. { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1452. { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 },
  1453. { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 },
  1454. { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1455. { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 },
  1456. { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 },
  1457. { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1458. { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 },
  1459. { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1460. { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 },
  1461. { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 },
  1462. { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 },
  1463. /* This *is* a commutative instruction. */
  1464. { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1465. { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 },
  1466. { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 },
  1467. /* This *is* a commutative instruction. */
  1468. { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1469. { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 },
  1470. { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 },
  1471. { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1472. { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 },
  1473. { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 },
  1474. { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 },
  1475. { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 },
  1476. { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 },
  1477. { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
  1478. { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
  1479. { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
  1480. { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
  1481. /* FPop1 and FPop2 are not instructions. Don't accept them. */
  1482. { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 },
  1483. { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
  1484. { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
  1485. { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 },
  1486. { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 },
  1487. { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 },
  1488. { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
  1489. { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
  1490. { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
  1491. { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 },
  1492. { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 },
  1493. { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 },
  1494. { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
  1495. { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
  1496. { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 },
  1497. { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 },
  1498. { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 },
  1499. { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 },
  1500. { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 },
  1501. { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 },
  1502. { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 },
  1503. { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 },
  1504. { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 },
  1505. { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 },
  1506. { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 },
  1507. { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 },
  1508. { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 },
  1509. { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 },
  1510. { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 },
  1511. { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 },
  1512. { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 },
  1513. { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 },
  1514. { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 },
  1515. { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 },
  1516. { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 },
  1517. { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
  1518. { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 },
  1519. { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 },
  1520. { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 },
  1521. { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
  1522. { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 },
  1523. { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 },
  1524. { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 },
  1525. { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
  1526. { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 },
  1527. { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 },
  1528. { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 },
  1529. { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 },
  1530. { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 },
  1531. { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 },
  1532. { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 },
  1533. { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 },
  1534. { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 },
  1535. #define CMPFCC(x) (((x)&0x3)<<25)
  1536. { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 },
  1537. { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 },
  1538. { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 },
  1539. { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 },
  1540. { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 },
  1541. { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 },
  1542. { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 },
  1543. { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 },
  1544. { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 },
  1545. { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 },
  1546. { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 },
  1547. { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 },
  1548. { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 },
  1549. { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 },
  1550. { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 },
  1551. { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 },
  1552. { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 },
  1553. { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 },
  1554. { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 },
  1555. { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 },
  1556. { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
  1557. { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 },
  1558. { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 },
  1559. { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 },
  1560. { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 },
  1561. { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
  1562. { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 },
  1563. { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 },
  1564. { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 },
  1565. { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 },
  1566. { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 },
  1567. { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 },
  1568. { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 },
  1569. { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 },
  1570. { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 },
  1571. { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 },
  1572. { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 },
  1573. { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 },
  1574. { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 },
  1575. { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 },
  1576. /* These Extended FPop (FIFO) instructions are new in the Fujitsu
  1577. MB86934, replacing the CPop instructions from v6 and later
  1578. processors. */
  1579. #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite }
  1580. #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite }
  1581. #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite }
  1582. EFPOP1_2 ("efitod", 0x0c8, "f,H"),
  1583. EFPOP1_2 ("efitos", 0x0c4, "f,g"),
  1584. EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
  1585. EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
  1586. EFPOP1_2 ("efstod", 0x0c9, "f,H"),
  1587. EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
  1588. EFPOP1_2 ("efmovs", 0x001, "f,g"),
  1589. EFPOP1_2 ("efnegs", 0x005, "f,g"),
  1590. EFPOP1_2 ("efabss", 0x009, "f,g"),
  1591. EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
  1592. EFPOP1_2 ("efsqrts", 0x029, "f,g"),
  1593. EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
  1594. EFPOP1_3 ("efadds", 0x041, "e,f,g"),
  1595. EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
  1596. EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
  1597. EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
  1598. EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
  1599. EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
  1600. EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
  1601. EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
  1602. EFPOP2_2 ("efcmpd", 0x052, "v,B"),
  1603. EFPOP2_2 ("efcmped", 0x056, "v,B"),
  1604. EFPOP2_2 ("efcmps", 0x051, "e,f"),
  1605. EFPOP2_2 ("efcmpes", 0x055, "e,f"),
  1606. #undef EFPOP1_2
  1607. #undef EFPOP1_3
  1608. #undef EFPOP2_2
  1609. /* These are marked F_ALIAS, so that they won't conflict with sparclite insns
  1610. present. Otherwise, the F_ALIAS flag is ignored. */
  1611. { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 },
  1612. { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
  1613. /* sparclet specific insns */
  1614. COMMUTEOP ("umac", 0x3e, sparclet),
  1615. COMMUTEOP ("smac", 0x3f, sparclet),
  1616. COMMUTEOP ("umacd", 0x2e, sparclet),
  1617. COMMUTEOP ("smacd", 0x2f, sparclet),
  1618. COMMUTEOP ("umuld", 0x09, sparclet),
  1619. COMMUTEOP ("smuld", 0x0d, sparclet),
  1620. { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet },
  1621. { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet },
  1622. /* The manual isn't completely accurate on these insns. The `rs2' field is
  1623. treated as being 6 bits to account for 6 bit immediates to cpush. It is
  1624. assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
  1625. #define BIT5 (1<<5)
  1626. { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet },
  1627. { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet },
  1628. { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet },
  1629. { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet },
  1630. { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet },
  1631. { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet },
  1632. { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
  1633. #undef BIT5
  1634. /* sparclet coprocessor branch insns */
  1635. #define SLCBCC2(opcode, mask, lose) \
  1636. { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \
  1637. { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
  1638. #define SLCBCC(opcode, mask) \
  1639. SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
  1640. /* cbn,cba can't be defined here because they're defined elsewhere and GAS
  1641. requires all mnemonics of the same name to be consecutive. */
  1642. /*SLCBCC("cbn", 0), - already defined */
  1643. SLCBCC("cbe", 1),
  1644. SLCBCC("cbf", 2),
  1645. SLCBCC("cbef", 3),
  1646. SLCBCC("cbr", 4),
  1647. SLCBCC("cber", 5),
  1648. SLCBCC("cbfr", 6),
  1649. SLCBCC("cbefr", 7),
  1650. /*SLCBCC("cba", 8), - already defined */
  1651. SLCBCC("cbne", 9),
  1652. SLCBCC("cbnf", 10),
  1653. SLCBCC("cbnef", 11),
  1654. SLCBCC("cbnr", 12),
  1655. SLCBCC("cbner", 13),
  1656. SLCBCC("cbnfr", 14),
  1657. SLCBCC("cbnefr", 15),
  1658. #undef SLCBCC2
  1659. #undef SLCBCC
  1660. { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
  1661. { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
  1662. { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
  1663. { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
  1664. /* v9 synthetic insns */
  1665. { "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
  1666. { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
  1667. { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
  1668. { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
  1669. { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
  1670. { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
  1671. { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
  1672. { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
  1673. { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
  1674. /* Ultrasparc extensions */
  1675. { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
  1676. /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
  1677. { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a },
  1678. { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a },
  1679. { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a },
  1680. { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a },
  1681. { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a },
  1682. { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a },
  1683. { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a },
  1684. { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a },
  1685. { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a },
  1686. { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a },
  1687. { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a },
  1688. { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a },
  1689. { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a },
  1690. /* Note that the mixing of 32/64 bit regs is intentional. */
  1691. { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a },
  1692. { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a },
  1693. { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a },
  1694. { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a },
  1695. { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a },
  1696. { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a },
  1697. { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a },
  1698. { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a },
  1699. { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a },
  1700. { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a },
  1701. { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a },
  1702. { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a },
  1703. { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a },
  1704. { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a },
  1705. { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a },
  1706. { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a },
  1707. { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a },
  1708. { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a },
  1709. { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a },
  1710. { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a },
  1711. { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a },
  1712. { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a },
  1713. { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a },
  1714. { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a },
  1715. { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a },
  1716. { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a },
  1717. { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a },
  1718. { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a },
  1719. { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a },
  1720. { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a },
  1721. { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a },
  1722. { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a },
  1723. { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a },
  1724. { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a },
  1725. { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a },
  1726. { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a },
  1727. { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a },
  1728. { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a },
  1729. { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a },
  1730. { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a },
  1731. { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a },
  1732. { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a },
  1733. { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a },
  1734. { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a },
  1735. { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a },
  1736. { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a },
  1737. { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a },
  1738. { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a },
  1739. { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a },
  1740. { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a },
  1741. { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a },
  1742. { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a },
  1743. { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a },
  1744. { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a },
  1745. { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a },
  1746. { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a },
  1747. { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a },
  1748. { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a },
  1749. { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
  1750. { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
  1751. /* Cheetah instructions */
  1752. { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
  1753. { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
  1754. { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
  1755. { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
  1756. { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
  1757. { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
  1758. { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
  1759. { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
  1760. { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
  1761. /* More v9 specific insns, these need to come last so they do not clash
  1762. with v9a instructions such as "edge8" which looks like impdep1. */
  1763. #define IMPDEP(name, code) \
  1764. { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
  1765. { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \
  1766. { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \
  1767. { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a }
  1768. IMPDEP ("impdep1", 0x36),
  1769. IMPDEP ("impdep2", 0x37),
  1770. #undef IMPDEP
  1771. };
  1772. static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
  1773. /* Utilities for argument parsing. */
  1774. typedef struct
  1775. {
  1776. int value;
  1777. const char *name;
  1778. } arg;
  1779. /* Look up VALUE in TABLE. */
  1780. static const char *
  1781. lookup_value (const arg *table, int value)
  1782. {
  1783. const arg *p;
  1784. for (p = table; p->name; ++p)
  1785. if (value == p->value)
  1786. return p->name;
  1787. return NULL;
  1788. }
  1789. /* Handle ASI's. */
  1790. static const arg asi_table_v8[] =
  1791. {
  1792. { 0x00, "#ASI_M_RES00" },
  1793. { 0x01, "#ASI_M_UNA01" },
  1794. { 0x02, "#ASI_M_MXCC" },
  1795. { 0x03, "#ASI_M_FLUSH_PROBE" },
  1796. { 0x04, "#ASI_M_MMUREGS" },
  1797. { 0x05, "#ASI_M_TLBDIAG" },
  1798. { 0x06, "#ASI_M_DIAGS" },
  1799. { 0x07, "#ASI_M_IODIAG" },
  1800. { 0x08, "#ASI_M_USERTXT" },
  1801. { 0x09, "#ASI_M_KERNELTXT" },
  1802. { 0x0A, "#ASI_M_USERDATA" },
  1803. { 0x0B, "#ASI_M_KERNELDATA" },
  1804. { 0x0C, "#ASI_M_TXTC_TAG" },
  1805. { 0x0D, "#ASI_M_TXTC_DATA" },
  1806. { 0x0E, "#ASI_M_DATAC_TAG" },
  1807. { 0x0F, "#ASI_M_DATAC_DATA" },
  1808. { 0x10, "#ASI_M_FLUSH_PAGE" },
  1809. { 0x11, "#ASI_M_FLUSH_SEG" },
  1810. { 0x12, "#ASI_M_FLUSH_REGION" },
  1811. { 0x13, "#ASI_M_FLUSH_CTX" },
  1812. { 0x14, "#ASI_M_FLUSH_USER" },
  1813. { 0x17, "#ASI_M_BCOPY" },
  1814. { 0x18, "#ASI_M_IFLUSH_PAGE" },
  1815. { 0x19, "#ASI_M_IFLUSH_SEG" },
  1816. { 0x1A, "#ASI_M_IFLUSH_REGION" },
  1817. { 0x1B, "#ASI_M_IFLUSH_CTX" },
  1818. { 0x1C, "#ASI_M_IFLUSH_USER" },
  1819. { 0x1F, "#ASI_M_BFILL" },
  1820. { 0x20, "#ASI_M_BYPASS" },
  1821. { 0x29, "#ASI_M_FBMEM" },
  1822. { 0x2A, "#ASI_M_VMEUS" },
  1823. { 0x2B, "#ASI_M_VMEPS" },
  1824. { 0x2C, "#ASI_M_VMEUT" },
  1825. { 0x2D, "#ASI_M_VMEPT" },
  1826. { 0x2E, "#ASI_M_SBUS" },
  1827. { 0x2F, "#ASI_M_CTL" },
  1828. { 0x31, "#ASI_M_FLUSH_IWHOLE" },
  1829. { 0x36, "#ASI_M_IC_FLCLEAR" },
  1830. { 0x37, "#ASI_M_DC_FLCLEAR" },
  1831. { 0x39, "#ASI_M_DCDR" },
  1832. { 0x40, "#ASI_M_VIKING_TMP1" },
  1833. { 0x41, "#ASI_M_VIKING_TMP2" },
  1834. { 0x4c, "#ASI_M_ACTION" },
  1835. { 0, NULL }
  1836. };
  1837. static const arg asi_table_v9[] =
  1838. {
  1839. /* These are in the v9 architecture manual. */
  1840. /* The shorter versions appear first, they're here because Sun's as has them.
  1841. Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
  1842. UltraSPARC architecture manual). */
  1843. { 0x04, "#ASI_N" },
  1844. { 0x0c, "#ASI_N_L" },
  1845. { 0x10, "#ASI_AIUP" },
  1846. { 0x11, "#ASI_AIUS" },
  1847. { 0x18, "#ASI_AIUP_L" },
  1848. { 0x19, "#ASI_AIUS_L" },
  1849. { 0x80, "#ASI_P" },
  1850. { 0x81, "#ASI_S" },
  1851. { 0x82, "#ASI_PNF" },
  1852. { 0x83, "#ASI_SNF" },
  1853. { 0x88, "#ASI_P_L" },
  1854. { 0x89, "#ASI_S_L" },
  1855. { 0x8a, "#ASI_PNF_L" },
  1856. { 0x8b, "#ASI_SNF_L" },
  1857. { 0x04, "#ASI_NUCLEUS" },
  1858. { 0x0c, "#ASI_NUCLEUS_LITTLE" },
  1859. { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
  1860. { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
  1861. { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
  1862. { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
  1863. { 0x80, "#ASI_PRIMARY" },
  1864. { 0x81, "#ASI_SECONDARY" },
  1865. { 0x82, "#ASI_PRIMARY_NOFAULT" },
  1866. { 0x83, "#ASI_SECONDARY_NOFAULT" },
  1867. { 0x88, "#ASI_PRIMARY_LITTLE" },
  1868. { 0x89, "#ASI_SECONDARY_LITTLE" },
  1869. { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
  1870. { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
  1871. /* These are UltraSPARC extensions. */
  1872. { 0x14, "#ASI_PHYS_USE_EC"},
  1873. { 0x15, "#ASI_PHYS_BYPASS_EC_WITH_EBIT"},
  1874. { 0x45, "#ASI_LSU_CONTROL_REG"},
  1875. { 0x47, "#ASI_DCACHE_TAG"},
  1876. { 0x4a, "#ASI_UPA_CONFIG_REG"},
  1877. { 0x50, "#ASI_IMMU" },
  1878. { 0x51, "#ASI_IMMU_TSB_8KB_PTR_REG" },
  1879. { 0x52, "#ASI_IMMU_TSB_64KB_PTR_REG" },
  1880. /*{ 0x53, "#reserved?" },*/
  1881. { 0x54, "#ASI_ITLB_DATA_IN_REG" },
  1882. { 0x55, "#ASI_ITLB_DATA_ACCESS_REG" },
  1883. { 0x56, "#ASI_ITLB_TAG_READ_REG" },
  1884. { 0x57, "#ASI_IMMU_DEMAP" },
  1885. { 0x58, "#ASI_DMMU" },
  1886. { 0x59, "#ASI_DMMU_TSB_8KB_PTR_REG" },
  1887. { 0x5a, "#ASI_DMMU_TSB_64KB_PTR_REG" },
  1888. { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR_REG" },
  1889. { 0x5c, "#ASI_DTLB_DATA_IN_REG" },
  1890. { 0x5d, "#ASI_DTLB_DATA_ACCESS_REG" },
  1891. { 0x5e, "#ASI_DTLB_TAG_READ_REG" },
  1892. { 0x5f, "#ASI_DMMU_DEMAP" },
  1893. { 0x67, "#ASI_IC_TAG"},
  1894. /* FIXME: There are dozens of them. Not sure we want them all.
  1895. Most are for kernel building but some are for vis type stuff. */
  1896. { 0, NULL }
  1897. };
  1898. /* Return the name for ASI value VALUE or NULL if not found. */
  1899. static const char *
  1900. sparc_decode_asi_v9 (int value)
  1901. {
  1902. return lookup_value (asi_table_v9, value);
  1903. }
  1904. static const char *
  1905. sparc_decode_asi_v8 (int value)
  1906. {
  1907. return lookup_value (asi_table_v8, value);
  1908. }
  1909. /* Handle membar masks. */
  1910. static const arg membar_table[] =
  1911. {
  1912. { 0x40, "#Sync" },
  1913. { 0x20, "#MemIssue" },
  1914. { 0x10, "#Lookaside" },
  1915. { 0x08, "#StoreStore" },
  1916. { 0x04, "#LoadStore" },
  1917. { 0x02, "#StoreLoad" },
  1918. { 0x01, "#LoadLoad" },
  1919. { 0, NULL }
  1920. };
  1921. /* Return the name for membar value VALUE or NULL if not found. */
  1922. static const char *
  1923. sparc_decode_membar (int value)
  1924. {
  1925. return lookup_value (membar_table, value);
  1926. }
  1927. /* Handle prefetch args. */
  1928. static const arg prefetch_table[] =
  1929. {
  1930. { 0, "#n_reads" },
  1931. { 1, "#one_read" },
  1932. { 2, "#n_writes" },
  1933. { 3, "#one_write" },
  1934. { 4, "#page" },
  1935. { 16, "#invalidate" },
  1936. { 0, NULL }
  1937. };
  1938. /* Return the name for prefetch value VALUE or NULL if not found. */
  1939. static const char *
  1940. sparc_decode_prefetch (int value)
  1941. {
  1942. return lookup_value (prefetch_table, value);
  1943. }
  1944. /* Handle sparclet coprocessor registers. */
  1945. static const arg sparclet_cpreg_table[] =
  1946. {
  1947. { 0, "%ccsr" },
  1948. { 1, "%ccfr" },
  1949. { 2, "%cccrcr" },
  1950. { 3, "%ccpr" },
  1951. { 4, "%ccsr2" },
  1952. { 5, "%cccrr" },
  1953. { 6, "%ccrstr" },
  1954. { 0, NULL }
  1955. };
  1956. /* Return the name for sparclet cpreg value VALUE or NULL if not found. */
  1957. static const char *
  1958. sparc_decode_sparclet_cpreg (int value)
  1959. {
  1960. return lookup_value (sparclet_cpreg_table, value);
  1961. }
  1962. #undef MASK_V9
  1963. /* opcodes/sparc-dis.c */
  1964. /* Print SPARC instructions.
  1965. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
  1966. 2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
  1967. This program is free software; you can redistribute it and/or modify
  1968. it under the terms of the GNU General Public License as published by
  1969. the Free Software Foundation; either version 2 of the License, or
  1970. (at your option) any later version.
  1971. This program is distributed in the hope that it will be useful,
  1972. but WITHOUT ANY WARRANTY; without even the implied warranty of
  1973. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1974. GNU General Public License for more details.
  1975. You should have received a copy of the GNU General Public License
  1976. along with this program; if not, see <http://www.gnu.org/licenses/>. */
  1977. /* Bitmask of v9 architectures. */
  1978. #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
  1979. | (1 << SPARC_OPCODE_ARCH_V9A) \
  1980. | (1 << SPARC_OPCODE_ARCH_V9B))
  1981. /* 1 if INSN is for v9 only. */
  1982. #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
  1983. /* 1 if INSN is for v9. */
  1984. #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
  1985. /* The sorted opcode table. */
  1986. static const sparc_opcode **sorted_opcodes;
  1987. /* For faster lookup, after insns are sorted they are hashed. */
  1988. /* ??? I think there is room for even more improvement. */
  1989. #define HASH_SIZE 256
  1990. /* It is important that we only look at insn code bits as that is how the
  1991. opcode table is hashed. OPCODE_BITS is a table of valid bits for each
  1992. of the main types (0,1,2,3). */
  1993. static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
  1994. #define HASH_INSN(INSN) \
  1995. ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
  1996. typedef struct sparc_opcode_hash
  1997. {
  1998. struct sparc_opcode_hash *next;
  1999. const sparc_opcode *opcode;
  2000. } sparc_opcode_hash;
  2001. static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
  2002. /* Sign-extend a value which is N bits long. */
  2003. #define SEX(value, bits) \
  2004. ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
  2005. >> ((8 * sizeof (int)) - bits) )
  2006. static const char * const reg_names[] =
  2007. { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
  2008. "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
  2009. "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
  2010. "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
  2011. "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
  2012. "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
  2013. "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
  2014. "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
  2015. "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  2016. "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
  2017. "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
  2018. "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
  2019. /* psr, wim, tbr, fpsr, cpsr are v8 only. */
  2020. "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
  2021. };
  2022. #define freg_names (&reg_names[4 * 8])
  2023. /* These are ordered according to there register number in
  2024. rdpr and wrpr insns. */
  2025. static const char * const v9_priv_reg_names[] =
  2026. {
  2027. "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
  2028. "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
  2029. "wstate", "fq", "gl"
  2030. /* "ver" - special cased */
  2031. };
  2032. /* These are ordered according to there register number in
  2033. rdhpr and wrhpr insns. */
  2034. static const char * const v9_hpriv_reg_names[] =
  2035. {
  2036. "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
  2037. "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
  2038. "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
  2039. "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
  2040. "resv28", "resv29", "resv30", "hstick_cmpr"
  2041. };
  2042. /* These are ordered according to there register number in
  2043. rd and wr insns (-16). */
  2044. static const char * const v9a_asr_reg_names[] =
  2045. {
  2046. "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
  2047. "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
  2048. };
  2049. /* Macros used to extract instruction fields. Not all fields have
  2050. macros defined here, only those which are actually used. */
  2051. #define X_RD(i) (((i) >> 25) & 0x1f)
  2052. #define X_RS1(i) (((i) >> 14) & 0x1f)
  2053. #define X_LDST_I(i) (((i) >> 13) & 1)
  2054. #define X_ASI(i) (((i) >> 5) & 0xff)
  2055. #define X_RS2(i) (((i) >> 0) & 0x1f)
  2056. #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
  2057. #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
  2058. #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
  2059. #define X_IMM22(i) X_DISP22 (i)
  2060. #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
  2061. /* These are for v9. */
  2062. #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
  2063. #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
  2064. #define X_MEMBAR(i) ((i) & 0x7f)
  2065. /* Here is the union which was used to extract instruction fields
  2066. before the shift and mask macros were written.
  2067. union sparc_insn
  2068. {
  2069. unsigned long int code;
  2070. struct
  2071. {
  2072. unsigned int anop:2;
  2073. #define op ldst.anop
  2074. unsigned int anrd:5;
  2075. #define rd ldst.anrd
  2076. unsigned int op3:6;
  2077. unsigned int anrs1:5;
  2078. #define rs1 ldst.anrs1
  2079. unsigned int i:1;
  2080. unsigned int anasi:8;
  2081. #define asi ldst.anasi
  2082. unsigned int anrs2:5;
  2083. #define rs2 ldst.anrs2
  2084. #define shcnt rs2
  2085. } ldst;
  2086. struct
  2087. {
  2088. unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
  2089. unsigned int IMM13:13;
  2090. #define imm13 IMM13.IMM13
  2091. } IMM13;
  2092. struct
  2093. {
  2094. unsigned int anop:2;
  2095. unsigned int a:1;
  2096. unsigned int cond:4;
  2097. unsigned int op2:3;
  2098. unsigned int DISP22:22;
  2099. #define disp22 branch.DISP22
  2100. #define imm22 disp22
  2101. } branch;
  2102. struct
  2103. {
  2104. unsigned int anop:2;
  2105. unsigned int a:1;
  2106. unsigned int z:1;
  2107. unsigned int rcond:3;
  2108. unsigned int op2:3;
  2109. unsigned int DISP16HI:2;
  2110. unsigned int p:1;
  2111. unsigned int _rs1:5;
  2112. unsigned int DISP16LO:14;
  2113. } branch16;
  2114. struct
  2115. {
  2116. unsigned int anop:2;
  2117. unsigned int adisp30:30;
  2118. #define disp30 call.adisp30
  2119. } call;
  2120. }; */
  2121. /* Nonzero if INSN is the opcode for a delayed branch. */
  2122. static int
  2123. is_delayed_branch (unsigned long insn)
  2124. {
  2125. sparc_opcode_hash *op;
  2126. for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
  2127. {
  2128. const sparc_opcode *opcode = op->opcode;
  2129. if ((opcode->match & insn) == opcode->match
  2130. && (opcode->lose & insn) == 0)
  2131. return opcode->flags & F_DELAYED;
  2132. }
  2133. return 0;
  2134. }
  2135. /* extern void qsort (); */
  2136. /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
  2137. to compare_opcodes. */
  2138. static unsigned int current_arch_mask;
  2139. /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
  2140. static int
  2141. compute_arch_mask (unsigned long mach)
  2142. {
  2143. switch (mach)
  2144. {
  2145. case 0 :
  2146. case bfd_mach_sparc :
  2147. return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
  2148. case bfd_mach_sparc_sparclet :
  2149. return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
  2150. case bfd_mach_sparc_sparclite :
  2151. case bfd_mach_sparc_sparclite_le :
  2152. /* sparclites insns are recognized by default (because that's how
  2153. they've always been treated, for better or worse). Kludge this by
  2154. indicating generic v8 is also selected. */
  2155. return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
  2156. | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
  2157. case bfd_mach_sparc_v8plus :
  2158. case bfd_mach_sparc_v9 :
  2159. return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
  2160. case bfd_mach_sparc_v8plusa :
  2161. case bfd_mach_sparc_v9a :
  2162. return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
  2163. case bfd_mach_sparc_v8plusb :
  2164. case bfd_mach_sparc_v9b :
  2165. return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
  2166. }
  2167. abort ();
  2168. }
  2169. /* Compare opcodes A and B. */
  2170. static int
  2171. compare_opcodes (const void * a, const void * b)
  2172. {
  2173. sparc_opcode *op0 = * (sparc_opcode **) a;
  2174. sparc_opcode *op1 = * (sparc_opcode **) b;
  2175. unsigned long int match0 = op0->match, match1 = op1->match;
  2176. unsigned long int lose0 = op0->lose, lose1 = op1->lose;
  2177. register unsigned int i;
  2178. /* If one (and only one) insn isn't supported by the current architecture,
  2179. prefer the one that is. If neither are supported, but they're both for
  2180. the same architecture, continue processing. Otherwise (both unsupported
  2181. and for different architectures), prefer lower numbered arch's (fudged
  2182. by comparing the bitmasks). */
  2183. if (op0->architecture & current_arch_mask)
  2184. {
  2185. if (! (op1->architecture & current_arch_mask))
  2186. return -1;
  2187. }
  2188. else
  2189. {
  2190. if (op1->architecture & current_arch_mask)
  2191. return 1;
  2192. else if (op0->architecture != op1->architecture)
  2193. return op0->architecture - op1->architecture;
  2194. }
  2195. /* If a bit is set in both match and lose, there is something
  2196. wrong with the opcode table. */
  2197. if (match0 & lose0)
  2198. {
  2199. fprintf
  2200. (stderr,
  2201. /* xgettext:c-format */
  2202. _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
  2203. op0->name, match0, lose0);
  2204. op0->lose &= ~op0->match;
  2205. lose0 = op0->lose;
  2206. }
  2207. if (match1 & lose1)
  2208. {
  2209. fprintf
  2210. (stderr,
  2211. /* xgettext:c-format */
  2212. _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
  2213. op1->name, match1, lose1);
  2214. op1->lose &= ~op1->match;
  2215. lose1 = op1->lose;
  2216. }
  2217. /* Because the bits that are variable in one opcode are constant in
  2218. another, it is important to order the opcodes in the right order. */
  2219. for (i = 0; i < 32; ++i)
  2220. {
  2221. unsigned long int x = 1 << i;
  2222. int x0 = (match0 & x) != 0;
  2223. int x1 = (match1 & x) != 0;
  2224. if (x0 != x1)
  2225. return x1 - x0;
  2226. }
  2227. for (i = 0; i < 32; ++i)
  2228. {
  2229. unsigned long int x = 1 << i;
  2230. int x0 = (lose0 & x) != 0;
  2231. int x1 = (lose1 & x) != 0;
  2232. if (x0 != x1)
  2233. return x1 - x0;
  2234. }
  2235. /* They are functionally equal. So as long as the opcode table is
  2236. valid, we can put whichever one first we want, on aesthetic grounds. */
  2237. /* Our first aesthetic ground is that aliases defer to real insns. */
  2238. {
  2239. int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
  2240. if (alias_diff != 0)
  2241. /* Put the one that isn't an alias first. */
  2242. return alias_diff;
  2243. }
  2244. /* Except for aliases, two "identical" instructions had
  2245. better have the same opcode. This is a sanity check on the table. */
  2246. i = strcmp (op0->name, op1->name);
  2247. if (i)
  2248. {
  2249. if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
  2250. return i;
  2251. else
  2252. fprintf (stderr,
  2253. /* xgettext:c-format */
  2254. _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
  2255. op0->name, op1->name);
  2256. }
  2257. /* Fewer arguments are preferred. */
  2258. {
  2259. int length_diff = strlen (op0->args) - strlen (op1->args);
  2260. if (length_diff != 0)
  2261. /* Put the one with fewer arguments first. */
  2262. return length_diff;
  2263. }
  2264. /* Put 1+i before i+1. */
  2265. {
  2266. char *p0 = (char *) strchr (op0->args, '+');
  2267. char *p1 = (char *) strchr (op1->args, '+');
  2268. if (p0 && p1)
  2269. {
  2270. /* There is a plus in both operands. Note that a plus
  2271. sign cannot be the first character in args,
  2272. so the following [-1]'s are valid. */
  2273. if (p0[-1] == 'i' && p1[1] == 'i')
  2274. /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
  2275. return 1;
  2276. if (p0[1] == 'i' && p1[-1] == 'i')
  2277. /* op0 is 1+i and op1 is i+1, so op0 goes first. */
  2278. return -1;
  2279. }
  2280. }
  2281. /* Put 1,i before i,1. */
  2282. {
  2283. int i0 = strncmp (op0->args, "i,1", 3) == 0;
  2284. int i1 = strncmp (op1->args, "i,1", 3) == 0;
  2285. if (i0 ^ i1)
  2286. return i0 - i1;
  2287. }
  2288. /* They are, as far as we can tell, identical.
  2289. Since qsort may have rearranged the table partially, there is
  2290. no way to tell which one was first in the opcode table as
  2291. written, so just say there are equal. */
  2292. /* ??? This is no longer true now that we sort a vector of pointers,
  2293. not the table itself. */
  2294. return 0;
  2295. }
  2296. /* Build a hash table from the opcode table.
  2297. OPCODE_TABLE is a sorted list of pointers into the opcode table. */
  2298. static void
  2299. build_hash_table (const sparc_opcode **opcode_table,
  2300. sparc_opcode_hash **hash_table,
  2301. int num_opcodes)
  2302. {
  2303. int i;
  2304. int hash_count[HASH_SIZE];
  2305. static sparc_opcode_hash *hash_buf = NULL;
  2306. /* Start at the end of the table and work backwards so that each
  2307. chain is sorted. */
  2308. memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
  2309. memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
  2310. if (hash_buf != NULL)
  2311. free (hash_buf);
  2312. hash_buf = malloc (sizeof (* hash_buf) * num_opcodes);
  2313. for (i = num_opcodes - 1; i >= 0; --i)
  2314. {
  2315. int hash = HASH_INSN (opcode_table[i]->match);
  2316. sparc_opcode_hash *h = &hash_buf[i];
  2317. h->next = hash_table[hash];
  2318. h->opcode = opcode_table[i];
  2319. hash_table[hash] = h;
  2320. ++hash_count[hash];
  2321. }
  2322. #if 0 /* for debugging */
  2323. {
  2324. int min_count = num_opcodes, max_count = 0;
  2325. int total;
  2326. for (i = 0; i < HASH_SIZE; ++i)
  2327. {
  2328. if (hash_count[i] < min_count)
  2329. min_count = hash_count[i];
  2330. if (hash_count[i] > max_count)
  2331. max_count = hash_count[i];
  2332. total += hash_count[i];
  2333. }
  2334. printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
  2335. min_count, max_count, (double) total / HASH_SIZE);
  2336. }
  2337. #endif
  2338. }
  2339. /* Print one instruction from MEMADDR on INFO->STREAM.
  2340. We suffix the instruction with a comment that gives the absolute
  2341. address involved, as well as its symbolic form, if the instruction
  2342. is preceded by a findable `sethi' and it either adds an immediate
  2343. displacement to that register, or it is an `add' or `or' instruction
  2344. on that register. */
  2345. int
  2346. print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
  2347. {
  2348. FILE *stream = info->stream;
  2349. bfd_byte buffer[4];
  2350. unsigned long insn;
  2351. sparc_opcode_hash *op;
  2352. /* Nonzero of opcode table has been initialized. */
  2353. static int opcodes_initialized = 0;
  2354. /* bfd mach number of last call. */
  2355. static unsigned long current_mach = 0;
  2356. bfd_vma (*getword) (const unsigned char *);
  2357. if (!opcodes_initialized
  2358. || info->mach != current_mach)
  2359. {
  2360. int i;
  2361. current_arch_mask = compute_arch_mask (info->mach);
  2362. if (!opcodes_initialized)
  2363. sorted_opcodes =
  2364. malloc (sparc_num_opcodes * sizeof (sparc_opcode *));
  2365. /* Reset the sorted table so we can resort it. */
  2366. for (i = 0; i < sparc_num_opcodes; ++i)
  2367. sorted_opcodes[i] = &sparc_opcodes[i];
  2368. qsort ((char *) sorted_opcodes, sparc_num_opcodes,
  2369. sizeof (sorted_opcodes[0]), compare_opcodes);
  2370. build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
  2371. current_mach = info->mach;
  2372. opcodes_initialized = 1;
  2373. }
  2374. {
  2375. int status =
  2376. (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
  2377. if (status != 0)
  2378. {
  2379. (*info->memory_error_func) (status, memaddr, info);
  2380. return -1;
  2381. }
  2382. }
  2383. /* On SPARClite variants such as DANlite (sparc86x), instructions
  2384. are always big-endian even when the machine is in little-endian mode. */
  2385. if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
  2386. getword = bfd_getb32;
  2387. else
  2388. getword = bfd_getl32;
  2389. insn = getword (buffer);
  2390. info->insn_info_valid = 1; /* We do return this info. */
  2391. info->insn_type = dis_nonbranch; /* Assume non branch insn. */
  2392. info->branch_delay_insns = 0; /* Assume no delay. */
  2393. info->target = 0; /* Assume no target known. */
  2394. for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
  2395. {
  2396. const sparc_opcode *opcode = op->opcode;
  2397. /* If the insn isn't supported by the current architecture, skip it. */
  2398. if (! (opcode->architecture & current_arch_mask))
  2399. continue;
  2400. if ((opcode->match & insn) == opcode->match
  2401. && (opcode->lose & insn) == 0)
  2402. {
  2403. /* Nonzero means that we have found an instruction which has
  2404. the effect of adding or or'ing the imm13 field to rs1. */
  2405. int imm_added_to_rs1 = 0;
  2406. int imm_ored_to_rs1 = 0;
  2407. /* Nonzero means that we have found a plus sign in the args
  2408. field of the opcode table. */
  2409. int found_plus = 0;
  2410. /* Nonzero means we have an annulled branch. */
  2411. /* int is_annulled = 0; */ /* see FIXME below */
  2412. /* Do we have an `add' or `or' instruction combining an
  2413. immediate with rs1? */
  2414. if (opcode->match == 0x80102000) /* or */
  2415. imm_ored_to_rs1 = 1;
  2416. if (opcode->match == 0x80002000) /* add */
  2417. imm_added_to_rs1 = 1;
  2418. if (X_RS1 (insn) != X_RD (insn)
  2419. && strchr (opcode->args, 'r') != NULL)
  2420. /* Can't do simple format if source and dest are different. */
  2421. continue;
  2422. if (X_RS2 (insn) != X_RD (insn)
  2423. && strchr (opcode->args, 'O') != NULL)
  2424. /* Can't do simple format if source and dest are different. */
  2425. continue;
  2426. (*info->fprintf_func) (stream, "%s", opcode->name);
  2427. {
  2428. const char *s;
  2429. if (opcode->args[0] != ',')
  2430. (*info->fprintf_func) (stream, " ");
  2431. for (s = opcode->args; *s != '\0'; ++s)
  2432. {
  2433. while (*s == ',')
  2434. {
  2435. (*info->fprintf_func) (stream, ",");
  2436. ++s;
  2437. switch (*s)
  2438. {
  2439. case 'a':
  2440. (*info->fprintf_func) (stream, "a");
  2441. /* is_annulled = 1; */ /* see FIXME below */
  2442. ++s;
  2443. continue;
  2444. case 'N':
  2445. (*info->fprintf_func) (stream, "pn");
  2446. ++s;
  2447. continue;
  2448. case 'T':
  2449. (*info->fprintf_func) (stream, "pt");
  2450. ++s;
  2451. continue;
  2452. default:
  2453. break;
  2454. }
  2455. }
  2456. (*info->fprintf_func) (stream, " ");
  2457. switch (*s)
  2458. {
  2459. case '+':
  2460. found_plus = 1;
  2461. /* Fall through. */
  2462. default:
  2463. (*info->fprintf_func) (stream, "%c", *s);
  2464. break;
  2465. case '#':
  2466. (*info->fprintf_func) (stream, "0");
  2467. break;
  2468. #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
  2469. case '1':
  2470. case 'r':
  2471. reg (X_RS1 (insn));
  2472. break;
  2473. case '2':
  2474. case 'O':
  2475. reg (X_RS2 (insn));
  2476. break;
  2477. case 'd':
  2478. reg (X_RD (insn));
  2479. break;
  2480. #undef reg
  2481. #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
  2482. #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
  2483. case 'e':
  2484. freg (X_RS1 (insn));
  2485. break;
  2486. case 'v': /* Double/even. */
  2487. case 'V': /* Quad/multiple of 4. */
  2488. fregx (X_RS1 (insn));
  2489. break;
  2490. case 'f':
  2491. freg (X_RS2 (insn));
  2492. break;
  2493. case 'B': /* Double/even. */
  2494. case 'R': /* Quad/multiple of 4. */
  2495. fregx (X_RS2 (insn));
  2496. break;
  2497. case 'g':
  2498. freg (X_RD (insn));
  2499. break;
  2500. case 'H': /* Double/even. */
  2501. case 'J': /* Quad/multiple of 4. */
  2502. fregx (X_RD (insn));
  2503. break;
  2504. #undef freg
  2505. #undef fregx
  2506. #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
  2507. case 'b':
  2508. creg (X_RS1 (insn));
  2509. break;
  2510. case 'c':
  2511. creg (X_RS2 (insn));
  2512. break;
  2513. case 'D':
  2514. creg (X_RD (insn));
  2515. break;
  2516. #undef creg
  2517. case 'h':
  2518. (*info->fprintf_func) (stream, "%%hi(%#x)",
  2519. ((unsigned) 0xFFFFFFFF
  2520. & ((int) X_IMM22 (insn) << 10)));
  2521. break;
  2522. case 'i': /* 13 bit immediate. */
  2523. case 'I': /* 11 bit immediate. */
  2524. case 'j': /* 10 bit immediate. */
  2525. {
  2526. int imm;
  2527. if (*s == 'i')
  2528. imm = X_SIMM (insn, 13);
  2529. else if (*s == 'I')
  2530. imm = X_SIMM (insn, 11);
  2531. else
  2532. imm = X_SIMM (insn, 10);
  2533. /* Check to see whether we have a 1+i, and take
  2534. note of that fact.
  2535. Note: because of the way we sort the table,
  2536. we will be matching 1+i rather than i+1,
  2537. so it is OK to assume that i is after +,
  2538. not before it. */
  2539. if (found_plus)
  2540. imm_added_to_rs1 = 1;
  2541. if (imm <= 9)
  2542. (*info->fprintf_func) (stream, "%d", imm);
  2543. else
  2544. (*info->fprintf_func) (stream, "%#x", imm);
  2545. }
  2546. break;
  2547. case 'X': /* 5 bit unsigned immediate. */
  2548. case 'Y': /* 6 bit unsigned immediate. */
  2549. {
  2550. int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
  2551. if (imm <= 9)
  2552. (info->fprintf_func) (stream, "%d", imm);
  2553. else
  2554. (info->fprintf_func) (stream, "%#x", (unsigned) imm);
  2555. }
  2556. break;
  2557. case '3':
  2558. (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
  2559. break;
  2560. case 'K':
  2561. {
  2562. int mask = X_MEMBAR (insn);
  2563. int bit = 0x40, printed_one = 0;
  2564. const char *name;
  2565. if (mask == 0)
  2566. (info->fprintf_func) (stream, "0");
  2567. else
  2568. while (bit)
  2569. {
  2570. if (mask & bit)
  2571. {
  2572. if (printed_one)
  2573. (info->fprintf_func) (stream, "|");
  2574. name = sparc_decode_membar (bit);
  2575. (info->fprintf_func) (stream, "%s", name);
  2576. printed_one = 1;
  2577. }
  2578. bit >>= 1;
  2579. }
  2580. break;
  2581. }
  2582. case 'k':
  2583. info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
  2584. (*info->print_address_func) (info->target, info);
  2585. break;
  2586. case 'G':
  2587. info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
  2588. (*info->print_address_func) (info->target, info);
  2589. break;
  2590. case '6':
  2591. case '7':
  2592. case '8':
  2593. case '9':
  2594. (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
  2595. break;
  2596. case 'z':
  2597. (*info->fprintf_func) (stream, "%%icc");
  2598. break;
  2599. case 'Z':
  2600. (*info->fprintf_func) (stream, "%%xcc");
  2601. break;
  2602. case 'E':
  2603. (*info->fprintf_func) (stream, "%%ccr");
  2604. break;
  2605. case 's':
  2606. (*info->fprintf_func) (stream, "%%fprs");
  2607. break;
  2608. case 'o':
  2609. (*info->fprintf_func) (stream, "%%asi");
  2610. break;
  2611. case 'W':
  2612. (*info->fprintf_func) (stream, "%%tick");
  2613. break;
  2614. case 'P':
  2615. (*info->fprintf_func) (stream, "%%pc");
  2616. break;
  2617. case '?':
  2618. if (X_RS1 (insn) == 31)
  2619. (*info->fprintf_func) (stream, "%%ver");
  2620. else if ((unsigned) X_RS1 (insn) < 17)
  2621. (*info->fprintf_func) (stream, "%%%s",
  2622. v9_priv_reg_names[X_RS1 (insn)]);
  2623. else
  2624. (*info->fprintf_func) (stream, "%%reserved");
  2625. break;
  2626. case '!':
  2627. if ((unsigned) X_RD (insn) < 17)
  2628. (*info->fprintf_func) (stream, "%%%s",
  2629. v9_priv_reg_names[X_RD (insn)]);
  2630. else
  2631. (*info->fprintf_func) (stream, "%%reserved");
  2632. break;
  2633. case '$':
  2634. if ((unsigned) X_RS1 (insn) < 32)
  2635. (*info->fprintf_func) (stream, "%%%s",
  2636. v9_hpriv_reg_names[X_RS1 (insn)]);
  2637. else
  2638. (*info->fprintf_func) (stream, "%%reserved");
  2639. break;
  2640. case '%':
  2641. if ((unsigned) X_RD (insn) < 32)
  2642. (*info->fprintf_func) (stream, "%%%s",
  2643. v9_hpriv_reg_names[X_RD (insn)]);
  2644. else
  2645. (*info->fprintf_func) (stream, "%%reserved");
  2646. break;
  2647. case '/':
  2648. if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
  2649. (*info->fprintf_func) (stream, "%%reserved");
  2650. else
  2651. (*info->fprintf_func) (stream, "%%%s",
  2652. v9a_asr_reg_names[X_RS1 (insn)-16]);
  2653. break;
  2654. case '_':
  2655. if (X_RD (insn) < 16 || X_RD (insn) > 25)
  2656. (*info->fprintf_func) (stream, "%%reserved");
  2657. else
  2658. (*info->fprintf_func) (stream, "%%%s",
  2659. v9a_asr_reg_names[X_RD (insn)-16]);
  2660. break;
  2661. case '*':
  2662. {
  2663. const char *name = sparc_decode_prefetch (X_RD (insn));
  2664. if (name)
  2665. (*info->fprintf_func) (stream, "%s", name);
  2666. else
  2667. (*info->fprintf_func) (stream, "%ld", X_RD (insn));
  2668. break;
  2669. }
  2670. case 'M':
  2671. (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
  2672. break;
  2673. case 'm':
  2674. (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
  2675. break;
  2676. case 'L':
  2677. info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
  2678. (*info->print_address_func) (info->target, info);
  2679. break;
  2680. case 'n':
  2681. (*info->fprintf_func)
  2682. (stream, "%#x", SEX (X_DISP22 (insn), 22));
  2683. break;
  2684. case 'l':
  2685. info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
  2686. (*info->print_address_func) (info->target, info);
  2687. break;
  2688. case 'A':
  2689. {
  2690. const char *name;
  2691. if ((info->mach == bfd_mach_sparc_v8plusa) ||
  2692. ((info->mach >= bfd_mach_sparc_v9) &&
  2693. (info->mach <= bfd_mach_sparc_v9b)))
  2694. name = sparc_decode_asi_v9 (X_ASI (insn));
  2695. else
  2696. name = sparc_decode_asi_v8 (X_ASI (insn));
  2697. if (name)
  2698. (*info->fprintf_func) (stream, "%s", name);
  2699. else
  2700. (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
  2701. break;
  2702. }
  2703. case 'C':
  2704. (*info->fprintf_func) (stream, "%%csr");
  2705. break;
  2706. case 'F':
  2707. (*info->fprintf_func) (stream, "%%fsr");
  2708. break;
  2709. case 'p':
  2710. (*info->fprintf_func) (stream, "%%psr");
  2711. break;
  2712. case 'q':
  2713. (*info->fprintf_func) (stream, "%%fq");
  2714. break;
  2715. case 'Q':
  2716. (*info->fprintf_func) (stream, "%%cq");
  2717. break;
  2718. case 't':
  2719. (*info->fprintf_func) (stream, "%%tbr");
  2720. break;
  2721. case 'w':
  2722. (*info->fprintf_func) (stream, "%%wim");
  2723. break;
  2724. case 'x':
  2725. (*info->fprintf_func) (stream, "%ld",
  2726. ((X_LDST_I (insn) << 8)
  2727. + X_ASI (insn)));
  2728. break;
  2729. case 'y':
  2730. (*info->fprintf_func) (stream, "%%y");
  2731. break;
  2732. case 'u':
  2733. case 'U':
  2734. {
  2735. int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
  2736. const char *name = sparc_decode_sparclet_cpreg (val);
  2737. if (name)
  2738. (*info->fprintf_func) (stream, "%s", name);
  2739. else
  2740. (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
  2741. break;
  2742. }
  2743. }
  2744. }
  2745. }
  2746. /* If we are adding or or'ing something to rs1, then
  2747. check to see whether the previous instruction was
  2748. a sethi to the same register as in the sethi.
  2749. If so, attempt to print the result of the add or
  2750. or (in this context add and or do the same thing)
  2751. and its symbolic value. */
  2752. if (imm_ored_to_rs1 || imm_added_to_rs1)
  2753. {
  2754. unsigned long prev_insn;
  2755. int errcode;
  2756. if (memaddr >= 4)
  2757. errcode =
  2758. (*info->read_memory_func)
  2759. (memaddr - 4, buffer, sizeof (buffer), info);
  2760. else
  2761. errcode = 1;
  2762. prev_insn = getword (buffer);
  2763. if (errcode == 0)
  2764. {
  2765. /* If it is a delayed branch, we need to look at the
  2766. instruction before the delayed branch. This handles
  2767. sequences such as:
  2768. sethi %o1, %hi(_foo), %o1
  2769. call _printf
  2770. or %o1, %lo(_foo), %o1 */
  2771. if (is_delayed_branch (prev_insn))
  2772. {
  2773. if (memaddr >= 8)
  2774. errcode = (*info->read_memory_func)
  2775. (memaddr - 8, buffer, sizeof (buffer), info);
  2776. else
  2777. errcode = 1;
  2778. prev_insn = getword (buffer);
  2779. }
  2780. }
  2781. /* If there was a problem reading memory, then assume
  2782. the previous instruction was not sethi. */
  2783. if (errcode == 0)
  2784. {
  2785. /* Is it sethi to the same register? */
  2786. if ((prev_insn & 0xc1c00000) == 0x01000000
  2787. && X_RD (prev_insn) == X_RS1 (insn))
  2788. {
  2789. (*info->fprintf_func) (stream, "\t! ");
  2790. info->target =
  2791. ((unsigned) 0xFFFFFFFF
  2792. & ((int) X_IMM22 (prev_insn) << 10));
  2793. if (imm_added_to_rs1)
  2794. info->target += X_SIMM (insn, 13);
  2795. else
  2796. info->target |= X_SIMM (insn, 13);
  2797. (*info->print_address_func) (info->target, info);
  2798. info->insn_type = dis_dref;
  2799. info->data_size = 4; /* FIXME!!! */
  2800. }
  2801. }
  2802. }
  2803. if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
  2804. {
  2805. /* FIXME -- check is_annulled flag. */
  2806. if (opcode->flags & F_UNBR)
  2807. info->insn_type = dis_branch;
  2808. if (opcode->flags & F_CONDBR)
  2809. info->insn_type = dis_condbranch;
  2810. if (opcode->flags & F_JSR)
  2811. info->insn_type = dis_jsr;
  2812. if (opcode->flags & F_DELAYED)
  2813. info->branch_delay_insns = 1;
  2814. }
  2815. return sizeof (buffer);
  2816. }
  2817. }
  2818. info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
  2819. (*info->fprintf_func) (stream, _("unknown"));
  2820. return sizeof (buffer);
  2821. }