qtest.c 11 KB

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  1. /*
  2. * Test Server
  3. *
  4. * Copyright IBM, Corp. 2011
  5. *
  6. * Authors:
  7. * Anthony Liguori <aliguori@us.ibm.com>
  8. *
  9. * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10. * See the COPYING file in the top-level directory.
  11. *
  12. */
  13. #include "qtest.h"
  14. #include "hw/qdev.h"
  15. #include "qemu-char.h"
  16. #include "ioport.h"
  17. #include "memory.h"
  18. #include "hw/irq.h"
  19. #include "sysemu.h"
  20. #include "cpus.h"
  21. #define MAX_IRQ 256
  22. const char *qtest_chrdev;
  23. const char *qtest_log;
  24. int qtest_allowed = 0;
  25. static DeviceState *irq_intercept_dev;
  26. static FILE *qtest_log_fp;
  27. static CharDriverState *qtest_chr;
  28. static GString *inbuf;
  29. static int irq_levels[MAX_IRQ];
  30. static qemu_timeval start_time;
  31. static bool qtest_opened;
  32. #define FMT_timeval "%ld.%06ld"
  33. /**
  34. * QTest Protocol
  35. *
  36. * Line based protocol, request/response based. Server can send async messages
  37. * so clients should always handle many async messages before the response
  38. * comes in.
  39. *
  40. * Valid requests
  41. *
  42. * Clock management:
  43. *
  44. * The qtest client is completely in charge of the vm_clock. qtest commands
  45. * let you adjust the value of the clock (monotonically). All the commands
  46. * return the current value of the clock in nanoseconds.
  47. *
  48. * > clock_step
  49. * < OK VALUE
  50. *
  51. * Advance the clock to the next deadline. Useful when waiting for
  52. * asynchronous events.
  53. *
  54. * > clock_step NS
  55. * < OK VALUE
  56. *
  57. * Advance the clock by NS nanoseconds.
  58. *
  59. * > clock_set NS
  60. * < OK VALUE
  61. *
  62. * Advance the clock to NS nanoseconds (do nothing if it's already past).
  63. *
  64. * PIO and memory access:
  65. *
  66. * > outb ADDR VALUE
  67. * < OK
  68. *
  69. * > outw ADDR VALUE
  70. * < OK
  71. *
  72. * > outl ADDR VALUE
  73. * < OK
  74. *
  75. * > inb ADDR
  76. * < OK VALUE
  77. *
  78. * > inw ADDR
  79. * < OK VALUE
  80. *
  81. * > inl ADDR
  82. * < OK VALUE
  83. *
  84. * > read ADDR SIZE
  85. * < OK DATA
  86. *
  87. * > write ADDR SIZE DATA
  88. * < OK
  89. *
  90. * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
  91. *
  92. * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
  93. * than the expected size, the value will be zero filled at the end of the data
  94. * sequence.
  95. *
  96. * IRQ management:
  97. *
  98. * > irq_intercept_in QOM-PATH
  99. * < OK
  100. *
  101. * > irq_intercept_out QOM-PATH
  102. * < OK
  103. *
  104. * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
  105. * QOM-PATH. When the pin is triggered, one of the following async messages
  106. * will be printed to the qtest stream:
  107. *
  108. * IRQ raise NUM
  109. * IRQ lower NUM
  110. *
  111. * where NUM is an IRQ number. For the PC, interrupts can be intercepted
  112. * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
  113. * NUM=0 even though it is remapped to GSI 2).
  114. */
  115. static int hex2nib(char ch)
  116. {
  117. if (ch >= '0' && ch <= '9') {
  118. return ch - '0';
  119. } else if (ch >= 'a' && ch <= 'f') {
  120. return 10 + (ch - 'a');
  121. } else if (ch >= 'A' && ch <= 'F') {
  122. return 10 + (ch - 'a');
  123. } else {
  124. return -1;
  125. }
  126. }
  127. static void qtest_get_time(qemu_timeval *tv)
  128. {
  129. qemu_gettimeofday(tv);
  130. tv->tv_sec -= start_time.tv_sec;
  131. tv->tv_usec -= start_time.tv_usec;
  132. if (tv->tv_usec < 0) {
  133. tv->tv_usec += 1000000;
  134. tv->tv_sec -= 1;
  135. }
  136. }
  137. static void qtest_send_prefix(CharDriverState *chr)
  138. {
  139. qemu_timeval tv;
  140. if (!qtest_log_fp || !qtest_opened) {
  141. return;
  142. }
  143. qtest_get_time(&tv);
  144. fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
  145. tv.tv_sec, (long) tv.tv_usec);
  146. }
  147. static void GCC_FMT_ATTR(2, 3) qtest_send(CharDriverState *chr,
  148. const char *fmt, ...)
  149. {
  150. va_list ap;
  151. char buffer[1024];
  152. size_t len;
  153. va_start(ap, fmt);
  154. len = vsnprintf(buffer, sizeof(buffer), fmt, ap);
  155. va_end(ap);
  156. qemu_chr_fe_write(chr, (uint8_t *)buffer, len);
  157. if (qtest_log_fp && qtest_opened) {
  158. fprintf(qtest_log_fp, "%s", buffer);
  159. }
  160. }
  161. static void qtest_irq_handler(void *opaque, int n, int level)
  162. {
  163. qemu_irq *old_irqs = opaque;
  164. qemu_set_irq(old_irqs[n], level);
  165. if (irq_levels[n] != level) {
  166. CharDriverState *chr = qtest_chr;
  167. irq_levels[n] = level;
  168. qtest_send_prefix(chr);
  169. qtest_send(chr, "IRQ %s %d\n",
  170. level ? "raise" : "lower", n);
  171. }
  172. }
  173. static void qtest_process_command(CharDriverState *chr, gchar **words)
  174. {
  175. const gchar *command;
  176. g_assert(words);
  177. command = words[0];
  178. if (qtest_log_fp) {
  179. qemu_timeval tv;
  180. int i;
  181. qtest_get_time(&tv);
  182. fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
  183. tv.tv_sec, (long) tv.tv_usec);
  184. for (i = 0; words[i]; i++) {
  185. fprintf(qtest_log_fp, " %s", words[i]);
  186. }
  187. fprintf(qtest_log_fp, "\n");
  188. }
  189. g_assert(command);
  190. if (strcmp(words[0], "irq_intercept_out") == 0
  191. || strcmp(words[0], "irq_intercept_in") == 0) {
  192. DeviceState *dev;
  193. g_assert(words[1]);
  194. dev = DEVICE(object_resolve_path(words[1], NULL));
  195. if (!dev) {
  196. qtest_send_prefix(chr);
  197. qtest_send(chr, "FAIL Unknown device\n");
  198. return;
  199. }
  200. if (irq_intercept_dev) {
  201. qtest_send_prefix(chr);
  202. if (irq_intercept_dev != dev) {
  203. qtest_send(chr, "FAIL IRQ intercept already enabled\n");
  204. } else {
  205. qtest_send(chr, "OK\n");
  206. }
  207. return;
  208. }
  209. if (words[0][14] == 'o') {
  210. qemu_irq_intercept_out(&dev->gpio_out, qtest_irq_handler, dev->num_gpio_out);
  211. } else {
  212. qemu_irq_intercept_in(dev->gpio_in, qtest_irq_handler, dev->num_gpio_in);
  213. }
  214. irq_intercept_dev = dev;
  215. qtest_send_prefix(chr);
  216. qtest_send(chr, "OK\n");
  217. } else if (strcmp(words[0], "outb") == 0 ||
  218. strcmp(words[0], "outw") == 0 ||
  219. strcmp(words[0], "outl") == 0) {
  220. uint16_t addr;
  221. uint32_t value;
  222. g_assert(words[1] && words[2]);
  223. addr = strtol(words[1], NULL, 0);
  224. value = strtol(words[2], NULL, 0);
  225. if (words[0][3] == 'b') {
  226. cpu_outb(addr, value);
  227. } else if (words[0][3] == 'w') {
  228. cpu_outw(addr, value);
  229. } else if (words[0][3] == 'l') {
  230. cpu_outl(addr, value);
  231. }
  232. qtest_send_prefix(chr);
  233. qtest_send(chr, "OK\n");
  234. } else if (strcmp(words[0], "inb") == 0 ||
  235. strcmp(words[0], "inw") == 0 ||
  236. strcmp(words[0], "inl") == 0) {
  237. uint16_t addr;
  238. uint32_t value = -1U;
  239. g_assert(words[1]);
  240. addr = strtol(words[1], NULL, 0);
  241. if (words[0][2] == 'b') {
  242. value = cpu_inb(addr);
  243. } else if (words[0][2] == 'w') {
  244. value = cpu_inw(addr);
  245. } else if (words[0][2] == 'l') {
  246. value = cpu_inl(addr);
  247. }
  248. qtest_send_prefix(chr);
  249. qtest_send(chr, "OK 0x%04x\n", value);
  250. } else if (strcmp(words[0], "read") == 0) {
  251. uint64_t addr, len, i;
  252. uint8_t *data;
  253. g_assert(words[1] && words[2]);
  254. addr = strtoul(words[1], NULL, 0);
  255. len = strtoul(words[2], NULL, 0);
  256. data = g_malloc(len);
  257. cpu_physical_memory_read(addr, data, len);
  258. qtest_send_prefix(chr);
  259. qtest_send(chr, "OK 0x");
  260. for (i = 0; i < len; i++) {
  261. qtest_send(chr, "%02x", data[i]);
  262. }
  263. qtest_send(chr, "\n");
  264. g_free(data);
  265. } else if (strcmp(words[0], "write") == 0) {
  266. uint64_t addr, len, i;
  267. uint8_t *data;
  268. size_t data_len;
  269. g_assert(words[1] && words[2] && words[3]);
  270. addr = strtoul(words[1], NULL, 0);
  271. len = strtoul(words[2], NULL, 0);
  272. data_len = strlen(words[3]);
  273. if (data_len < 3) {
  274. qtest_send(chr, "ERR invalid argument size\n");
  275. return;
  276. }
  277. data = g_malloc(len);
  278. for (i = 0; i < len; i++) {
  279. if ((i * 2 + 4) <= data_len) {
  280. data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
  281. data[i] |= hex2nib(words[3][i * 2 + 3]);
  282. } else {
  283. data[i] = 0;
  284. }
  285. }
  286. cpu_physical_memory_write(addr, data, len);
  287. g_free(data);
  288. qtest_send_prefix(chr);
  289. qtest_send(chr, "OK\n");
  290. } else if (strcmp(words[0], "clock_step") == 0) {
  291. int64_t ns;
  292. if (words[1]) {
  293. ns = strtoll(words[1], NULL, 0);
  294. } else {
  295. ns = qemu_clock_deadline(vm_clock);
  296. }
  297. qtest_clock_warp(qemu_get_clock_ns(vm_clock) + ns);
  298. qtest_send_prefix(chr);
  299. qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_get_clock_ns(vm_clock));
  300. } else if (strcmp(words[0], "clock_set") == 0) {
  301. int64_t ns;
  302. g_assert(words[1]);
  303. ns = strtoll(words[1], NULL, 0);
  304. qtest_clock_warp(ns);
  305. qtest_send_prefix(chr);
  306. qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_get_clock_ns(vm_clock));
  307. } else {
  308. qtest_send_prefix(chr);
  309. qtest_send(chr, "FAIL Unknown command `%s'\n", words[0]);
  310. }
  311. }
  312. static void qtest_process_inbuf(CharDriverState *chr, GString *inbuf)
  313. {
  314. char *end;
  315. while ((end = strchr(inbuf->str, '\n')) != NULL) {
  316. size_t offset;
  317. GString *cmd;
  318. gchar **words;
  319. offset = end - inbuf->str;
  320. cmd = g_string_new_len(inbuf->str, offset);
  321. g_string_erase(inbuf, 0, offset + 1);
  322. words = g_strsplit(cmd->str, " ", 0);
  323. qtest_process_command(chr, words);
  324. g_strfreev(words);
  325. g_string_free(cmd, TRUE);
  326. }
  327. }
  328. static void qtest_read(void *opaque, const uint8_t *buf, int size)
  329. {
  330. CharDriverState *chr = opaque;
  331. g_string_append_len(inbuf, (const gchar *)buf, size);
  332. qtest_process_inbuf(chr, inbuf);
  333. }
  334. static int qtest_can_read(void *opaque)
  335. {
  336. return 1024;
  337. }
  338. static void qtest_event(void *opaque, int event)
  339. {
  340. int i;
  341. switch (event) {
  342. case CHR_EVENT_OPENED:
  343. qemu_system_reset(false);
  344. for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
  345. irq_levels[i] = 0;
  346. }
  347. qemu_gettimeofday(&start_time);
  348. qtest_opened = true;
  349. if (qtest_log_fp) {
  350. fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
  351. start_time.tv_sec, (long) start_time.tv_usec);
  352. }
  353. break;
  354. case CHR_EVENT_CLOSED:
  355. qtest_opened = false;
  356. if (qtest_log_fp) {
  357. qemu_timeval tv;
  358. qtest_get_time(&tv);
  359. fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
  360. tv.tv_sec, (long) tv.tv_usec);
  361. }
  362. break;
  363. default:
  364. break;
  365. }
  366. }
  367. int qtest_init(void)
  368. {
  369. CharDriverState *chr;
  370. g_assert(qtest_chrdev != NULL);
  371. configure_icount("0");
  372. chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
  373. qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
  374. qemu_chr_fe_set_echo(chr, true);
  375. inbuf = g_string_new("");
  376. if (qtest_log) {
  377. if (strcmp(qtest_log, "none") != 0) {
  378. qtest_log_fp = fopen(qtest_log, "w+");
  379. }
  380. } else {
  381. qtest_log_fp = stderr;
  382. }
  383. qtest_chr = chr;
  384. return 0;
  385. }