vmware_vga.c 34 KB

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  1. /*
  2. * QEMU VMware-SVGA "chipset".
  3. *
  4. * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. */
  24. #include "hw.h"
  25. #include "loader.h"
  26. #include "console.h"
  27. #include "pci.h"
  28. #include "vmware_vga.h"
  29. #undef VERBOSE
  30. #define HW_RECT_ACCEL
  31. #define HW_FILL_ACCEL
  32. #define HW_MOUSE_ACCEL
  33. # include "vga_int.h"
  34. struct vmsvga_state_s {
  35. VGACommonState vga;
  36. int width;
  37. int height;
  38. int invalidated;
  39. int depth;
  40. int bypp;
  41. int enable;
  42. int config;
  43. struct {
  44. int id;
  45. int x;
  46. int y;
  47. int on;
  48. } cursor;
  49. int index;
  50. int scratch_size;
  51. uint32_t *scratch;
  52. int new_width;
  53. int new_height;
  54. uint32_t guest;
  55. uint32_t svgaid;
  56. uint32_t wred;
  57. uint32_t wgreen;
  58. uint32_t wblue;
  59. int syncing;
  60. int fb_size;
  61. MemoryRegion fifo_ram;
  62. uint8_t *fifo_ptr;
  63. unsigned int fifo_size;
  64. union {
  65. uint32_t *fifo;
  66. struct QEMU_PACKED {
  67. uint32_t min;
  68. uint32_t max;
  69. uint32_t next_cmd;
  70. uint32_t stop;
  71. /* Add registers here when adding capabilities. */
  72. uint32_t fifo[0];
  73. } *cmd;
  74. };
  75. #define REDRAW_FIFO_LEN 512
  76. struct vmsvga_rect_s {
  77. int x, y, w, h;
  78. } redraw_fifo[REDRAW_FIFO_LEN];
  79. int redraw_fifo_first, redraw_fifo_last;
  80. };
  81. struct pci_vmsvga_state_s {
  82. PCIDevice card;
  83. struct vmsvga_state_s chip;
  84. MemoryRegion io_bar;
  85. };
  86. #define SVGA_MAGIC 0x900000UL
  87. #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
  88. #define SVGA_ID_0 SVGA_MAKE_ID(0)
  89. #define SVGA_ID_1 SVGA_MAKE_ID(1)
  90. #define SVGA_ID_2 SVGA_MAKE_ID(2)
  91. #define SVGA_LEGACY_BASE_PORT 0x4560
  92. #define SVGA_INDEX_PORT 0x0
  93. #define SVGA_VALUE_PORT 0x1
  94. #define SVGA_BIOS_PORT 0x2
  95. #define SVGA_VERSION_2
  96. #ifdef SVGA_VERSION_2
  97. # define SVGA_ID SVGA_ID_2
  98. # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
  99. # define SVGA_IO_MUL 1
  100. # define SVGA_FIFO_SIZE 0x10000
  101. # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
  102. #else
  103. # define SVGA_ID SVGA_ID_1
  104. # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
  105. # define SVGA_IO_MUL 4
  106. # define SVGA_FIFO_SIZE 0x10000
  107. # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
  108. #endif
  109. enum {
  110. /* ID 0, 1 and 2 registers */
  111. SVGA_REG_ID = 0,
  112. SVGA_REG_ENABLE = 1,
  113. SVGA_REG_WIDTH = 2,
  114. SVGA_REG_HEIGHT = 3,
  115. SVGA_REG_MAX_WIDTH = 4,
  116. SVGA_REG_MAX_HEIGHT = 5,
  117. SVGA_REG_DEPTH = 6,
  118. SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
  119. SVGA_REG_PSEUDOCOLOR = 8,
  120. SVGA_REG_RED_MASK = 9,
  121. SVGA_REG_GREEN_MASK = 10,
  122. SVGA_REG_BLUE_MASK = 11,
  123. SVGA_REG_BYTES_PER_LINE = 12,
  124. SVGA_REG_FB_START = 13,
  125. SVGA_REG_FB_OFFSET = 14,
  126. SVGA_REG_VRAM_SIZE = 15,
  127. SVGA_REG_FB_SIZE = 16,
  128. /* ID 1 and 2 registers */
  129. SVGA_REG_CAPABILITIES = 17,
  130. SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
  131. SVGA_REG_MEM_SIZE = 19,
  132. SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
  133. SVGA_REG_SYNC = 21, /* Write to force synchronization */
  134. SVGA_REG_BUSY = 22, /* Read to check if sync is done */
  135. SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
  136. SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
  137. SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
  138. SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
  139. SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
  140. SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
  141. SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
  142. SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
  143. SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
  144. SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
  145. SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
  146. SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
  147. SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
  148. };
  149. #define SVGA_CAP_NONE 0
  150. #define SVGA_CAP_RECT_FILL (1 << 0)
  151. #define SVGA_CAP_RECT_COPY (1 << 1)
  152. #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
  153. #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
  154. #define SVGA_CAP_RASTER_OP (1 << 4)
  155. #define SVGA_CAP_CURSOR (1 << 5)
  156. #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
  157. #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
  158. #define SVGA_CAP_8BIT_EMULATION (1 << 8)
  159. #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
  160. #define SVGA_CAP_GLYPH (1 << 10)
  161. #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
  162. #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
  163. #define SVGA_CAP_ALPHA_BLEND (1 << 13)
  164. #define SVGA_CAP_3D (1 << 14)
  165. #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
  166. #define SVGA_CAP_MULTIMON (1 << 16)
  167. #define SVGA_CAP_PITCHLOCK (1 << 17)
  168. /*
  169. * FIFO offsets (seen as an array of 32-bit words)
  170. */
  171. enum {
  172. /*
  173. * The original defined FIFO offsets
  174. */
  175. SVGA_FIFO_MIN = 0,
  176. SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
  177. SVGA_FIFO_NEXT_CMD,
  178. SVGA_FIFO_STOP,
  179. /*
  180. * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
  181. */
  182. SVGA_FIFO_CAPABILITIES = 4,
  183. SVGA_FIFO_FLAGS,
  184. SVGA_FIFO_FENCE,
  185. SVGA_FIFO_3D_HWVERSION,
  186. SVGA_FIFO_PITCHLOCK,
  187. };
  188. #define SVGA_FIFO_CAP_NONE 0
  189. #define SVGA_FIFO_CAP_FENCE (1 << 0)
  190. #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
  191. #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
  192. #define SVGA_FIFO_FLAG_NONE 0
  193. #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
  194. /* These values can probably be changed arbitrarily. */
  195. #define SVGA_SCRATCH_SIZE 0x8000
  196. #define SVGA_MAX_WIDTH 2360
  197. #define SVGA_MAX_HEIGHT 1770
  198. #ifdef VERBOSE
  199. # define GUEST_OS_BASE 0x5001
  200. static const char *vmsvga_guest_id[] = {
  201. [0x00] = "Dos",
  202. [0x01] = "Windows 3.1",
  203. [0x02] = "Windows 95",
  204. [0x03] = "Windows 98",
  205. [0x04] = "Windows ME",
  206. [0x05] = "Windows NT",
  207. [0x06] = "Windows 2000",
  208. [0x07] = "Linux",
  209. [0x08] = "OS/2",
  210. [0x09] = "an unknown OS",
  211. [0x0a] = "BSD",
  212. [0x0b] = "Whistler",
  213. [0x0c] = "an unknown OS",
  214. [0x0d] = "an unknown OS",
  215. [0x0e] = "an unknown OS",
  216. [0x0f] = "an unknown OS",
  217. [0x10] = "an unknown OS",
  218. [0x11] = "an unknown OS",
  219. [0x12] = "an unknown OS",
  220. [0x13] = "an unknown OS",
  221. [0x14] = "an unknown OS",
  222. [0x15] = "Windows 2003",
  223. };
  224. #endif
  225. enum {
  226. SVGA_CMD_INVALID_CMD = 0,
  227. SVGA_CMD_UPDATE = 1,
  228. SVGA_CMD_RECT_FILL = 2,
  229. SVGA_CMD_RECT_COPY = 3,
  230. SVGA_CMD_DEFINE_BITMAP = 4,
  231. SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
  232. SVGA_CMD_DEFINE_PIXMAP = 6,
  233. SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
  234. SVGA_CMD_RECT_BITMAP_FILL = 8,
  235. SVGA_CMD_RECT_PIXMAP_FILL = 9,
  236. SVGA_CMD_RECT_BITMAP_COPY = 10,
  237. SVGA_CMD_RECT_PIXMAP_COPY = 11,
  238. SVGA_CMD_FREE_OBJECT = 12,
  239. SVGA_CMD_RECT_ROP_FILL = 13,
  240. SVGA_CMD_RECT_ROP_COPY = 14,
  241. SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
  242. SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
  243. SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
  244. SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
  245. SVGA_CMD_DEFINE_CURSOR = 19,
  246. SVGA_CMD_DISPLAY_CURSOR = 20,
  247. SVGA_CMD_MOVE_CURSOR = 21,
  248. SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
  249. SVGA_CMD_DRAW_GLYPH = 23,
  250. SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
  251. SVGA_CMD_UPDATE_VERBOSE = 25,
  252. SVGA_CMD_SURFACE_FILL = 26,
  253. SVGA_CMD_SURFACE_COPY = 27,
  254. SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
  255. SVGA_CMD_FRONT_ROP_FILL = 29,
  256. SVGA_CMD_FENCE = 30,
  257. };
  258. /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
  259. enum {
  260. SVGA_CURSOR_ON_HIDE = 0,
  261. SVGA_CURSOR_ON_SHOW = 1,
  262. SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
  263. SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
  264. };
  265. static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
  266. int x, int y, int w, int h)
  267. {
  268. int line;
  269. int bypl;
  270. int width;
  271. int start;
  272. uint8_t *src;
  273. uint8_t *dst;
  274. if (x + w > s->width) {
  275. fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
  276. __FUNCTION__, x, w);
  277. x = MIN(x, s->width);
  278. w = s->width - x;
  279. }
  280. if (y + h > s->height) {
  281. fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
  282. __FUNCTION__, y, h);
  283. y = MIN(y, s->height);
  284. h = s->height - y;
  285. }
  286. line = h;
  287. bypl = s->bypp * s->width;
  288. width = s->bypp * w;
  289. start = s->bypp * x + bypl * y;
  290. src = s->vga.vram_ptr + start;
  291. dst = ds_get_data(s->vga.ds) + start;
  292. for (; line > 0; line --, src += bypl, dst += bypl)
  293. memcpy(dst, src, width);
  294. dpy_update(s->vga.ds, x, y, w, h);
  295. }
  296. static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
  297. {
  298. memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr,
  299. s->bypp * s->width * s->height);
  300. dpy_update(s->vga.ds, 0, 0, s->width, s->height);
  301. }
  302. static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
  303. int x, int y, int w, int h)
  304. {
  305. struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
  306. s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
  307. rect->x = x;
  308. rect->y = y;
  309. rect->w = w;
  310. rect->h = h;
  311. }
  312. static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
  313. {
  314. struct vmsvga_rect_s *rect;
  315. if (s->invalidated) {
  316. s->redraw_fifo_first = s->redraw_fifo_last;
  317. return;
  318. }
  319. /* Overlapping region updates can be optimised out here - if someone
  320. * knows a smart algorithm to do that, please share. */
  321. while (s->redraw_fifo_first != s->redraw_fifo_last) {
  322. rect = &s->redraw_fifo[s->redraw_fifo_first ++];
  323. s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
  324. vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
  325. }
  326. }
  327. #ifdef HW_RECT_ACCEL
  328. static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
  329. int x0, int y0, int x1, int y1, int w, int h)
  330. {
  331. uint8_t *vram = s->vga.vram_ptr;
  332. int bypl = s->bypp * s->width;
  333. int width = s->bypp * w;
  334. int line = h;
  335. uint8_t *ptr[2];
  336. if (y1 > y0) {
  337. ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
  338. ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
  339. for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
  340. memmove(ptr[1], ptr[0], width);
  341. }
  342. } else {
  343. ptr[0] = vram + s->bypp * x0 + bypl * y0;
  344. ptr[1] = vram + s->bypp * x1 + bypl * y1;
  345. for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
  346. memmove(ptr[1], ptr[0], width);
  347. }
  348. }
  349. vmsvga_update_rect_delayed(s, x1, y1, w, h);
  350. }
  351. #endif
  352. #ifdef HW_FILL_ACCEL
  353. static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
  354. uint32_t c, int x, int y, int w, int h)
  355. {
  356. uint8_t *vram = s->vga.vram_ptr;
  357. int bypp = s->bypp;
  358. int bypl = bypp * s->width;
  359. int width = bypp * w;
  360. int line = h;
  361. int column;
  362. uint8_t *fst = vram + bypp * x + bypl * y;
  363. uint8_t *dst;
  364. uint8_t *src;
  365. uint8_t col[4];
  366. col[0] = c;
  367. col[1] = c >> 8;
  368. col[2] = c >> 16;
  369. col[3] = c >> 24;
  370. if (line--) {
  371. dst = fst;
  372. src = col;
  373. for (column = width; column > 0; column--) {
  374. *(dst++) = *(src++);
  375. if (src - col == bypp) {
  376. src = col;
  377. }
  378. }
  379. dst = fst;
  380. for (; line > 0; line--) {
  381. dst += bypl;
  382. memcpy(dst, fst, width);
  383. }
  384. }
  385. vmsvga_update_rect_delayed(s, x, y, w, h);
  386. }
  387. #endif
  388. struct vmsvga_cursor_definition_s {
  389. int width;
  390. int height;
  391. int id;
  392. int bpp;
  393. int hot_x;
  394. int hot_y;
  395. uint32_t mask[1024];
  396. uint32_t image[4096];
  397. };
  398. #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
  399. #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
  400. #ifdef HW_MOUSE_ACCEL
  401. static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
  402. struct vmsvga_cursor_definition_s *c)
  403. {
  404. QEMUCursor *qc;
  405. int i, pixels;
  406. qc = cursor_alloc(c->width, c->height);
  407. qc->hot_x = c->hot_x;
  408. qc->hot_y = c->hot_y;
  409. switch (c->bpp) {
  410. case 1:
  411. cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image,
  412. 1, (void*)c->mask);
  413. #ifdef DEBUG
  414. cursor_print_ascii_art(qc, "vmware/mono");
  415. #endif
  416. break;
  417. case 32:
  418. /* fill alpha channel from mask, set color to zero */
  419. cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask,
  420. 1, (void*)c->mask);
  421. /* add in rgb values */
  422. pixels = c->width * c->height;
  423. for (i = 0; i < pixels; i++) {
  424. qc->data[i] |= c->image[i] & 0xffffff;
  425. }
  426. #ifdef DEBUG
  427. cursor_print_ascii_art(qc, "vmware/32bit");
  428. #endif
  429. break;
  430. default:
  431. fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
  432. __FUNCTION__, c->bpp);
  433. cursor_put(qc);
  434. qc = cursor_builtin_left_ptr();
  435. }
  436. if (s->vga.ds->cursor_define)
  437. s->vga.ds->cursor_define(qc);
  438. cursor_put(qc);
  439. }
  440. #endif
  441. #define CMD(f) le32_to_cpu(s->cmd->f)
  442. static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
  443. {
  444. int num;
  445. if (!s->config || !s->enable)
  446. return 0;
  447. num = CMD(next_cmd) - CMD(stop);
  448. if (num < 0)
  449. num += CMD(max) - CMD(min);
  450. return num >> 2;
  451. }
  452. static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
  453. {
  454. uint32_t cmd = s->fifo[CMD(stop) >> 2];
  455. s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
  456. if (CMD(stop) >= CMD(max))
  457. s->cmd->stop = s->cmd->min;
  458. return cmd;
  459. }
  460. static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
  461. {
  462. return le32_to_cpu(vmsvga_fifo_read_raw(s));
  463. }
  464. static void vmsvga_fifo_run(struct vmsvga_state_s *s)
  465. {
  466. uint32_t cmd, colour;
  467. int args, len;
  468. int x, y, dx, dy, width, height;
  469. struct vmsvga_cursor_definition_s cursor;
  470. uint32_t cmd_start;
  471. len = vmsvga_fifo_length(s);
  472. while (len > 0) {
  473. /* May need to go back to the start of the command if incomplete */
  474. cmd_start = s->cmd->stop;
  475. switch (cmd = vmsvga_fifo_read(s)) {
  476. case SVGA_CMD_UPDATE:
  477. case SVGA_CMD_UPDATE_VERBOSE:
  478. len -= 5;
  479. if (len < 0)
  480. goto rewind;
  481. x = vmsvga_fifo_read(s);
  482. y = vmsvga_fifo_read(s);
  483. width = vmsvga_fifo_read(s);
  484. height = vmsvga_fifo_read(s);
  485. vmsvga_update_rect_delayed(s, x, y, width, height);
  486. break;
  487. case SVGA_CMD_RECT_FILL:
  488. len -= 6;
  489. if (len < 0)
  490. goto rewind;
  491. colour = vmsvga_fifo_read(s);
  492. x = vmsvga_fifo_read(s);
  493. y = vmsvga_fifo_read(s);
  494. width = vmsvga_fifo_read(s);
  495. height = vmsvga_fifo_read(s);
  496. #ifdef HW_FILL_ACCEL
  497. vmsvga_fill_rect(s, colour, x, y, width, height);
  498. break;
  499. #else
  500. args = 0;
  501. goto badcmd;
  502. #endif
  503. case SVGA_CMD_RECT_COPY:
  504. len -= 7;
  505. if (len < 0)
  506. goto rewind;
  507. x = vmsvga_fifo_read(s);
  508. y = vmsvga_fifo_read(s);
  509. dx = vmsvga_fifo_read(s);
  510. dy = vmsvga_fifo_read(s);
  511. width = vmsvga_fifo_read(s);
  512. height = vmsvga_fifo_read(s);
  513. #ifdef HW_RECT_ACCEL
  514. vmsvga_copy_rect(s, x, y, dx, dy, width, height);
  515. break;
  516. #else
  517. args = 0;
  518. goto badcmd;
  519. #endif
  520. case SVGA_CMD_DEFINE_CURSOR:
  521. len -= 8;
  522. if (len < 0)
  523. goto rewind;
  524. cursor.id = vmsvga_fifo_read(s);
  525. cursor.hot_x = vmsvga_fifo_read(s);
  526. cursor.hot_y = vmsvga_fifo_read(s);
  527. cursor.width = x = vmsvga_fifo_read(s);
  528. cursor.height = y = vmsvga_fifo_read(s);
  529. vmsvga_fifo_read(s);
  530. cursor.bpp = vmsvga_fifo_read(s);
  531. args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
  532. if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
  533. SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image)
  534. goto badcmd;
  535. len -= args;
  536. if (len < 0)
  537. goto rewind;
  538. for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
  539. cursor.mask[args] = vmsvga_fifo_read_raw(s);
  540. for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
  541. cursor.image[args] = vmsvga_fifo_read_raw(s);
  542. #ifdef HW_MOUSE_ACCEL
  543. vmsvga_cursor_define(s, &cursor);
  544. break;
  545. #else
  546. args = 0;
  547. goto badcmd;
  548. #endif
  549. /*
  550. * Other commands that we at least know the number of arguments
  551. * for so we can avoid FIFO desync if driver uses them illegally.
  552. */
  553. case SVGA_CMD_DEFINE_ALPHA_CURSOR:
  554. len -= 6;
  555. if (len < 0)
  556. goto rewind;
  557. vmsvga_fifo_read(s);
  558. vmsvga_fifo_read(s);
  559. vmsvga_fifo_read(s);
  560. x = vmsvga_fifo_read(s);
  561. y = vmsvga_fifo_read(s);
  562. args = x * y;
  563. goto badcmd;
  564. case SVGA_CMD_RECT_ROP_FILL:
  565. args = 6;
  566. goto badcmd;
  567. case SVGA_CMD_RECT_ROP_COPY:
  568. args = 7;
  569. goto badcmd;
  570. case SVGA_CMD_DRAW_GLYPH_CLIPPED:
  571. len -= 4;
  572. if (len < 0)
  573. goto rewind;
  574. vmsvga_fifo_read(s);
  575. vmsvga_fifo_read(s);
  576. args = 7 + (vmsvga_fifo_read(s) >> 2);
  577. goto badcmd;
  578. case SVGA_CMD_SURFACE_ALPHA_BLEND:
  579. args = 12;
  580. goto badcmd;
  581. /*
  582. * Other commands that are not listed as depending on any
  583. * CAPABILITIES bits, but are not described in the README either.
  584. */
  585. case SVGA_CMD_SURFACE_FILL:
  586. case SVGA_CMD_SURFACE_COPY:
  587. case SVGA_CMD_FRONT_ROP_FILL:
  588. case SVGA_CMD_FENCE:
  589. case SVGA_CMD_INVALID_CMD:
  590. break; /* Nop */
  591. default:
  592. args = 0;
  593. badcmd:
  594. len -= args;
  595. if (len < 0)
  596. goto rewind;
  597. while (args --)
  598. vmsvga_fifo_read(s);
  599. printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
  600. __FUNCTION__, cmd);
  601. break;
  602. rewind:
  603. s->cmd->stop = cmd_start;
  604. break;
  605. }
  606. }
  607. s->syncing = 0;
  608. }
  609. static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
  610. {
  611. struct vmsvga_state_s *s = opaque;
  612. return s->index;
  613. }
  614. static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
  615. {
  616. struct vmsvga_state_s *s = opaque;
  617. s->index = index;
  618. }
  619. static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
  620. {
  621. uint32_t caps;
  622. struct vmsvga_state_s *s = opaque;
  623. switch (s->index) {
  624. case SVGA_REG_ID:
  625. return s->svgaid;
  626. case SVGA_REG_ENABLE:
  627. return s->enable;
  628. case SVGA_REG_WIDTH:
  629. return s->width;
  630. case SVGA_REG_HEIGHT:
  631. return s->height;
  632. case SVGA_REG_MAX_WIDTH:
  633. return SVGA_MAX_WIDTH;
  634. case SVGA_REG_MAX_HEIGHT:
  635. return SVGA_MAX_HEIGHT;
  636. case SVGA_REG_DEPTH:
  637. return s->depth;
  638. case SVGA_REG_BITS_PER_PIXEL:
  639. return (s->depth + 7) & ~7;
  640. case SVGA_REG_PSEUDOCOLOR:
  641. return 0x0;
  642. case SVGA_REG_RED_MASK:
  643. return s->wred;
  644. case SVGA_REG_GREEN_MASK:
  645. return s->wgreen;
  646. case SVGA_REG_BLUE_MASK:
  647. return s->wblue;
  648. case SVGA_REG_BYTES_PER_LINE:
  649. return ((s->depth + 7) >> 3) * s->new_width;
  650. case SVGA_REG_FB_START: {
  651. struct pci_vmsvga_state_s *pci_vmsvga
  652. = container_of(s, struct pci_vmsvga_state_s, chip);
  653. return pci_get_bar_addr(&pci_vmsvga->card, 1);
  654. }
  655. case SVGA_REG_FB_OFFSET:
  656. return 0x0;
  657. case SVGA_REG_VRAM_SIZE:
  658. return s->vga.vram_size;
  659. case SVGA_REG_FB_SIZE:
  660. return s->fb_size;
  661. case SVGA_REG_CAPABILITIES:
  662. caps = SVGA_CAP_NONE;
  663. #ifdef HW_RECT_ACCEL
  664. caps |= SVGA_CAP_RECT_COPY;
  665. #endif
  666. #ifdef HW_FILL_ACCEL
  667. caps |= SVGA_CAP_RECT_FILL;
  668. #endif
  669. #ifdef HW_MOUSE_ACCEL
  670. if (s->vga.ds->mouse_set)
  671. caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
  672. SVGA_CAP_CURSOR_BYPASS;
  673. #endif
  674. return caps;
  675. case SVGA_REG_MEM_START: {
  676. struct pci_vmsvga_state_s *pci_vmsvga
  677. = container_of(s, struct pci_vmsvga_state_s, chip);
  678. return pci_get_bar_addr(&pci_vmsvga->card, 2);
  679. }
  680. case SVGA_REG_MEM_SIZE:
  681. return s->fifo_size;
  682. case SVGA_REG_CONFIG_DONE:
  683. return s->config;
  684. case SVGA_REG_SYNC:
  685. case SVGA_REG_BUSY:
  686. return s->syncing;
  687. case SVGA_REG_GUEST_ID:
  688. return s->guest;
  689. case SVGA_REG_CURSOR_ID:
  690. return s->cursor.id;
  691. case SVGA_REG_CURSOR_X:
  692. return s->cursor.x;
  693. case SVGA_REG_CURSOR_Y:
  694. return s->cursor.x;
  695. case SVGA_REG_CURSOR_ON:
  696. return s->cursor.on;
  697. case SVGA_REG_HOST_BITS_PER_PIXEL:
  698. return (s->depth + 7) & ~7;
  699. case SVGA_REG_SCRATCH_SIZE:
  700. return s->scratch_size;
  701. case SVGA_REG_MEM_REGS:
  702. case SVGA_REG_NUM_DISPLAYS:
  703. case SVGA_REG_PITCHLOCK:
  704. case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
  705. return 0;
  706. default:
  707. if (s->index >= SVGA_SCRATCH_BASE &&
  708. s->index < SVGA_SCRATCH_BASE + s->scratch_size)
  709. return s->scratch[s->index - SVGA_SCRATCH_BASE];
  710. printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
  711. }
  712. return 0;
  713. }
  714. static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
  715. {
  716. struct vmsvga_state_s *s = opaque;
  717. switch (s->index) {
  718. case SVGA_REG_ID:
  719. if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
  720. s->svgaid = value;
  721. break;
  722. case SVGA_REG_ENABLE:
  723. s->enable = value;
  724. s->config &= !!value;
  725. s->width = -1;
  726. s->height = -1;
  727. s->invalidated = 1;
  728. s->vga.invalidate(&s->vga);
  729. if (s->enable) {
  730. s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
  731. vga_dirty_log_stop(&s->vga);
  732. } else {
  733. vga_dirty_log_start(&s->vga);
  734. }
  735. break;
  736. case SVGA_REG_WIDTH:
  737. s->new_width = value;
  738. s->invalidated = 1;
  739. break;
  740. case SVGA_REG_HEIGHT:
  741. s->new_height = value;
  742. s->invalidated = 1;
  743. break;
  744. case SVGA_REG_DEPTH:
  745. case SVGA_REG_BITS_PER_PIXEL:
  746. if (value != s->depth) {
  747. printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
  748. s->config = 0;
  749. }
  750. break;
  751. case SVGA_REG_CONFIG_DONE:
  752. if (value) {
  753. s->fifo = (uint32_t *) s->fifo_ptr;
  754. /* Check range and alignment. */
  755. if ((CMD(min) | CMD(max) |
  756. CMD(next_cmd) | CMD(stop)) & 3)
  757. break;
  758. if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
  759. break;
  760. if (CMD(max) > SVGA_FIFO_SIZE)
  761. break;
  762. if (CMD(max) < CMD(min) + 10 * 1024)
  763. break;
  764. }
  765. s->config = !!value;
  766. break;
  767. case SVGA_REG_SYNC:
  768. s->syncing = 1;
  769. vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
  770. break;
  771. case SVGA_REG_GUEST_ID:
  772. s->guest = value;
  773. #ifdef VERBOSE
  774. if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
  775. ARRAY_SIZE(vmsvga_guest_id))
  776. printf("%s: guest runs %s.\n", __FUNCTION__,
  777. vmsvga_guest_id[value - GUEST_OS_BASE]);
  778. #endif
  779. break;
  780. case SVGA_REG_CURSOR_ID:
  781. s->cursor.id = value;
  782. break;
  783. case SVGA_REG_CURSOR_X:
  784. s->cursor.x = value;
  785. break;
  786. case SVGA_REG_CURSOR_Y:
  787. s->cursor.y = value;
  788. break;
  789. case SVGA_REG_CURSOR_ON:
  790. s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
  791. s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
  792. #ifdef HW_MOUSE_ACCEL
  793. if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
  794. s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
  795. #endif
  796. break;
  797. case SVGA_REG_MEM_REGS:
  798. case SVGA_REG_NUM_DISPLAYS:
  799. case SVGA_REG_PITCHLOCK:
  800. case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
  801. break;
  802. default:
  803. if (s->index >= SVGA_SCRATCH_BASE &&
  804. s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
  805. s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
  806. break;
  807. }
  808. printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
  809. }
  810. }
  811. static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
  812. {
  813. printf("%s: what are we supposed to return?\n", __FUNCTION__);
  814. return 0xcafe;
  815. }
  816. static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
  817. {
  818. printf("%s: what are we supposed to do with (%08x)?\n",
  819. __FUNCTION__, data);
  820. }
  821. static inline void vmsvga_size(struct vmsvga_state_s *s)
  822. {
  823. if (s->new_width != s->width || s->new_height != s->height) {
  824. s->width = s->new_width;
  825. s->height = s->new_height;
  826. qemu_console_resize(s->vga.ds, s->width, s->height);
  827. s->invalidated = 1;
  828. }
  829. }
  830. static void vmsvga_update_display(void *opaque)
  831. {
  832. struct vmsvga_state_s *s = opaque;
  833. if (!s->enable) {
  834. s->vga.update(&s->vga);
  835. return;
  836. }
  837. vmsvga_size(s);
  838. vmsvga_fifo_run(s);
  839. vmsvga_update_rect_flush(s);
  840. /*
  841. * Is it more efficient to look at vram VGA-dirty bits or wait
  842. * for the driver to issue SVGA_CMD_UPDATE?
  843. */
  844. if (s->invalidated) {
  845. s->invalidated = 0;
  846. vmsvga_update_screen(s);
  847. }
  848. }
  849. static void vmsvga_reset(DeviceState *dev)
  850. {
  851. struct pci_vmsvga_state_s *pci =
  852. DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
  853. struct vmsvga_state_s *s = &pci->chip;
  854. s->index = 0;
  855. s->enable = 0;
  856. s->config = 0;
  857. s->width = -1;
  858. s->height = -1;
  859. s->svgaid = SVGA_ID;
  860. s->cursor.on = 0;
  861. s->redraw_fifo_first = 0;
  862. s->redraw_fifo_last = 0;
  863. s->syncing = 0;
  864. vga_dirty_log_start(&s->vga);
  865. }
  866. static void vmsvga_invalidate_display(void *opaque)
  867. {
  868. struct vmsvga_state_s *s = opaque;
  869. if (!s->enable) {
  870. s->vga.invalidate(&s->vga);
  871. return;
  872. }
  873. s->invalidated = 1;
  874. }
  875. /* save the vga display in a PPM image even if no display is
  876. available */
  877. static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch)
  878. {
  879. struct vmsvga_state_s *s = opaque;
  880. if (!s->enable) {
  881. s->vga.screen_dump(&s->vga, filename, cswitch);
  882. return;
  883. }
  884. if (s->depth == 32) {
  885. DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
  886. s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
  887. ppm_save(filename, ds);
  888. g_free(ds);
  889. }
  890. }
  891. static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
  892. {
  893. struct vmsvga_state_s *s = opaque;
  894. if (s->vga.text_update)
  895. s->vga.text_update(&s->vga, chardata);
  896. }
  897. static int vmsvga_post_load(void *opaque, int version_id)
  898. {
  899. struct vmsvga_state_s *s = opaque;
  900. s->invalidated = 1;
  901. if (s->config)
  902. s->fifo = (uint32_t *) s->fifo_ptr;
  903. return 0;
  904. }
  905. static const VMStateDescription vmstate_vmware_vga_internal = {
  906. .name = "vmware_vga_internal",
  907. .version_id = 0,
  908. .minimum_version_id = 0,
  909. .minimum_version_id_old = 0,
  910. .post_load = vmsvga_post_load,
  911. .fields = (VMStateField []) {
  912. VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
  913. VMSTATE_INT32(enable, struct vmsvga_state_s),
  914. VMSTATE_INT32(config, struct vmsvga_state_s),
  915. VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
  916. VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
  917. VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
  918. VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
  919. VMSTATE_INT32(index, struct vmsvga_state_s),
  920. VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
  921. scratch_size, 0, vmstate_info_uint32, uint32_t),
  922. VMSTATE_INT32(new_width, struct vmsvga_state_s),
  923. VMSTATE_INT32(new_height, struct vmsvga_state_s),
  924. VMSTATE_UINT32(guest, struct vmsvga_state_s),
  925. VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
  926. VMSTATE_INT32(syncing, struct vmsvga_state_s),
  927. VMSTATE_INT32(fb_size, struct vmsvga_state_s),
  928. VMSTATE_END_OF_LIST()
  929. }
  930. };
  931. static const VMStateDescription vmstate_vmware_vga = {
  932. .name = "vmware_vga",
  933. .version_id = 0,
  934. .minimum_version_id = 0,
  935. .minimum_version_id_old = 0,
  936. .fields = (VMStateField []) {
  937. VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
  938. VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
  939. vmstate_vmware_vga_internal, struct vmsvga_state_s),
  940. VMSTATE_END_OF_LIST()
  941. }
  942. };
  943. static void vmsvga_init(struct vmsvga_state_s *s,
  944. MemoryRegion *address_space, MemoryRegion *io)
  945. {
  946. s->scratch_size = SVGA_SCRATCH_SIZE;
  947. s->scratch = g_malloc(s->scratch_size * 4);
  948. s->vga.ds = graphic_console_init(vmsvga_update_display,
  949. vmsvga_invalidate_display,
  950. vmsvga_screen_dump,
  951. vmsvga_text_update, s);
  952. s->fifo_size = SVGA_FIFO_SIZE;
  953. memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
  954. vmstate_register_ram_global(&s->fifo_ram);
  955. s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
  956. vga_common_init(&s->vga);
  957. vga_init(&s->vga, address_space, io, true);
  958. vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
  959. s->depth = ds_get_bits_per_pixel(s->vga.ds);
  960. s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
  961. switch (s->depth) {
  962. case 8:
  963. s->wred = 0x00000007;
  964. s->wgreen = 0x00000038;
  965. s->wblue = 0x000000c0;
  966. break;
  967. case 15:
  968. s->wred = 0x0000001f;
  969. s->wgreen = 0x000003e0;
  970. s->wblue = 0x00007c00;
  971. break;
  972. case 16:
  973. s->wred = 0x0000001f;
  974. s->wgreen = 0x000007e0;
  975. s->wblue = 0x0000f800;
  976. break;
  977. case 24:
  978. s->wred = 0x00ff0000;
  979. s->wgreen = 0x0000ff00;
  980. s->wblue = 0x000000ff;
  981. break;
  982. case 32:
  983. s->wred = 0x00ff0000;
  984. s->wgreen = 0x0000ff00;
  985. s->wblue = 0x000000ff;
  986. break;
  987. }
  988. }
  989. static uint64_t vmsvga_io_read(void *opaque, target_phys_addr_t addr,
  990. unsigned size)
  991. {
  992. struct vmsvga_state_s *s = opaque;
  993. switch (addr) {
  994. case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
  995. case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
  996. case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
  997. default: return -1u;
  998. }
  999. }
  1000. static void vmsvga_io_write(void *opaque, target_phys_addr_t addr,
  1001. uint64_t data, unsigned size)
  1002. {
  1003. struct vmsvga_state_s *s = opaque;
  1004. switch (addr) {
  1005. case SVGA_IO_MUL * SVGA_INDEX_PORT:
  1006. vmsvga_index_write(s, addr, data);
  1007. break;
  1008. case SVGA_IO_MUL * SVGA_VALUE_PORT:
  1009. vmsvga_value_write(s, addr, data);
  1010. break;
  1011. case SVGA_IO_MUL * SVGA_BIOS_PORT:
  1012. vmsvga_bios_write(s, addr, data);
  1013. break;
  1014. }
  1015. }
  1016. static const MemoryRegionOps vmsvga_io_ops = {
  1017. .read = vmsvga_io_read,
  1018. .write = vmsvga_io_write,
  1019. .endianness = DEVICE_LITTLE_ENDIAN,
  1020. .valid = {
  1021. .min_access_size = 4,
  1022. .max_access_size = 4,
  1023. },
  1024. };
  1025. static int pci_vmsvga_initfn(PCIDevice *dev)
  1026. {
  1027. struct pci_vmsvga_state_s *s =
  1028. DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
  1029. MemoryRegion *iomem;
  1030. iomem = &s->chip.vga.vram;
  1031. s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
  1032. s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
  1033. s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
  1034. memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
  1035. "vmsvga-io", 0x10);
  1036. pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
  1037. vmsvga_init(&s->chip, pci_address_space(dev),
  1038. pci_address_space_io(dev));
  1039. pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
  1040. pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
  1041. &s->chip.fifo_ram);
  1042. if (!dev->rom_bar) {
  1043. /* compatibility with pc-0.13 and older */
  1044. vga_init_vbe(&s->chip.vga, pci_address_space(dev));
  1045. }
  1046. return 0;
  1047. }
  1048. static Property vga_vmware_properties[] = {
  1049. DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
  1050. chip.vga.vram_size_mb, 16),
  1051. DEFINE_PROP_END_OF_LIST(),
  1052. };
  1053. static void vmsvga_class_init(ObjectClass *klass, void *data)
  1054. {
  1055. DeviceClass *dc = DEVICE_CLASS(klass);
  1056. PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  1057. k->no_hotplug = 1;
  1058. k->init = pci_vmsvga_initfn;
  1059. k->romfile = "vgabios-vmware.bin";
  1060. k->vendor_id = PCI_VENDOR_ID_VMWARE;
  1061. k->device_id = SVGA_PCI_DEVICE_ID;
  1062. k->class_id = PCI_CLASS_DISPLAY_VGA;
  1063. k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
  1064. k->subsystem_id = SVGA_PCI_DEVICE_ID;
  1065. dc->reset = vmsvga_reset;
  1066. dc->vmsd = &vmstate_vmware_vga;
  1067. dc->props = vga_vmware_properties;
  1068. }
  1069. static TypeInfo vmsvga_info = {
  1070. .name = "vmware-svga",
  1071. .parent = TYPE_PCI_DEVICE,
  1072. .instance_size = sizeof(struct pci_vmsvga_state_s),
  1073. .class_init = vmsvga_class_init,
  1074. };
  1075. static void vmsvga_register_types(void)
  1076. {
  1077. type_register_static(&vmsvga_info);
  1078. }
  1079. type_init(vmsvga_register_types)